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I. INTRODUCTION
Manuscript received January 11, 2013; accepted January 22, 2013. Date of
publication March 26, 2013; date of current version April 02, 2013. This work
was supported by 973 (2009CB320403), the Natural Science Foundation of
Shanghai under Grant 10ZR1416600, the Doctoral Fund of Ministry of Education of China under Grant 20090073120033, the National Science and Technology Major Project of the Ministry of Science under Grant 2011ZX03001007-03, and the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry.
The authors are with the Department of Electronics Engineering, Shanghai
Jiao Tong University, Shanghai 200240, China (e-mail: hbydtjj@gmail.com).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LAWP.2013.2253303
(1)
TANG et al.: GENERAL METHOD FOR MODELING PACKAGED DIODE SPANNING MULTIPLE CELLS IN FDTD
393
(2)
where
(9)
According to the principle of time average and central difference, and
at time-step
can be estimated from
the corresponding values at time-step and
, described as
(10)
(3)
(11)
can be 1 to determine the polarity of the lumped network
referred to the
component as shown in Fig. 1.
The current density generated by the lumped network has the
expression
(4)
Meanwhile, the voltage of the lumped network can be modeled as a line integral of electric fields
(5)
A Schottky barrier diode (MA4E1317) with equivalent circuit as shown in Fig. 2 is analyzed in this letter. The circuit includes four voltage-independent elements
and
two nonlinear voltage-dependent elements
, while ,
, and
are not considered in the equivalent circuit of diode
in [5]. In [10], the relationships of
and
branches are
derived respectively according to
(7)
(14)
(13)
(6)
..
.
..
394
TABLE I
ELEMENT VALUE OF THE EQUIVALENT CIRCUIT OF DIODE MA4E1317
where
(15)
(16)
(17)
and the measured -parameters are used to specify the value of
each element, as listed in Table I.
The method proposed in [5] can achieve simulation efficiency
by deducing the explicit form of the relationship at the devices port. However, when it is applied to analyze MA4E1317
with an equivalent circuit shown in Fig. 2, the explicit form is
complicated.
To verify the proposed method in this letter, the microstrip circuit in Fig. 3 is simulated with a self-written MATLAB FDTD
field solver based on Section II. The diode is along -direction, connecting the ground and microstrip. The Yee cell size
is 0.4 mm in -direction and 0.55 mm in -direction. The thickness of the microstrip substrate is 0.795 mm. We have studied
two meshing schemes according to the number of cells the substrate is discretized into in -direction. One is three cells with
ps, and the other is nine cells with
ps
based on CFL stability criterion. The excitation is a resistive
sinusoidal voltage source whose amplitude is 20 V, operation
frequency is 5.8 GHz, and source resistance is 50 .
Fig. 4. Voltage across the diode. (a) Case (9, 1). (b) Cases (9, 3) and (3, 1).
(c) Cases (9, 9) and (3, 3).
TANG et al.: GENERAL METHOD FOR MODELING PACKAGED DIODE SPANNING MULTIPLE CELLS IN FDTD
395
For case (3, 3), 38 203 time-steps are simulated, and voltage
across the diode is shown in Fig. 5. It suggests that this method
can achieve stability.
IV. CONCLUSION
This letter extends the MNA to embed the electric fields of
multiple FDTD cells where circuit elements span. A general
method to fill the nodal matrix is derived so that it can be conveniently applied to analyze arbitrary two-terminal devices with
complicated equivalent circuits. The proposed method is verified through a packaged Schottky barrier diode computation,
and the result is in good agreement with the one obtained from
the commercial software ADS.
REFERENCES
Fig. 5. Voltage across the diode of case (3, 3).
We use
to denote the simulation case that the microstrip substrate is discretized into cells and the diode spans
cells with the other
cells treated as PEC. Five cases
are analyzed, including (3, 1), (3, 3), (9, 1), (9, 3), and (9, 9).
The voltage across the diode is recorded and compared to this
attained by the commercial circuit simulation package ADS. In
Fig. 4(a), case (9, 1) shows great discrepancy with ADS for this
case treating eight cells as PEC, the longest one among the five
studied cases, which would introduce the greatest numerical inductance. PEC modeling in case (9, 3) is the same length as
the case (3, 1). Fig. 4(b) indicates that results of cases (9, 3)
and (3, 1) are the same. Although the results are closer to ADS
than case (9, 1), the discrepancies at the positive and negative
peaks are not negligible as PEC is used to connect the diode and
ground. In Fig. 4(c), cases (9, 9) and (3, 3) share the same accuracy. As there is no PEC modeling in cases (9, 9) and (3, 3), the
results are in better agreement with ADS than cases (9, 1), (3, 1),
and (9, 3). A more accurate simulation result can be achieved
when is equal to .
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