Question 1

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<p>This is examined first whenever

<p>RISC has the following features

the processor tries to read data from

except for</p>

the main memory. </p>

RISC has the following features except

This is examined first whenever the

for

processor tries to read data from the

main memory.

A. Reduce accesses to main memory

A. Main Memory

B. Make good use of registers

B. Instructions

C. Utilize the compiler extensively

C. Cache

D. Instructions reequire multiple clock

cycles to execute
D. Registers

IncorrectQuestion 2

Question 3

D. Cache

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<p>This helps identify possible
interruptions to the normal flow of
instructions through U and V
pipelines.</p>
This helps identify possible interruptions
to the normal flow of instructions
through U and V pipelines.

A. Pentium

B. Branch Prediction

C. Pipelining

IncorrectQuestion 4
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<p>Pentium processors employs
how many types of pipelines?</p>
Pentium processors employs how many
types of pipelines?

A. 20

B. 14

C. 2

D. 5

C. write after write

IncorrectQuestion 5

D. read after read

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<p>What type of dependency exists
between these two
instructions?<br>SUB DX,
CX<br>ADD BX, DX</p>
What type of dependency exists
between these two instructions?
SUB DX, CX
ADD BX, DX

A. read after write

B. write after read

IncorrectQuestion 6
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<p>Which of the following is not part
of the transitions between bus cycle
states?</p>
Which of the following is not part of the
transitions between bus cycle states?

A. No bus cycle requested

B. Go back to T1 if a new request is

pending
B. T12

C. Valid adddress is output on the

address lines

D. Begin second bys cycle

IncorrectQuestion 7
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<p>This bus state indicates that no
bus cycle is currently running.</p>
This bus state indicates that no bus
cycle is currently running.

C. TD

D. Ti

Question 8
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<p>The bus will enter this state when
a second bus cycle is started before
the first one completes.</p>
The bus will enter this state when a
second bus cycle is started before the

A. T1

first one completes.

This bus cycles require additional

A. T1

decoding and use the byte enable

outputs for selection.

B. T12

A. Bus Cycle States

C. TD

B. Single Transfer Cycle

D. Ti

C. Burst Cycle

Question 9

D. Special Cycle

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<p>This bus cycles require additional
decoding and use the byte enable
outputs for selection.</p>

Question 10
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<p>This cycle transfers bytes that are

Question 11

non-cacheable between the

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processor and memory.</p>

<p>These are extra clock cycles

This cycle transfers bytes that are non-

generated when BDRY is not low

cacheable between the processor and

during T2 state.</p>

memory.

These are extra clock cycles generated

when BDRY is not low during T2 state.

A. Single Transfer Cycle

A. Idle States

B. Burst Cycle
B. Wait states

C. Bus Cycle State

C. Dead states

D. Special Cycle
D. Bus cycle states

Question 12

IncorrectQuestion 13

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<p>This cycle is used by the cache

<p>During this operation, no other

for line loads and writebacks.</p>

devices may take over control of the

This cycle is used by the cache for line

processsor buses.</p>

loads and writebacks.

During this operation, no other devices

may take over control of the processsor

A. Single Transfer Cycle

buses.

A. Locked Operation
B. Burst Cycle

B. Bus Snooping
C. Bus Cycle State

C. Atomic Operation
D. Special Cycle

D. Branch Prediction

C. Atomic Operation

Question 14

D. Semaphor

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<p>This is a special type of counter
variable that must be read, updated,
stored in one single, uninterruptable
operation.</p>
This is a special type of counter variable
that must be read, updated, stored in
one single, uninterruptable operation.

Question 15
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<p>This put its buses into a highimpedance state, beginning with the
next clock cycle.</p>
This put its buses into a high-impedance
state, beginning with the next clock

A. Locked Operation

cycle.

A. HLT
B. Atomic Access

B. BOFF

B. BOFF

C. Shutdown
C. Shutdown

D. Bus Hold
D. Bus Hold

Question 16
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Question 17

<p>This completes the current bus

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cycle and then tri-states its

<p>This cycle is run when the

buses.</p>

processor encounters the HLT

This completes the current bus cycle

instruction.</p>

and then tri-states its buses.

This cycle is run when the processor

encounters the HLT instruction.

A. HLT
A. HLT

B. BOFF

B. BOFF

C. Shutdown

C. Shutdown

D. Bus Hold

D. Bus Hold

Question 18

Question 19

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<p>This cycle is run if the Pentium

<p>In this cycle the Pentium

detects an internal parity error.</p>

processor is able to watch the

This cycle is run if the Pentium detects

system bus in a multiprocessor

an internal parity error.

system.</p>
In this cycle the Pentium processor is

A. HLT

able to watch the system bus in a

multiprocessor system.

Under special circumstances, this is

A. Inquire Cycles

capable of executing two integer or two

floating-point instructions
simultaneously.

B. Bus Snooping
A. Pentium

C. Pipelined Cycles
B. Pentium II

D. Cache Coherency
C. Pentium III

Question 20
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D. Pentium IV

<p>Under special circumstances, this

is capable of executing two integer or
two floating-point instructions
simultaneously.</p>

IncorrectQuestion 21
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<p>Which among the choices is not

one of the restrictions placed on a

D. Neither instruction may contain both

pair of integer instructions

immediate data and a displacement

attempting parallel execution?</p>

value

Which among the choices is not one of

the restrictions placed on a pair of
integer instructions attempting parallel

IncorrectQuestion 22

execution?
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<p>This data dependency exists if
A. Both must be simple instructions

the second instruction reads an

operand written to it by the first
instruction.</p>

B. No data dependencies may exist

between them

This data dependency exists if the

second instruction reads an operand
written to it by the first instruction.

C. Postfixed instructions may only

A. read after read

execute in the U pipeline

B. write after write

B. write after write

C. write after read

C. write after read

D. read after write

D. read after write

IncorrectQuestion 23
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Question 24

<p>This data dependecy exists if

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both instruction write to the same

<p>This stage in pipelining is used to

operand</p>

write the results of the completed

This data dependecy exists if both

instruction and verify conditional

instruction write to the same operand

branch instruction predictions.</p>

This stage in pipelining is used to write

A. read after read

the results of the completed instruction

and verify conditional branch instruction
predictions.

Pentium uses this scheme to avoid

A. WB

bubbles in the pipeline, where no work

is done as the pipeline stages are
reloaded.

B. D1
A. branch prediction

C. D2
B. branch target buffer

D. EX
C. dynamic branch prediction

Question 25
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D. branch instruction

<p>Pentium uses this scheme to

avoid bubbles in the pipeline, where
no work is done as the pipeline
stages are reloaded.</p>

Question 26
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<p>The history bits are initially set to

D. 01

01, what will be the history bits after

this sequence; Taken-&gt;Taken&gt;Not Taken-&gt;Not Taken-&gt;Not

IncorrectQuestion 27

Taken-&gt;Taken?</p>
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The history bits are initially set to 01,
<p>The history bits are initially set to
what will be the history bits after this
10, what will be the history bits after
sequence; Taken->Taken->Not Takenthis sequence; Taken-&gt;Taken>Not Taken->Not Taken->Taken?
&gt;Not Taken-&gt;Not Taken-&gt;Not
Taken-&gt;Taken?</p>
A. 00

The history bits are initially set to 10,

what will be the history bits after this
sequence; Taken->Taken->Not Taken-

B. 10

>Not Taken->Not Taken->Taken?

A. 00
C. 11

B. 10

C. 11

C. access time

D. 01

D. hit ratio

Question 28

Question 29

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<p>This specifies the percentage of

<p>This cache organization uses

hits to total cache accesses.</p>

larger tags and does not select an

This specifies the percentage of hits to

entry based on index bits.</p>

total cache accesses.

This cache organization uses larger tags

and does not select an entry based on

A. hit

index bits.

A. fully associative cache

B. miss

B. set associative cache

B. set associative cache

C. direct-mapped cache

C. direct-mapped cache
D. single-mapped cache

D. single-mapped cache
Question 30
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<p>This cache organization uses a
portion of the incoming physical
address to select an entry.</p>
This cache organization uses a portion
of the incoming physical address to
select an entry.

Question 31
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<p>This state of cache line has been
modified and is only available in a
single cache.</p>
This state of cache line has been
modified and is only available in a single

A. fully associative cache

cache.

This state of cache line may invalidate

A. Modified

the copies in the other cache of the

current line during once a write occur.

B. Exclusive

A. Modified

C. Shared

B. Exclusive

D. Invalid

C. Shared

Question 32

D. Invalid

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<p>This state of cache line may
invalidate the copies in the other
cache of the current line during once
a write occur.</p>

Question 33
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<p>This is the FPU pipeline stage

were memory data are converted into
floating-point format and write the

Question 34

operand to floating-point file.</p>

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This is the FPU pipeline stage were
<p>What is the average access time
memory data are converted into floatingfor a system that contains 15ns
point format and write the operand to
cache and 75ns RAM if the hit ration
floating-point file.
is 0.89?</p>
What is the average access time for a
A. EX

system that contains 15ns cache and

75ns RAM if the hit ration is 0.89?

B. X1

A. 276.9ns

C. X2

B. 12103.11ns

D. WF

C. 23.25ns

D. 1211.4ns

C. 84.35

IncorrectQuestion 35

D. 1825.36.4ns

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<p>What is the average access time
for a system that contains 18ns
cache and 78ns RAM if the hit ration
is 0.98?</p>
What is the average access time for a
system that contains 18ns cache and
78ns RAM if the hit ration is 0.98?

A. 1695.36ns

B. 19.56ns

Question 36
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<p>This translate linear addresses
into physical addresses.</p>
This translate linear addresses into
physical addresses.

A. TLB

B. TLS

B. Cache Coherency
C. TLC

C. MESI
D. TLT

D. Translation lookaside buffer

Question 37
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<p>This is a Pentium's mechanism

IncorrectQuestion 38

that is used to maintain cache

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coherency in its data cache.</p>

<p>What happens during a cache

This is a Pentium's mechanism that is

miss?</p>

used to maintain cache coherency in its

What happens during a cache miss?

data cache.
A. a copy is sent to the pipeline very
A. Bus Snooping

quickly, usally within one clock cycle.

B. the processor will not be forced to go

A. superpipeline

to external memory

B. internal level-2 cache

C. an external cache is examined next

C. five additional address lines

D. a copy of the instruction or data from
main memory is read to the cache
D. dual independent bus

Question 39
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<p>All of these are the reasons why
Pentium Pro outperformed Pentium
except for:</p>
All of these are the reasons why
Pentium Pro outperformed Pentium
except for:

IncorrectQuestion 40
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<p>This is used to detect and correct
single bit errors on the data bus and
detect bit errors on the address bus
and control signals.</p>

This is used to detect and correct single

<p>This technology is used to keep

bit errors on the data bus and detect bit

instruction pipeline busy.</p>

errors on the address bus and control

This technology is used to keep

signals.

instruction pipeline busy.

A. Error Detection

A. Dynamic Execution

B. Parity Check

B. Pipelining

C. Register Renaming

C. Speculative Execution

D. Error Checking and Correction

D. Speculative Loading

Question 41

Question 42

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<p>This unit is used to determine

IncorrectQuestion 43

which original 1A-32 register must be

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updated in program order.</p>

<p>In this unit the reservation station

This unit is used to determine which

controls the flow of data through the

original 1A-32 register must be updated

integer, floating-point, MMX, and

in program order.

load/store unit</p>
In this unit the reservation station

A. Fetch-Decode Unit

controls the flow of data through the

integer, floating-point, MMX, and
load/store unit

B. Retire Unit
A. Fetch-Decode Unit

C. Dispatch-Execute Unit
B. Retire Unit

D. MMX execution Unit

C. Dispatch-Execute Unit

C. Streaming SIMD Extensions

D. MMX execution Unit

D. Speculative Loading
Question 44
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<p>This is used to preload the data
cache with data the application is
expected to need.</p>
This is used to preload the data cache
with data the application is expected to
need.

Question 45
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<p>This technology enables one
instructions to perform its work on
multiple operands
simultaneously.</p>
This technology enables one

A. Data Prefetch Logic

instructions to perform its work on

multiple operands simultaneously.

B. Speculative Execution

A. SIMD

B. SSE

B. Superpipeline
C. Superscalar Machines

C. Hyper-Pipelined
D. Streaming SIMD Extensions

D. FPU Pipelining
Question 46
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<p>This allows the use of minimal
logic in each stage and a higher
clock speed for the pipeline.</p>
This allows the use of minimal logic in
each stage and a higher clock speed for
the pipeline.

Question 47
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<p>This is used to save decoding
time if the same instruction is fetched
in the future.</p>
This is used to save decoding time if the
same instruction is fetched in the future.

A. Pipelining

A. MMX Technology

B. Pentium II
B. Exectution Trace Cache

C. Pentium III
C. Dual Independent Bus

D. Penitum IV
D. Rapid Execution Engine

Question 49
Question 48

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<p>This processor allows true

<p>This processor supports

simultaneous execution of two

hyperthreading.</p>

threads at the same time</p>

This processor supports hyperthreading.

This processor allows true simultaneous

execution of two threads at the same

A. Pentium

time

A. Pentium

A. Brand Prediction

B. Itanium

B. Loop Unrolling

C. Celeron

C. Predication

D. Xeon

D. Looping technique

Question 50

Question 51

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<p>This is used to duplicate the

<p>In this technique data is

instructions found within a loop.</p>

preloaded before it is needed.</p>

This is used to duplicate the instructions

In this technique data is preloaded

found within a loop.

before it is needed.

04<br>ADD AX, CX<br>INC

A. Data Prefetch Logic

BX<br>SUB BX, AX<br>MOV CX,

BX<br>DEC CX</p>
Compute for the number of clock cycles

B. Speculative Execution

of the following instructions in UV

pipelining.

MOV AX, 02
C. Streaming SIMD Extensions

MOV BX, 03
MOV CX, 04
ADD AX, CX
INC BX

D. Speculative Loading
SUB BX, AX
MOV CX, BX
DEC CX
Question 52
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A. 60
<p>Compute for the number of clock
cycles of the following instructions in
UV pipelining.</p> <p>MOV AX,
02<br>MOV BX, 03<br>MOV CX,

B. 10

B. 60

C. 12
C. 19

D. 9
D. 10

IncorrectQuestion 53
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Question 54

<p>Compute for the number of clock

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cycles of 15 instructions in a 4-stage

<p>To reduce the number of

pipelining.</p>

accesses to main memory in

Compute for the number of clock cycles

RISC,one of the following has been

of 15 instructions in a 4-stage pipelining.

added to its design.</p>

To reduce the number of accesses to

A. 18

main memory in RISC,one of the

following has been added to its design.

A. Instruction Cache

This is the FPU pipeline state were

result are rounded and written to
floating-point register file.

B. Cache
A. EX

C. Floating point
B. X1

D. DMA
C. X2

Question 55
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D. WF

<p>This is the FPU pipeline state

were result are rounded and written
to floating-point register file.</p>

IncorrectQuestion 56
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<p>Compute for the number of clock

cycles of 15 instructions in nonpipelining.</p>
Compute for the number of clock cycles
of 15 instructions in non-pipelining.

A. 10

B. 60

C. 17

D. 45