1

Including Voltage Space Vector PWM in Undergraduate Courses

Ned Mohan, Waldemar Sulkowski, Philip Jose, Ted Brekken
1.

Objective

In undergraduate power electronics and electric drives courses, students are taught the sinusoidal pulsewidth-modulation (Sine-PWM) principle to synthesize desired output voltages of three-phase inverters. It
is also well known that the space vector PWM approach (SV-PWM) is better than the sinusoidal PWM
approach in utilizing the available dc-bus voltage by approximately 15% a significant difference.
However, SV-PWM is usually not covered due to its perceived complexity in implementation. The
purpose of this two-part article is first to present SV-PWM and then to simplify the explanation of how it
can be implemented using a similar carrier-based modulation as the Sine-PWM, and hence can be
included in undergraduate courses. A detailed description can be found in [1].
The inverter in Fig. 1 has three switching power-poles, each consisting of a bi-positional switch either
up or down. The object is to synthesize, by PWM, the average output of the inverter to be such that
the desired balanced set of voltages van (t ) , vbn (t ) , and vcn (t ) appears across the load, be it a motor stator

winding as shown in Fig. 1 for a counterclockwise rotation, or a UPS system, where

van (t ) + vbn (t ) + vcn (t ) = 0 . In this article, average refers to a voltage averaged over a switching timeperiod Ts (= 1/ f s ) and is indicated by lowercase v with a - on top, and explicitly shown to be a
function of time t .
+

2
3

Vd

n
c

e j0

4
3

Fig. 1 Three-phase inverter

Part 1: Voltage Space Vector PWM (SV-PWM)

In terms of the desired phase voltages, the voltage space vector can be written by multiplying phase
voltages by their phase orientations as in Fig. 1:
G
vs (t ) = van (t )e j 0 + vbn (t )e j 2 / 3 + vcn (t )e j 4 / 3
(1)
In Fig. 1, in terms of the switching power-pole output voltages with respect to the negative dc bus
van = vaN + vNn ; vbn = vbN + vNn ; vcn = vcN + vNn ;

(2)

Substituting Eq. 2 into Eq. 1 and recognizing that e j 0 + e j 2 / 3 + e j 4 / 3 = 0 , the voltage space vector can be
written in terms of the switching power-pole average output voltages as
G
vs (t ) = vaN (t )e j 0 + vbN (t )e j 2 / 3 + vcN (t )e j 4 / 3
(3)

A switch in a switching power-pole of Fig. 1 is either up or down, with the instantaneous output
voltage either 1 or 0 times Vd . With three poles, eight switch-status combinations are possible. In Eq. 3,
the voltage space vector can instantly take on one of the following seven distinct instantaneous values as
shown in Table 1, where phase "a" is represented by the least significant digit and phase c by the most
significant digit.
Table 1 Instantaneous Basic Voltage Vectors.
Basic Vector
Value
Switch State
c
b
a
G
v0 (000)
0
0
0
0
G
v1 (001)
Vd e j 0
0
0
1

G
v2 (010)

Vd e

G
v3 (011)

Vd e

G
v4 (100)

Vd e

G
v5 (101)

Vd e

G
v6 (110)
G
v7 (111)

2
3

4
3

5
3

Vd e j

G
G
In Table 1, v0 and v7 are the zero vectors because of their values. The resulting instantaneous voltage

vectors, which we will call the basic vectors, are shown in Fig. 2a forming six sectors.
The average voltage vector is synthesized by time-weighted averaging of the two adjacent basic non-zero
voltage vectors that form the sector (in which the average voltage vector to be synthesized lies) but using
both the zero vectors of equal duration. We will begin by synthesizing the average voltage vector in
G
G
G
sector 1, as shown in by vs (t ) in Fig. 2b. The adjacent basic vectors v1 and v3 are applied for intervals
G
G
xTs and yTs respectively, and the zero vectors v0 and v7 are applied for a duration 2z Ts each. By timeweighted averaging
1
G
G
G
G
G
vs (t ) = [ xTs v1 + yTs v3 + zTs 0] = xv1 + yv3
Ts

(4)

where, x + y + z = 1 . In Eq. 4, expressing the basic vectors in terms of their amplitude and phase angles
results in

G
vs (t ) = Vs e j s (t ) = Vd ( xe j 0 + ye j / 3 )
(5)
G
From Fig. 2b and Eq. 5 for vs (t ) , it is clear that the ratio y / x dictates the orientation s , and introducing
the zero-voltage interval z (= 1 x y ) controls the amplitude Vs . At the limit, where z = 0 and hence,
x + y = 1 , the tips of the voltage space vectors lie on the straight line connecting the two non-zero basic
vectors in Fig. 2b. However, normally the three voltages to be synthesized vary sinusoidally in time,
G
resulting in a rotating voltage space vector vs (t ) of constant amplitude. At the limit, shown by the
dashed circle in Fig. 2b, this amplitude has a maximum value

(V )
s

max

3
= Vd cos( ) =
Vd
6
2

b axis

(6)
G
v3 (011)

G
v2 (010)
II
I

III

G
v6 (110)

IV

G
vG7 (111) = 0
v0 (000) = 0

VI

j
G
v3 = V d e 3

G
vs
G
v1 (001)

a axis

G
y v3

G
v4 (100)

c axis

Vs ,max
G
vs
s

G
v5 (101)
(a)

G
v1 = Vd e j 0

G
x v1
(b)

G
Fig. 2 Instantaneous basic vectors and synthesis of vs (t ) .

Therefore the corresponding phase voltage peak,

2
3

times the space vector peak, has the following

maximum from Eq. 6

V
Va
= d
max
3

( )

( )

In Sine-PWM, Va

max

(7)
= 0.5Vd . Therefore, comparing that with Eq. 7 shows that the SV-PWM results in

a higher limit on the available output voltage by a factor of

2
3

, or by approximately 15 percent.

Part 2: Carrier-based Implementation of SV-PWM

In general, in a carrier-based PWM as shown in Fig. 3a, a control voltage is compared with a high-

frequency carrier signal of a triangular waveform that establishes the switching frequency f s of the
inverter. The resulting output voltage in Fig. 3b has an average value that depends on the control voltage
V V vcontrol , a (t )
vaN (t ) = d + d
;
etc.
(8)
2
2
V
tri

Similar expressions hold for the average outputs of the other two poles in terms of their respective control
voltages. These expressions lead to an average representation as shown in Fig. 3c for each pole as the
sum of the desired phase voltage and a common-mode voltage vcm (t ) as discussed below.
Vtri

+
a

Vd

Vd

a
b

vcontrol , a (t )

vaN (t )

v an (t )

vbn (t )

vcn (t )

vcm (t )

vcm (t )

vcm (t )
N

(b)

(b)

(a)

Fig. 3 (a) Switching power-pole, (b) carrier-based PWM, (c) average power-pole output.
In Sine-PWM, the control voltages in Eq. 8 form a balanced sinusoidal set of signals such their
instantaneous sum is always zero. Therefore, they have no common-mode voltage, and as seen by Eq. 8,
the average voltage of each pole has a common-mode voltage vcm (t ) = 0.5Vd .
G
G
In SV-PWM, Note from Fig. 2b that in sector 1 with the non-zero basic vectors v1 (001) and v3 (011) , the

instantaneous power-pole c voltage is always 0 except it is Vd for a

G
v7 (111) . Therefore, the average value of the power-pole c output is

z
2

Ts interval corresponding to

z
vcN (t ) = Vd
2

(9)

G
G
Also from Fig. 2b, in sector 1 with the non-zero basic vectors v1 (001) and v3 (011) , switching-pole a
G
voltage is always Vd except it is zero for a 2z Ts interval corresponding to v0 (000) . Therefore, the

average value of the switching-pole a output is

z
vaN (t ) = Vd Vd
2
Equating the values given by Eqs. 9 and 10 to the switching-pole voltages in Fig 3c,

(10)

z
vcn (t ) + vcm (t ) = Vd
2

(11)

z
van (t ) + vcm (t ) = Vd Vd
2

(12)

and

Solving Eqs. 11 and 12 using the fact that van (t ) + vbn (t ) + vcn (t ) = 0 ,
vcm (t ) =

Vd vbn (t )
+
2
2

(13)

Eq. 13 is valid only for sector 1. To generalize to all sectors, vbn (t ) in Eq. 13 can be replaced by the
maximum and minimum of the phase voltages as follows:

Vd max(van , vbn , vcn ) + min(van , vbn , vcn )

2
2

Using the representation in Fig. 3c, and Eqs 8 and 14,

vcm (t ) =

(14)

vcontrol , a (t ) van (t ) max(van , vbn , vcn ) + min(van , vbn , vcn )

=

Vd / 2
Vd
Vtri

etc.

(15)

In Sine-PWM, the second term in the right side of Eq. 15 is zero. The limits of Sine-PWM and the SVPWM schemes are shown in Fig. 4a by their space vector circles, and the corresponding control voltages
are shown in Fig. 4b in accordance with Eq. 15. This figure clearly shows the benefit of using SV-PWM
over Sine-PWM leading to higher utilization of the dc-bus voltage. The above discussion also shows that
the SV-PWM can be implemented as simply as the Sine-PWM using carrier-based pulse-widthmodulation. Using MATLAB/Simulink, the analysis and simulation of SV-PWM in Direct Torque
Controlled (DTC) drives is carried out in [2] for encoder-less operation. For a thorough discussion of
various PWM schemes, readers are referred to [3].
Vs ,max ( SV PWM )
V

s ,max ( Sine PWM )

G
v2 (010)

vcontrol ( SV PWM )

G
v3 (011)

vcontrol ( Sine PWM )

II
III

IV

VI

G
v6 (110)

G
v1 (001)

G
v 4 (100)

G
v5 (101)
(a)

(b)

Fig. 4 Limits of SV-PWM and Sine-PWM.

ACKNOWLEDGEMENTS

The financial support received from the NSF grants DUE-0231119 and DUE-9952704 is gratefully
acknowledged.
REFERENCE

1. N. Mohan, First Course on Power Electronics, year 2004 edition, published by MNPERE
(WWW.MNPERE.COM).
2. N. Mohan, Advanced Electric Drives: Analysis, Control and Modeling using Simulink, year
2001 edition, published by MNPERE (WWW.MNPERE.COM).
3. D. Grahame Holmes and Thomas A. Lipo, Pulse Width Modulation for Power Converters:
Principles and Practice, 2003, published by John Wiley & Sons.
BIOGRAPHIES
Ned Mohan, Philip Jose and Ted Brekken are with the Department of Electrical Engineering at the
University of Minnesota, where Professor Waldemar Sulkowski is visiting on his sabbatical leave during
academic year 2003-2004 from the University of Narvik in Norway.