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Unit : mm
10.50.5
10.40.5
1.40.1
2.90.1
8.70.3 6.70.25
3.7
4.5
13.60.25
1.40.25
0.80.2
0.45 + 0.1
0.05
2.54
Features
1 2 3
AN7900F Series
4.20.25
2.770.3
(1.73)
3.10.1
13.60.25
4.50.25
17.00.25
3.80.25
5.3
(4.3)
Unit : mm
10.50.3
16.70.3
No external components
Output voltage : 5V, 6V, 7V, 8V, 9V, 10V,
12V, 15V, 18V, 20V, 24V
Overcurrent limit circuit built-in
Thermal over-load protection built-in
Area of safe operation (ASO) circuit built-in
2.50.25
4.50.3 1 : Common
2 : Input
3 : Output
0.4 + 0.1
0.05
1.40.2
0.80.2
(0.4)
2.00.25
2.54
4.50.3
1
8.70.3
Overview
2.50.25
1 : Common
2 : Input
3 : Output
Block Diagram
1
Common
Output
R1
+
Voltage
Reference
Error Amp.
R2
Q1
Starter
Thermal
Protection
Pass Tr.
Current
Limiter
RSC
2
Input
Symbol
Input voltage
VI
Power dissipation
AN7900T Series
PD
AN7900F Series
Rating
35 *1
Unit
40 *2
15 *3
10.25 *3
Topr
30 to +80
Storage temperature
Tstg
55 to +150
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=7 to 20V,
IO=5mA to 1A, PD<
=*
min
4.8
typ
max
4.75
Unit
5.2
5.25
100
mV
50
mV
10
100
mV
50
mV
Tj=25C
mA
Ibias (IN)
1.3
mA
Ibias (L)
0.5
mA
Vno
RR
VDIF (min.)
62
40
74
dB
IO=1A, Tj=25C
1.1
2.1
0.4
mV/C
IO (Peak)
Tj=25C
VO/Ta
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=10V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=8 to 21V,
IO=5mA to 1A, PD<
=*
min
5.75
typ
max
5.7
Unit
6.25
6.3
120
mV
1.5
60
mV
10
120
mV
60
mV
Tj=25C
mA
Ibias (IN)
1.3
mA
Ibias (L)
0.5
mA
Vno
RR
60
44
73
dB
V
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
0.5
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=11V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=79 to 22V,
IO=5mA to 1A, PD<
=*
min
6.7
typ
max
6.65
Unit
7.3
7.35
140
mV
1.5
70
mV
12
140
mV
70
mV
Tj=25C
mA
Ibias (IN)
1.3
mA
Ibias (L)
0.5
mA
Vno
RR
58
48
72
dB
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
0.5
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=12V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=10 to 23V,
IO=5mA to 1A, PD<
=*
min
7.7
typ
max
7.6
Unit
8.3
8.4
160
mV
80
mV
12
160
mV
80
mV
2.2
4.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
Vno
RR
56
52
71
dB
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
0.6
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=14V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=11.5 to 24V,
IO=5mA to 1A, PD<
=*
8.55
Unit
9.35
9.45
180
mV
90
mV
12
180
mV
90
mV
2.2
4.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
71
dB
IO=1A, Tj=25C
1.1
2.1
0.6
mV/C
Vno
RR
VDIF (min.)
8.65
max
typ
min
IO (Peak)
Tj=25C
VO/Ta
56
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=15V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=12.5 to 25V,
IO=5mA to 1A, PD<
=*
VI=12.5 to 27V, Tj=25C
min
9.6
typ
max
10
9.5
Unit
10.4
10.5
200
mV
2.5
100
mV
12
200
mV
100
mV
2.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
Vno
RR
56
64
71
dB
V
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
0.7
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=16V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=14.5 to 27V,
IO=5mA to 1A, PD<
=*
max
typ
12
11.4
Unit
12.5
12.6
10
240
mV
120
mV
12
240
mV
120
mV
2.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
70
dB
IO=1A, Tj=25C
1.1
2.1
0.8
mV/C
Vno
RR
VDIF (min.)
11.5
min
IO (Peak)
Tj=25C
VO/Ta
55
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=19V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=17.5 to 30V,
IO=5mA to 1A, PD<
=*
VI=17.5 to 30V, Tj=25C
min
14.4
typ
max
15
14.25
Unit
15.6
15.75
11
300
mV
150
mV
12
300
mV
150
mV
2.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
Vno
RR
54
90
69
dB
V
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
0.9
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=23V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=21 to 33V,
IO=5mA to 1A, PD<
=*
18
17.1
Unit
18.7
18.9
15
360
mV
180
mV
12
360
mV
180
mV
2.5
mA
mA
0.5
mA
Tj=25C
Ibias (IN)
Ibias (L)
68
dB
IO=1A, Tj=25C
1.1
Vno
RR
VDIF (min.)
17.3
max
typ
min
53
IO (Peak)
Tj=25C
2.1
VO/Ta
mV/C
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=27V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=23 to 35V,
IO=5mA to 1A, PD<
=*
min
19.2
typ
max
20
19
Unit
20.8
21
16
400
mV
5.5
200
mV
12
400
mV
200
mV
Tj=25C
mA
mA
0.5
mA
Ibias (IN)
Ibias (L)
Vno
RR
52
135
67
dB
V
IO=1A, Tj=25C
1.1
IO (Peak)
Tj=25C
2.1
VO/Ta
mV/C
VDIF (min.)
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=29V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Symbol
Output voltage
VO
VO
Line regulation
Load regulation
Bias current
REGIN
REGL
Ibias
Condition
Tj=25C
VI=27 to 38V,
IO=5mA to 1A, PD<
=*
24
22.8
Unit
25
25.2
18
480
mV
240
mV
12
480
mV
240
mV
Tj=25C
mA
mA
0.5
mA
Ibias (IN)
Ibias (L)
65
dB
IO=1A, Tj=25C
1.1
Vno
RR
VDIF (min.)
23
max
typ
min
50
IO (Peak)
Tj=25C
2.1
VO/Ta
mV/C
Note 1) The specified condition Tj=25C means that the test should be carried out with the test time so short (within 10ms) that the
drift in characteristic value due to the rise in chip junction temperature can be ignored.
Note 2) Unless otherwise specified, VI=33V, IO=500mA, CI=2F, CO=1F, Tj=0 to 125C
* AN7900T series : 15W, AN7900F series : 10.25W
Characteristic Curve
16
(1) Infinite Heat Sink
(2) 5C/W Heat Sink
(3) 15C/W Heat Sink
(4) No Heat Sink
14
12
(2)
10
8
6
(3)
4
2
12
(1)
10
8
(2)
6
(3)
4
(4)
2
(4)
0
40
80
120
160
15
10
5
10
10
20
6
10
Time t (s)
AN7905T/F
120
Output
3
CI
AN7900T
AN7900F
IO =
50
0m
IO =
A
20
IO = 0mA
20m
A
0.8
0.6
0.4
50
160
100
150
RR f
AN7905T/F
2
0
1
50
120
AN7905T/F
IO=100mA
100
80
60
40
20
0
0
10
20
30
40
10
50
100
1k
10k
100k
Frequency f (Hz)
Time t (s)
Application Circuit
1) Current Bootstrap Circuit
Input
IO=1000mA
1.0
80
1.2
40
1.4
(1)
14
VDIF (min.) Tj
Minimum I/O Voltage Difference VDIF (min.) (V)
PD Ta (AN7900F Series)
PD Ta (AN7900T Series)
16
VI
Q1
VI
CO
IO
Common
2F
V O
R2
VO
AN7900T
AN7900F
VO
AN7900T
AN7900F
1F
2F
Ibias
R1
V
|VO| =VO + Ibias + RO R1
2
1F