PCB Designing Final Project

PRINTED CIRCUIT BOARD (PCB) DESIGNING
PCB Basic
Chapter
Introduction
Printed-circuit
boards
(PCBs)
are
at
the
heart
of
the
modern
electronic packaging found in almost every consumer electronics product.

In essence, a PCB creates the connections between components within
a s ys t e m . M a s s r e p r o d u c i b i l i t y f o r c i r c u i t s w i t h e v e n a m o d i c u m o f
complexity and/or speed requires a PCB based packaging scheme. When
d e s i g n e d c o r r e c t l y, P C B s b r i n g p r e d i c t a b i l i t y.
A c o r r e c t d e s i g n m i n i m i z e s w i r i n g l e n g t h s a n d l a ys o u t t h e b o a r d s o s i g n a l integrity issues are controlled. It also makes it much easier to find

c o m p o n e n t s d u r i n g t r o u b l e s h o o t i n g a n d r e p a i r. E v e n h i g h - p i n - c o u n t I C s
c a n b e r e m o v e d , i f n e c e s s a r y, a n d r e p l a c e d . U p t o a b o u t
1 0 ye a r s a g o , a d v a n c e d P C B d e s i g n t e c h n o l o g i e s l i k e m i c r o v i a s , h i g h density
interconnects
(HDIs),
embedded
passives,
and
high-pin-count
F P G A s w e r e a v a i l a b l e p r i m a r i l y t o p o w e r u s e r s i n g l o b a l o rg a n i z a t i o n s
designing bleeding edge products. But these design technologies are
rapidly entering the mainstream, making them challenges for a broader
spectrum of PCB designers than ever before.
Printed Circuit Board, Bare Board, Circuit Board, Circuit
C a r d , P r i n t e d B o a r d , P C B , P W B , Al l t h e s e t e r m s a r e u s e d t o
describe a device that provides elec trical interconnections and a
s u r f a c e f o r m o u n t i n g e l e c t r o n i c c o m p o n e n t s . Al t h o u g h " p r i n t e d
wiring board" is more technically correct, the term "printed circuit
board" (PCB) is most commonly used. The Glossary (Chapter 8)
supplies
concise
differentiations,
but
all
terms
are
used
i n t e r c h a n g e a b l y.
EVOLUTION & INDUSTRY OVERVIEW

Although the first patents describing the "printed wire" were
i s s u e d i n 1 9 0 3 , P C B s a s w e k n o w t h e m c a m e i n t o u s e a f t e r Wor l d
War I I . D r. P a u l E i s l e r. An Au s t r i a n s c i e n t i s t w o r k i n g i n E n g l a n d ,
is generally credited with making the first PCB.
The concept was to replace radio tube wiring with something less
b u l k y.
In the 1950s and '60s, boards with circuitry on one side (singles i d e d ) w e r e t h e d o m i n a n t v a r i e t y. S t i l l i n u s e t o d a y,
s i n g l e - s i d e d b o a r d s a r e t h e s i m p l e s t v a r i e t y o f P C B . ( Ter m s i n b o l d
are defined in Chapter 7.) They are manufactured in high volume, most
often for consumer electronics, and are the least expensive to produce.
During the late '60s and early '70s, processes were devel oped for
plating
copper on the
walls
of the drilled
holes
in cir cuit
boards,
permitting top and bottom circuitry to be electri cally interconnected. These

double-sided boards became the industry -standard. Used today in consumer
products and computer peripheral equipment, double-sided boards are
slightly more expensive than single-sided boards.
As the densities and complexities of electronic compo nents increased,
t h e m u l t i l a y e r b o a r d - a p r o c e s s o f s a n d w i c h i n g s e v e r a l c i r c u i t r y l a ye r s
t o g e t h e r - w a s d e v e l o p e d . B y t h e m i d 1 9 8 0 s , m u l t i l a ye r s a c c o u n t e d f o r t h e
m a j o r i t y o f P C B s p r o d u c e d i n t h e U . S . Tod a y' s c o m p u t e r s , a e r o s p a c e e q u i p ment,
and
instrumentation
and
telecommunications
gear
all
contain
m u l t i l a ye r b o a r d s . M u l t i l a ye r s a r e t h e m o s t e x p e n s i v e t yp e o f P C B t o
produce.
TABLE 1-1.
C O M PAN Y
Ibiden
LARGEST PCB PRODUCERS:

C O U N T RY
2002SALES
Japan
932
CMK
Japan
931
Sanmina-SCI
U.S.
887
Nippon Mektron
Japan
562
Compeq
Tai w a n
515
U n l m i c r on
Tai w a n
465
Samsung Electro -Mech
S. Korea
462
Via s y s t e m s
U.S.
430
S. Korea
428
Japan
420
Daeduch
Shinko Electric
I n U . S . $ m i l l i o n s . S o u r c e : N . T. I n f o r m a t i o n
THE INDUSTRY
The U.S. PCB industry experienced monumental growth from the mid1970s through the '80s. In 1975, the U.S. output was approximately $1
billion. This figure grew to $2.6 billion in 1980, $4.1 billion in 1985, and
almost $6 billion in 1994. The worldwide output for PCBs in 2000 was $42
billion,
global
recession,
brought
on
by
excessive
capacity
and
diminished demand, slowed sales in 2001 and 2002. Most estimates place
the worldwide production in 2002 at about $33 billion.
In the mid 1980s, there were approximately 1,200 PCB producers in
the U.S. By 2002, that figure had dropped by half, due to high capital
equipment
costs,
environmental
regula tion
expenses,
and
o f fs h o r e
competition-Most shops in the U.S. are privately owned and are called
independents or merchants. These shops manufacture cus tom PCBs for
other companies, called original equipment manufacturers (OEMs). Some
OEMs manufacture PCBs for their own use. These facilities are called
captives. In 1979, captive producers accounted for 60% of the output, but
s i n c e t h e n c a p t i v e p r o d u c t i o n h a s s t e a d i l y d e c l i n e d . As o f 2 0 0 2 f e w c a p t i v e
shops remained and the vast majority of the U.S. output was manufactured
by independents.
PCB facilities can be small, with sales of a few thousand dollars each
m o n t h , o r v e r y l a r g e , w i t h m o n t h l y s a l e s i n t h e m i l l i o n s . Tab l e 1 - 1 s h o w s
the 10 largest producers in 2002.
THE MARKET
T h e l a r g e s t c o n s u m e r o f c i r c u i t b o a r d s i s t h e c o m p u t e r i n d u s t r y. T h i s
dominance
has
been
consistent
for
more
than
two
decades,
but
t e l e c o m m u n i c a t i o n s a n d a u t o m o t i v e h a v e r e c e n t l y m a d e g a i n s . Tab l e 1 - 2
shows the electronics produc tion by each major segment.
Independent PCB manufacturers generally do not design or specify
the boards they produce. Information regarding the shape of the board, the
mechanical and electrical properties, the surface-finish, and the material
c o m p o s i t i o n i s p r o v i d e d b y t h e P C B d e s i g n e r. T h e d e s i g n e r w o r k s e i t h e r
for an OEM. a design service bureau, or a contract manufacturer-OEMs
s p e c i f y a n d o r d e r t h e v a s t m a j o r i t y o f P C B s . S i n c e 1 9 9 0 h o w e v e r, t h e
trend has been for OEMs to order the entire circuit board assembly from a
contract electronics manufacturer (CEM). In such cases, the specifications
of the bare board and the selection of the board fabricator are often made
b y t h e c o n t r a c t o r. I n 1 9 9 8 , O E M s m a d e u p a b o u t 9 % o f t h e s a l e s o f
electronics assemblies. By 2002, CEMs accounted for about 16%.
T h e e x p e c t a t i o n s o f t h e P C B c o n s u m e r h a v e c h a n g e d d r a m a t i c a l l y.
C u s t o m e r s a r e d e m a n d i n g h i g h e r q u a l i t y p r od u c t s a n d a t m o r e c o m p e t i t i v e
prices- Forward-thinking PCB facilities are implementing complicated
p h i l o s o p h i e s f o r m a n a g i n g t h e f l o w o f p r o d u c t o n t h e s h o p f l o o r. L o n g t i m e
military standards are being phased out and replaced by commercial ones,
o r c a n c e l e d a l t o g e t h e r. S e r v i c e a n d s p e e d a r e n o w t h e c r i t i c a l e l e m e n t s o f a
s u c c e s s f u l P C B f a b r i c a t o r. C u s t o m e r s d e m a n d h i g h - t e c h b o a r d s i n a m a t t e r
of hours, and just-in-lime inventory control, statistical process con trol,
and inventory invoicing are alt services that customers have come to
e x p e c t f r o m t h e i r P C B v e n d o r s . Al l t h e w h i l e , t h e b u r d e n o f k e e p i n g u p
w i t h a d v a n c e s i n t e c h n o l o g y l i e s w i t h t h e f a b r i c a t o r.
TABLE 1- 2. WO RLD ELECTRO N ICS EQ UIP MEN T

P RO DUCTIO N. 2001
S EG MENT
SALES
% OF SALES
Computer
300.4
29.4
Communications
242.1
23.7
Industrial
114 . 8
11. 2
Consumer
103.3
10.1
Instrumentation
84.1
8.2
M i l i t a r y/ G o v e r n m e n t
92.9
9.1
Automotive
49.5
4.8
Office Equipment
35.1
3.4
I n U . S . $ b i l l i o n s S o u r c e : H e n d e r s o n Ven t u r e s
TAB L E 1 - 3 . W O R L D P C B M A N U FAC T U R I N G B Y R E G I O N , 2 0 0 2
REG IO N
% OF MARK ET
Japan
30-0
N o r t h Am e r i c a
17.0
China
14.3
Tai w a n
12.3
Wes t e r n E u r o p e
11. 8
R e s t o f As i a
6.9
South Korea
6.8
Others
2.9
I n c l u d e s r i g i d a n d f l e x c i r c u i t b o a r d s , S o u r c e : N . T. I n f o r m a t i o n
The PCB industry has become much more global in the past five
ye a r s . C u s t o m e r s t o d a y w i l t b u y b o a r d s f r o m w h e r e v e r t h e y g e t t h e b e s t
v a l u e . W h i l e N o r t h Am e r i c a a n d J a p a n h a v e h i s t o r i c a l l y b a t t l e d f o r t h e
m a r k e t l e a d i n P C B p r o d u c t i o n , o t h e r As i a n n a t i o n s , l e d b y Tai w a n a n d
C h i n a , h a v e g r o w n , a n d a r e t h r e a t e n i n g N o r t h Am e r i c a ' s r e i g n . P C B c o m p a n i e s i n Tai w a n , C h i n a , S o u t h K o r e a , a n d e l s e w h e r e i n s o u t h e a s t As i a n o w
a c c o u n t f o r o n e - t h i r d o f g l o b a l p r o d u c t i o n . Tab l e 1 - 3 s h o w s t h e w o r l d P C B
manufacturing by region.
GENERAL DESCRIPTION
Most printed circuit boards are made from laminate, a flat, rigid
material constructed with epoxy glass in the middle and copper foil on the
outside. The epoxy glass serves as an insu lating material and provides the
structural strength for mounting components. The copper is the conductive
medium through which electrical currents travel. The fabrication process
begins with the laminate (also called the dielectric or substrate) as the
primary raw material.
Electrical interconnections are accomplished with copper traces (also
c a l l e d c o n d u c t o r s , r u n s , a n d c i r c u i t r y) o n t h e b a s e m a t e r i a l . T h e t r a c e s a r e
made by selectively removing portions of the copper foil- Electrical current
is also carried by copper deposited on the walls of holes drilled in the
boards, thus connecting the top surface circuitry to the bottom as well as to
layers of circuitry inside the base material.

Boards with circuits on one side are called single-sided boards; those
with circuitry on both sides are called double sided. Boards with circuitry
o n b o t h s i d e s , p l u s l a ye r s o f c i r c u i t s i n s i d e t h e b a s e m a t e r i a l , a r e c a l l e d
m u l t i l a ye r s . M u l t i l a ye r s a r e f u r t h e r d e f i n e d b y t h e n u m b e r o f l a y e r s : a t
l e a s t f o u r, a n d i n e x t r e m e c a s e s a s m a n y a s 6 0 o r m o r e .
The majority of boards produced in the U.S. today are 0.059" thick.
Some are as thick as 0.400" or as thin as 0.002'. A very thin PCB with the
c a p a b i l i t y o f b e n d i n g i s c a l l e d a f l e x i b l e c i r c u i t . T h e r e i s a l s o a h yb r i d
m a d e f r o m b o t h t e c h n o l o g i e s c a l l e d a r i g i d - f l e x b o a r d . Ab o u t 9 0 % o f t h e
boards produced in the U.S. are rigid PCBs.
The majority of circuit boards today have components mounted to
them. The components provide the "brains" that activate and monitor the
electrical current that passes through the board. Components are mounted
t o t h e P C B i n t w o w a ys :
1. Component legs (called "leads") are inserted through holes in the
PCB and attached to lands on the opposite side of the board. This
m e t h o d i s c a l l e d p i n - i n - h o l e o r t h r o u g h - h o l e t e c h n o l o g y.
2. Component leads are soldered directly to pads on the sur face of the
board. This technique is called surface-mount technology (SMT).
SMT is the most common assembly technique.
Regardless of what we call them, printed circuit boards provide a

cost-effective, reliable method for interconnecting electronic components.
PCBs can be small enough to fit in a hearing aid or large enough to drive

a
powerful
c o m p u t e r. T h e y
can
be rigid,
flexible,
or
even three-
dimensional or molded.
The
pressures
on
U.S.
board
makers
are
numerous.
Foreign
competition, high capital equipment costs, and demanding environmental

regulations make the PCB business not only very price competitive, but
a l s o e x t r e m e l y d i f f i c u l t t o e n t e r.
As
globalization
increases,
North
Am e r i c a ' s
PCB
capacity
has
d e c r e a s e d . I t i s e s t i m a t e d t h a t i n 2 0 0 1 - 0 2 N o r t h Am e r i c a c l o s e d 3 5 % o f i t s
c a p a c i t y. M e a n w h i l e , As i a , l e d b y C h i n a a n d Tai w a n , h a s m a d e s t r o n g
gains.
There is no danger of PCBs being replaced in the next decade,

h o w e v e r. I n s t e a d , t h e
circuit
board is becoming more of
an active
component - one that performs its own functions, versus simply performing
t h e " c o m m a n d s " o f t h e m i c r o p r o c e s s o r.
How PCB is Made
Chapter
How to Make PCB's

One of the most discouraging things about making a hardware project
(apart from obtaining all of the components) is building the printed circuit
board - PCB. It is sometimes possible to use strip board or some other prefabricated board but more often than not the circuit complexity and
performance requires a proper PCB to be made. The good news is that due
to
improvements
in
printing
and
processing
technologies
it
is
now
relatively easy to make inexpensive high quality PCB's at home.
10
WAR N I N G : M a k i n g P C B ' s r e q u i r e s t h e u s e o f F e r r i c C h l o r i d e ( F e C I 3 )
w h i c h i s c o r r o s i v e s o a v o i d s k i n a n d e ye c o n t a c t . R e m e m b e r s a f e t y f i r s t u s e
glasses, gloves and protective overalls. Ferric Chloride is also very
g o o d a t d i s t o r t i n g c l o t h s w e e k s a f t e r yo u t h i n k yo u h a v e w a s h e d i t o f f . I f
yo u d o g e t a n y o n yo u r s k i n t h e n w a s h i t o f f i m m e d i a t e l y w i t h l o t s o f w a t e r
and soap.
The Shopping List

T h i s i s t h e m i n i m u m t h i n g s yo u w i l l h e e d ,
1 . Ac c e s s t o a P C w i t h a L a s e r p r i n t e r e . g . H P L a s e r J e t
2. Cloths iron
3. Kettle
11

4 . Wat e r b u c k e t
5. A one liter glass jar with plastic screw top (biscuit jar)
6 . P C B h a n d d r i l l w i t h 0 . 8 m m a n d 1 m m d r i l l b i t s - F R 8 4 F, Q Y 6 4 U
7. Copper-Clad fiberglass board - WF40T
8 . P r e s s - n - P e e l P C B t r a n s f e r s ys t e m - AB 1 5 R
9. Ferric Chloride Copper etching fluid 250ml - WF10L
1 0 . Two p l a s t i c e t c h i n g t r a ys ( i d e a l l y d i f f e r e n t s i z e s ) - C H 3 8 R
11. P C B c l e a n i n g r u b b e r - H X 0 4 E
12. PCB solvent cleaner - LL59P
1 3 . S a f e t y g l a s s e s , l a t e x g l o v e s , o l d c l o t h e s / o v e r a l l s - K E 8 3 E , YJ 8 4 C
All part numbers are from the Maplin Electronics catalogue.
The Artw ork

U n t i l r e c e n t l y t h e a r t w o r k h a d b e e n a n a r e a o f D IY P C B ma n u f a c t u r e
w h i c h c a u s e d t h e b i g g e s t p r o b l e ms . B u t n o w b y c o mb i n i n g h i g h q u a l i t y l a s e r
p r i n t i n g w i t h t h e P r e s s - n - P e e l P C B t r a n s f e r s ys t e m t h e s e p r o b l e ms h a v e b e e n
s o l v e d . Th e f i r s t s t a g e i s t o t r a n s f e r t h e c i r c u i t l a yo u t f r o m t h e P C t o
t h e s p e c i a l P r e s s - n - P e e l f i l m . You w i l l f i n d t h a t m y p r o j e c t s p r o v i d e L a s e r
p r i n t f i l e s ( . p r n ) f o r p r i n t i n g t h e c i r c u i t l a yo u t d i r e c t o n t o t h i s f i l m ,
12
1. I cut the Press-n-Peel film in half for small boards
so it lasts longer
2. Put the film in the laser printer so that the print will appear on matt
blue side
3 . A t a D O S c o m m a n d p r o m p t t yp e : c o p y f i l e n a m e . p r n l p t 1 t o p r i n t o n t o
the film
This will produce a contact print where the black image will end up
as Copper on the final PCB. Now to transfer the artwork to the Copper
board by following the instructions with the Press-n-Peel film,
13
1 . C l e a n t h e C o p p e r b o a r d v e r y w e l l w i t h t h e P C B c l e a n i n g r u b b e r.
2 . H e a t t h e c l o t h s i r o n t o 3 0 0 d e g . F ( A c r yl i c t o P o l ye s t e r s e t t i n g ) .
3. Hold the film with the print in contact to the Copper and smoothly
iron the film down until the print appears black through the film
(about 1min).
4. Allow 5mins to cool down (or speed this up with water) then peel the
film off
T h i s s h o u l d p r o d u c e a c l e a n b l a c k p r i n t o n t o t h e C o p p e r. I f yo u l e t
t h e f i l m m o v e o r o v e r h e a t t h e n yo u w i l l f i n d t h a t t h e t r a c k s a n d w r i t i n g
w i l l b e s m e a r e d a n d o u t o f f o c u s a l s o t h e f i l m m a y b e w r i n k l e d u p . I f yo u
don't use enough heat or heat unevenly then the film may not stick or be
14

d a r k e n o u g h . I n e i t h e r c a s e c l e a n o f f t h e P C B a n d t r y a g a i n , yo u s h o u l d g e t
it right after a couple of goes.
The Etching
Now for the messy bit, etching the PCB to remove the unwanted
C o p p e r. P l e a s e r e a d t h e w a r n i n g a t t h e t o p o f t h e p a g e a s i t i s i m p o r t a n t t o
take
appropriate
precautions
before
handling
the
etch
chemicals.
r e c o m m e n d yo u d o t h i s o u t s i d e o r i n a s h e d a n d yo u m u s t w a r e g l a s s e s a n d
gloves. Keeping the etch chemicals warm (45deg C) is essential as it
reduces the etch time from over an hour to about 15mins.
1.
Dilute the concentrated Ferric Chloride fluid with water (1:1) and
pour into the one liter glass jar and screw the top on.
2 . P l a c e a s h e e t o f n e w s p a p e r o n a f l a t s u r f a c e a n d p u t t h e t r a ys o n
this.
3. Fill the kettle with water and boil.
4 . H e a t t h e F e r r i c C h l o r i d e j a r i n a b u c k e t o f h o t w a t e r. C a u t i o n d o n ' t
15

spill any drops and keep away from food.
1. Pour 1cm of boiling water into the bottom tray then place the other
tray on top.
2. Put the PCB copper side up on the top tray and pour all the Ferric
Chloride on top.
3. Gently rock the top tray to keep the etch fluid moving avoiding
spillage.
4. After about 15mins all of the unwanted Copper should have
disappeared.
5.
Remove the board and drop it into a bucket of cold water to clean
off
Usefull tip: For small boards just drill a 1mm hole in the corner of the
board and tie 2ft of strong cotton to this. Now put the board straight into
the Ferric Chloride jar with the end of the cotton outside and put the top on
t h e j a r. K e e p t h e j a r h o t b y h e a t i n g i n a t r a y o f b o i l i n g w a t e r a n d g e n t l y
rock to keep the etch fluid moving. Every 5mins use the cotton to lift the
16

board out and check progress. This method is much less messy as the Ferric
C h l o r i d e i s a l w a ys l e f t i n t h e g l a s s j a r.
Drilling
Drilling with 0.8mm drill bits can be a bit tricky as it's easy to break
t h e d r i l l b i t s . Al w a ys h o l d t h e d r i l l s t r a i g h t a n d d o n o t b e n d i t w h e n t h e
hole has started. Putting a soft block of wood under the PCB provides a
g o o d b a s e t o d r i l l i n t o . O n c e yo u h a v e b e c o m e e x p e r i e n c e d a t d r i l l i n g I
w o u l d r e c o m m e n d u s i n g Tun g s t e n C a r b i d e d r i l l s ( F E 4 9 D ) w h i c h e a s i l y
b r e a k b u t l a s t m u c h l o n g e r,
1 . D r y o ff t h e b o a r d a n d c l e a n a w a y t h e b l u e e t c h r e s i s t w i t h P C B s o l v e n t
c l e a n e r.
17

2 . U s i n g a 0 . 8 mm P C B d r i l l b i t d r i l l o u t a l l o f t h e c o mp o n e n t h o l e s .
3 . S o me 1 m m h o l e s ma y n e e d t o b e ma d e f o r c o n n e c t o r s , 3 m m f o r c o r n e r
fixings.
4 . F i n a l l y us e a P C B r u b b e r t o c l e a n t h e c o p p e r r e a d y f o r s o l d e r i n g
S o n ow yo u r P C B ' s f i n i s h e d a n d yo u c a n s t a r t s o l d e r i n g t h e c o mp o n e n t s i n .
You s h o u l d d o t h i s s o o n a f t e r yo u h a v e c l e a n e d t h e P C B ( w i t h i n 1 h o u r ) a s
the copper soon oxidizes and becomes hard to solder onto.
PCB Designing Flow Process

Printed
circuit
board
are
used
in
all
Chapter
types
of
electronic
products like Mobiles, Computers, toys, CNC machines, automobile

a n d a i r c r a f t s s y s t e m s e t c . B e l o w a r e a l l s t e p s w h i c h a r e u s e d i n
PCB designing with little introduction. The detail of these steps is
coming in next chapters.
SYSTEM
Design
System designer design a system according to

requirements. The ideas of systems designer is
converted into the soft form in the form of schematic.
Schematic diagram are used to represent graphically the
Schematic
Drafting
components and interconnections of electrical circuits.

A schematic is the ideal representation of a circuit.
Footprint
Generation
Nearly all PCBs will use some components that must be

soldered to the board.
18

Each of these components must have a footprint.
Board
All information of schematic is imported into the board

file through netlist.
To place all symbols/components according to circuit
Placement
&
Routing
wise and board requirement is called Placement.

To connect all symbol pins according to netlist
information is called Routing.
Design For Manufacturing (DFM).
DFM
The checks which are run on tool level to notify the
design
errors to avoid any mistake in design.
After finalizing the design, Gerber files are generated
Gerber
Data
to send to Fabrication House. The machines read

these file and prepare the board.
Fabrication
19

This is the process to manufacture the printed circuit
boards.
Assembly
The process to place/solder the components on the

board file is called Assembly.
Board
Testing
This is final process which is performed on final

assembled board to check connectivity and
signals integrity etc.
After final test the final product OR Master board will
Final
Product
be ready to work. When the final board works

successfully it means this design is ready for mass
production.
20
Chapter
STACKUP & IMPEDANCE CALCULATION

S t a c k u p a n a l ys i s c a n h e l p t o o p t i m i z e l a ye r c o u n t , t r a c e w i d t h a n d
spacing and electrical performance.
T h e t e r m s t a c k - u p r e f e r s t o t h e a r r a n g e m e n t a n d t h e t yp e s o f l a ye r s
i n a m u l t i l a ye r b o a r d . T h e d e s i g n o f a P C B s t a c k - u p i n v o l v e s a s c e r t a i n i n g
t h e n u m b e r o f s i g n a l l a ye r s n e e d e d t o r o u t e t h e b o a r d a n d t h e g r o u n d / p o w e r
planes demanded for adequate power distribution. It is recommended that
t h e l a ye r s a r e a r r a n g e d s o t h a t e a c h h i g h - s p e e d t r a c e i s r e f e r e n c e d t o a
continuous plane. Furthermore, it is desirable for the stack-up to include
p a r a l l e l ( a d j a c e n t ) p o w e r a n d g r o u n d l a ye r s f o r e n h a n c i n g c a p a c i t i v e
decoupling and reducing EMI, and the PCB stack-up will strongly influence
i m p e d a n c e o f a p o w e r d i s t r i b u t i o n s ys t e m ( P D S ) .
Prepreg (also called B-stage) consists of a glass cloth coated with
r e s i n ( e p o x y) t h a t h a s n o t b e e n f u l l y c u r e d . A p r e p r e g l a ye r i s a p p l i e d
b e t w e e n t w o i n t e r n a l l a ye r s ( o r c o r e s ) o f a m u l t i l a ye r P C B t o f u n c t i o n a s
glue through the lamination process. A core is a thin piece of dielectric
21

(cured fiberglass-epoxy resin) with copper foil bonded on both sides. The
term laminate also refers to a composition of two sheets of copper foil
laminated to a piece of woven glass cloth saturated with resin and fully
cured.
The thickness of the copper foil is expressed in ounces that represent
the weight of copper per square foot of surface area. Three common
thicknesses are 0.5 ounce, 1.0 ounce and 2.0 ounce. Copper foil of 1.0
ounce (~1.4 mils) thickness is produced by plating to a thickness sufficient
to equal one ounce of copper distributed over a one-square-foot area.
Use of 1.0 ounce copper foil is quite popular in PCB fabrication;

h o w e v e r, 0 . 5 o u n c e g r o u n d / p o w e r p l a n e s c a n b e s u f f i c i e n t f o r a l l h i g h speed PCBs with exception of those that demand very high power levels.
Copper foil that is categorized as 1.0 ounce foil has a thickness of
approximately 1.2 mils and 0.5 ounce foil has a thickness of 0.6 mils in the
completed circuit board because of anticipated copper losses that result
from the chemical processes used in the manufacturing process. The
t h i c k n e s s o f p l a n e g r o u n d a n d p o w e r l a ye r s a d d s t o t h e t o t a l P C B t h i c k n e s s .
Standard PCB thickness values include 39 mils, 62 mils, 93 mils and
125 mils, but other board thicknesses (for instance 100 mils) can be also
o b t a i n e d . S t a c k - u p p a r a m e t e r s s u c h a s s p a c i n g b e t w e e n l a ye r s , s u b s t r a t e
dielectric materials and trace dimensions need to be selected properly in
order to meet the board impedance and crosstalk requirements.
S e v e r a l s t a c k - u p f e a t u r e s c a n b e i l l u s t r a t e d b y c o n s i d e r i n g a f o u r - l a ye r
PCB, as depicted by Figure 1.
22
Ground and power planes perform multiple functions, one of which is to

distribute power to various devices, but they also furnish a means for
a c h i e v i n g c o n t r o l l e d i m p e d a n c e t r a n s m i s s i o n l i n e s . T h e p l a n e l a ye r s c a n
a p p r e c i a b l y d i m i n i s h n o i s e a n d r a d i a t i o n l e v e l s . At f r e q u e n c i e s e x c e e d i n g
1 0 M H z o r 1 5 M H z , i n c o r p o r a t i o n o f p o w e r a n d g r o u n d l a ye r s , s u c h a s a
m u l t i l a ye r s t a c k - u p a s o p p o s e d t o a t w o - l a ye r b o a r d i s r e c o m m e n d e d .
I n F i g u r e 1 , t h e l a ye r o r d e r f r o m t o p t o b o t t o m i s S i g , G n d , P w r a n d
S i g , w h i c h i m p l i e s t h a t t h e o u t e r l a ye r s a r e f o r m e d b y t h e s i g n a l l a ye r s ,
a n d t h e i n n e r l a ye r s a r e t h e g r o u n d a n d p o w e r. An o t h e r p o s s i b i l i t y i s t o
h a v e g r o u n d a n d p o w e r p l a n e l a ye r s a s o u t e r l a ye r s ( G n d , S i g , S i g , P w r ) .
This scheme can provide greater shielding 6, but it is accompanied by
several drawbacks. For example, the planes need to be cut to allow
component placement, and rework on the board becomes more difficult.
The stack-up depicted by Figure 1 is a common arrangement for a
f o u r - l a ye r
PCB;
the
parallel
power
and
ground
planes
can
furnish
interplane capacitance which is important in the stack-up design of highspeed PCBs.
23

The capacitance produced by a parallel plate capacitor is directly
proportional to the area of plates and inversely proportional to their
separation. In Figure 2, Mathcad is applied to compute and to plot
interplane capacitance (per unit area) for two different dielectric materials.
These include Isola 370HR (in red) and Rogers 4320 (in blue). The Isola
370HR material is a high performance 180C glass transition temperature
( T g ) s ys t e m f o r P C B a p p l i c a t i o n s w h e r e m a x i m u m t h e r m a l p e r f o r m a n c e a n d
reliability are entailed.
24
Rogers 4320 (prepreg) and 4350 (laminate) are glass-reinforced ceramic

thermosets that are available in several thicknesses with dielectric constant
r = 3 . 5 a n d l o s s t a n g e n t Tan ( ) = 0 . 0 0 4 . I n g e n e r a l , R o g e r s R O 4 0 0 0 s e r i e s
are low-loss materials that can be economically fabricated via standard
e p o x y/ g l a s s p r o c e s s e s . T h e y a r e d e s i g n e d w i t h e x c e l l e n t h i g h f r e q u e n c y
performance and low cost circuit production in mind.
T h e c a p a c i t a n c e r e s u l t i n g f r o m t w o a d j a c e n t p l a n e l a ye r s p l a ys a
c r u c i a l r o l e i n t h e p o w e r d e l i v e r y s ys t e m ( P D S ) o f h i g h - s p e e d b o a r d s .
Since such parallel plate capacitance is inversely related to the separation
25

o f t h e p l a n e p a i r s , i t i s d e s i r a b l e t o k e e p t h e p l a n e s n e a r e a c h o t h e r.
H o w e v e r, t h e r e a r e t w o i m p o r t a n t l i m i t a t i o n s c o n c e r n i n g h o w c l o s e t h e
planes can be fabricated. These restrictions relate to the capability of PCB
manufacturer to laminate the planes without causing shorts and to preserve
minimum dielectric thickness to meet insulation standards.
N o r m a l l y, P C B s c a n n o t p r o v i d e a d e q u a t e i n t e r p l a n e c a p a c i t a n c e t o
successfully meet decoupling requirements below 500 MHz. When this
occurs,
other
decoupling
methods,
such
as
e m p l o ym e n t
of
discrete
capacitors, are then needed.

L e t u s c o n s i d e r t h e s i x - l a ye r s t r u c t u r e o f F i g u r e 3 , w h i c h i n c l u d e s
both outer (microstrip) and inner (stripline) traces. For a surface microstrip
t h e s i g n a l c o n d u c t o r i s e x p o s e d t o a i r, s o t h e e f f e c t i v e d i e l e c t r i c c o n s t a n t
will be somewhere between that of air (which equals 1) and the dielectric
constant of the substrate below the trace. The signal speed is influenced by
the
effective
dielectric
constant
with
the
surface
microstrip
usually
o f f e r i n g t h e f a s t e s t p r o p a g a t i o n v e l o c i t y.
26

A f t e r p l a t i n g , o u t e r - l a ye r t r a c e s h a v e g r e a t e r t r a c e - w i d t h v a r i a t i o n t h a n
i n n e r l a ye r
traces. This
implies
that
stripline
traces
provide
superior
i m p e d a n c e c o n t r o l a s c o m p a r e d t o m i c r o s t r i p l i n e s . H o w e v e r, s t r i p l i n e s c a n
cause stubs when through-hole vias are used, as illustrated by Figure 3.
The configurations depicted by Figures 3a and 3b (which involve
connection to stripline traces) result in stubs due to unused via portions
( t h e s e g m e n t s w h i c h e x t e n d p a s t t h e v i a s l a s t c o n n e c t i n g l a ye r ) . H o w e v e r,
the case of Figure 3c, in which two microstrip transmission lines are
connected, can shun via stub formation.
Bogatin presents an interesting comparison of microstrip vs. stripline
traces
in
attenuation,
terms
of
far-end
impedance
crosstalk
and
control,
routing
differential
pair
coupling,
d e n s i t y. G e n e r a l l y, h i g h e r -
density PCBs are less expensive, but closely spaced traces can result in
crosstalk issues. The PCB manufacturing cost is directly related to the size
o f t h e P C B a n d t h e n u m b e r o f l a ye r s .
When designing a PCB stackup, it is essential to consider crosstalk 1
requirements. Depicted by FIGURE 4 are two single-ended traces having
l i n e w i d t h W, t h i c k n e s s t , e d g e - t o - e d g e s e p a r a t i o n S n a n d h e i g h t o v e r
reference plane H. Er is the relative dielectric constant of the substrate.
27

In order to minimize crosstalk, it is desirable to set H as small and
Sn as large as allowed by board target impedance and routing restrictions.
The effect of these stackup parameters on crosstalk is disclosed by
Equation 1 (FIGURE 5).
Lm is mutual inductance between two neighboring wires, H equals the

thickness of the dielectric substrate and L is the line inductance. The
center-to-center spacing (s) and edge-to-edge spacing (S n) for two traces of
width W are directly related as shown by Equation 2 (Figure 5).
Crosstalk requirements control trace separation (pitch), which in turn
i n f l u e n c e s b o a r d d e n s i t y a n d t h e n u m b e r o f r o u t i n g l a ye r s . F r o m E q u a t i o n s
1 and 2, it follows that crosstalk noise (between two neighboring traces)
being proportional to mutual inductance, decreases as Sn increases or H
decreases. Optimizing trace separation is also valuable for controlling
crosstalk
between
two
coupled
differential
pairs,
as
illustrated
in
FIGURE 6.
28
Crosstalk between differential pairs 1 and 2 can be diminished by

widening Sn. A study of far-end crosstalk (FEXT) and crosstalk-induced
jitter involving two edge-coupled differential pairs of W = 5 mil and
interapair separation Sp = 5 mil, revealed that increasing the pair-to-pair
spacing Sn from 5 mils to 20 mils can significantly reduce FEXT and
deterministic jitter (DJ). Other measures to avoid crosstalk problems
include minimizing parallel run lengths, incorporating guard traces and
orthogonally routing the signal lines which belong to adjacent routing
l a ye r s .
To a t t a i n g o o d s i g n a l i n t e g r i t y, a c l e a n u n o b s t r u c t e d r e t u r n p a t h i s
demanded for high-speed signals. Signal and power quality degradation can
occur in PCBs and IC packages due to high-speed traces traversing planesplits.
P l a n e l a ye r s f u l f i l l s e v e r a l d u t i e s i n p o w e r d i s t r i b u t i o n n e t w o r k s
( P D N s ) . T h e y c a n t r a n s f e r D C c u r r e n t f r o m s o u r c e t o l o a d , c o n n e c t b yp a s s
capacitors to active components and furnish a return path for the signals.
Current flows on power distribution in a manner to diminish total
29

i m p e d a n c e . At l o w f r e q u e n c i e s , t h i s t r a n s l a t e s t o m i n i m i z i n g r e s i s t a n c e b y
s p r e a d i n g o v e r e v e r y p o s s i b l e p a t h . At h i g h f r e q u e n c i e s , t h e r e t u r n c u r r e n t
crowds under the signal (on reference plane) to minimize inductance.
It is important to avoid splits on ground or power planes, but there
are situations when it is inevitable. For instance, power islands and moats
arise when multiple powers are incorporated on the same plane. Sometimes,
i t i s n e c e s s a r y t o a l l o w a p l a n e l a ye r c u t - o u t b e n e a t h a c o n n e c t o r i n o r d e r
to lessen the mounting pad capacitance.
Under such circumstances, when cutouts on reference planes are
unavoidable, it is critical not to route high-speed buses over such voids
(unless the plane with slots is sandwiched between two uniform/continuous
planes).
The
return
current
path
is
also
interrupted
whenever
signal
t r a n s i t i o n s f r o m o n e l a ye r t o a n o t h e r a n d c h a n g e s r e f e r e n c e p l a n e s . I t i s
then desirable to place near the signal via another via (if both reference
p l a n e s a r e o f s a m e t yp e ) o r a d e c o u p l i n g c a p a c i t o r ( i f o n e r e f e r e n c e p l a n e
is a ground while the other one is power). This can furnish for the return
current a high-frequency lane between the two reference planes.
T h i c k n e s s o f m e t a l ( i . e . p l a n e a n d s i g n a l ) l a ye r s i s a s i g n i f i c a n t
option when constructing PCB stackup. Thicker cladding offers lower
r e s i s t a n c e a n d s ym b o l i z e s a g o o d s e l e c t i o n f o r p o w e r p l a n e s . T h i n n e r
cladding sustains narrow lines with superior width control; hence, thin
c l a d d i n g i s o f t e n a l o g i c a l p r e f e r e n c e f o r s i g n a l l a ye r s t o a c h i e v e h i g h
density routing.
U t i l i z i n g 0 . 5 o z c o p p e r f o r s i g n a l l a ye r s i s a g o o d c h o i c e f o r
impedance control since only a very small amount of etching is necessary
30

to produce a trace. This allows controlling the trace width to within +/- 0.5
m i l s . H o w e v e r, t h e r e a r e a l s o c a s e s i n w h i c h t h i c k e r t r a c e s a r e d e s i r e d i n
o r d e r t o d e c r e a s e t h e t r a c e s D C r e s i s t a n c e ( o r f o r r e a l i z i n g s u p e r i o r
thermal performance), although it is more difficult to attain impedance
control for thicker traces.
Accomplishing
impedance
control
for
high-speed,
single-ended
signals (such as memory buses and CPU interfaces) and differential pairs
(high-speed serial-links, differential clocks, etc.) is vital in stackup design.
Mathematical
equations
exist
for
calculating
single-ended
and
differential impedance. These formulas offer useful insight regarding how

impedance depends on various stackup parameters (e.g., dielectric constant,
trace width, dielectric thickness). For instance, Equation 3 (Figure 5)
which is an IPC recommended approximation for microstrip impedance,
reveals that Zo decreases as the dielectric constant (Er) increases, copper
thickness (t) increases or trace width (W) increases. Furthermore, Zo
increases as dielectric height H increases. Equation 4 (Figure 5), which
applies to edge-coupled microstrip using FR4 material, illustrates that
differential impedance Zdiff is a function of Zo (the uncoupled singleended characteristic impedance for each trace), edge-to-edge separation
between traces Sn and dielectric thickness H.
Impedance formulas can provide helpful insight and more precise
results than rules of thumb approximations, but the accuracy of such
a n a l yt i c a l t e c h n i q u e s i s u s u a l l y l i m i t e d t o a b o u t 1 0 % . As c e r t a i n i n g
impedance to a higher degree of exactness would require the use of a field
solver program.
Whenever a PCB undergoes modifications, it is necessary to perform
s t a c k u p a n a l ys i s . S u c h a s s e s s m e n t c o n s i d e r s o p t i m u m n u m b e r o f l a ye r s ,
31

b o a r d s i z e , r o u t i n g d e n s i t y, c o p p e r w e i g h t , p o w e r n e e d s , P C B t h i c k n e s s ,
dielectric materials, trace widths/separation, most favorable impedance,
p r i c e a n d m a n u f a c t u r a b i l i t y.
A p p l i c a t i o n o f H yp e r Lyn x S t a c k u p E d i t o r f o r i m p e d a n c e p l a n n i n g i s
illustrated by FIGURE 7. The Stackup Editor allows adding or subtracting
l a ye r s a n d i n c o r p o r a t i n g s o l d e r m a s k .
For each dielectric, it permits selecting technology (prepreg or core),

t h i c k n e s s , d i e l e c t r i c c o n s t a n t a n d l o s s t a n g e n t . F o r m e t a l l a ye r s , i t a l l o w s
d e f i n i n g m e t a l t yp e ( f o r c o r r e c t r e s i s t i v i t y a n d t e m p e r a t u r e c o e f f i c i e n t ) .
Tra c e w i d t h s a n d t h i c k n e s s c a n b e s p e c i f i e d f o r e a c h s i g n a l l a ye r. T h e Z o
P l a n n i n g t a b a l l o w s f o r s p e c i f yi n g t a r g e t i m p e d a n c e ( f o r s i n g l e - e n d e d o r
32

differential pairs) and then solving for various parameters (trace width,
separation).
F i g u r e 7 s h o w s a s t a c k u p c o n s i s t i n g o f e i g h t l a ye r s . An e i g h t - l a ye r
stack can satisfy several desirable requirements, including multiple ground
a n d p o w e r l a ye r s . I n t h i s c a s e e a c h s i g n a l l a ye r i s a d j a c e n t t o a t i g h t l y
c o u p l e d p l a n e l a ye r, a n d t h e s i g n a l l a ye r s a r e l o c a t e d b e t w e e n p l a n e s l a ye r s
(and are thereby being well shielded).
In order to minimize warping, it is desirable for the stackup to be
s ym m e t r i c a l a n d w e l l b a l a n c e d . N o r m a l l y, a n N - l a ye r P C B i n c l u d e s N m e t a l
l a ye r s s e p a r a t e d b y N - 1 d i e l e c t r i c s , a n d N s h o u l d b e a n e v e n n u m b e r t o
avoid warpage.
Another measure to accomplish uniformity is to add dummy copper
p a d s ( t h i e v i n g ) t o o p e n a r e a s o n t h e P C B s o u t e r l a ye r s . T h i s a i d s i n
attaining a uniform copper distribution across the whole board surface.
P o u r i n g c o p p e r o n o u t e r l a ye r s a n d g r o u n d i n g i t w i t h m u l t i p l e v i a s
can enhance shielding, reduce crosstalk and improve heat dissipation.
Furthermore, copper/ground flooding (not to be confused with thieving,
w h i c h i n v o l v e s a p p l yi n g d u m m y c o p p e r p a d s ) i n f l u e n c e s i m p e d a n c e a n d c a n
convert mictrostrip lines into coplanar configuration. Such geometries can
b e e f f i c i e n t l y a n a l yz e d w i t h P o l a r I n s t r u m e n t s S i 8 0 0 0 s o f t w a r e t h a t
e m p l o ys B o u n d a r y E l e m e n t M o d e l i n g t o f o r e c a s t t h e f i n i s h e d i m p e d a n c e o f
various PCB structures.
FIGURE
exemplifies
impedance
computation
for
coplanar
d i f f e r e n t i a l p a i r.
33
The parameters comprise trace width = 12 mil, trace thickness = 2

mil, dielectric thickness = 8 mil, dielectric constant = 3.38, intrapair
separation = 15 mil, line to ground clearance (horizontal) = 10 mil, solder
mask thickness = 0.8 mil and solder mask dielectric constant = 4.5. Si8000
predicts differential impedance of 100.43 . This denotes a nominal
calculation,
but
frequently
it
is
necessary
to
consider
impedance
tolerances.
A t yp i c a l t o l e r a n c e v a l u e i s + / - 1 0 % . A d i f f e r e n t i a l i m p e d a n c e o f 1 0 0
+ / - 1 0 % i m p l i e s v a r i a t i o n f r o m 9 0 t o 110 . S o m e t i m e s , i t i s d e s i r a b l e t o
have a tighter tolerance such as +/- 5%, since impedance tolerance often
involves trade-off between impedance of PCB traces, package, driver
o u t p u t i m p e d a n c e a n d t e r m i n a t i o n r e s i s t o r s . Tig h t e n i n g t h e P C B t r a c e
34

tolerance makes it feasible to relax the constraints on other parameters
( p a c k a g e , d r i v e r, t e r m i n a t i o n ) , b u t t h i s a l s o i n c r e a s e s b o a r d f a b r i c a t i o n
cost. A 5% tolerance is more expensive to manufacture than a 10%
tolerance, which is costlier than a 15% tolerance.
T h r e e m a i n m a t e r i a l s 3 i n a m u l t i l a ye r P C B e m b r a c e c o p p e r f o i l
sheets,
resin
and
woven
glass
cloth.
Cores
or
laminate
sheets
are
constructed by affixing copper foil to one or both sides of fully cured

prepreg
sheets.
Prepreg
mats
are
weave
of
glass
fiber
ya r n s
preimpreganted with partially cured resin.

S e v e r a l r e s i n t yp e s a r e u t i l i z e d f o r p r e p r e g p r e p a r a t i o n . T h e s e r e s i n
s ys t e m s u s u a l l y d i f f e r i n e l e c t r i c a l p r o p e r t i e s ( s u c h a s d i e l e c t r i c c o n s t a n t
and loss tangent) and mechanical/thermal characteristics (coefficient of
expansion, glass transition temperature and rate of moisture absorption).
The commonly used FR-4 has a woven glass/epoxy resin composition.
H o w e v e r, t h e r e a r e a l t e r n a t i v e s s u c h a s G E T E K , M E G T R O N , B T, p o l ya m i d e
and
c ya n a t e
resin
material,
with
attractive
mechanical
or
electrical
properties (low dielectric constant and loss tangent).

Fibers are applied to strengthen the resins; these comprise the
electrical grade E glass and structural grade S glass. E glass is more
common, but S glass is stronger and has lower Er (also more expensive)
t h a n E g l a s s . Ad d i t i o n o f f i b e r t o r e s i n a l t e r s t h e e l e c t r i c a l a n d m e c h a n i c a l
characteristics of the composite structure based on glass-to-resin ratio. FR6 u t i l i z e s a p o l ye s t e r r e s i n s ys t e m p l u s g l a s s m a t t e r e i n f o r c e m e n t a n d i s
suitable for flame resistant, low capacitance or high impact applications.
Solder mask / resist is a coating that protects PCB traces and
prevents solder bridges and shorts. It facilitates wave soldering applied in
35

m a s s a s s e m b l y. S o l d e r m a s k i s a l a c q u e r - l i k e p o l ym e r l a ye r o f t e n a p p l i e d
with a green tint, but it is available in various colors and finishes. A
common solder mask is Liquid Photo Imagable (LPI).
F o r a m u l t i l a ye r P C B , t h e c o p p e r t h i c k n e s s d o e s n o t h a v e t o b e t h e
s a m e f o r a l l s t a c k u p l a ye r s . I t i s a l s o u n n e c e s s a r y f o r a l l t h e c o r e s t o b e o f
t h e s a m e l a m i n a t e . H yb r i d - t yp e c o n s t r u c t i o n h a s b e e n g a i n i n g p o p u l a r i t y.
The PCB conductor and dielectric losses 32 constitute another critical
consideration.
T h e D C c o n d u c t o r r e s i s t a n c e i s g o v e r n e d b y E q u a t i o n 5 . Al l o f t h e
Equations can be found in FIGURE 9. Here, Rdc represents resistance per
u n i t l e n g t h f o r D C c u r r e n t s , i s t h e b u l k c o n d u c t o r r e s i s t i v i t y, W i s t r a c e
width and t is thickness. The conductor DC losses are directly related to
Rdc and are frequency independent.
36

DC losses are negligible for short traces of large crosssections and become
important for long lines of small cross-sectional geometries and for multid r o p t o p o l o g i e s . I n E q u a t i o n 6 , R a c s ym b o l i z e s t h e AC c o n d u c t o r r e s i s t a n c e
per unit length and is the skin depth. R ac can be reduced by widening the
trace width. It varies inversely with and directly with f. When
a s c e r t a i n i n g t h e t o t a l AC r e s i s t a n c e , i t i s n e c e s s a r y t o a l s o a c c o u n t f o r
resistance of return current on the reference plane. Furthermore, the
c o n d u c t o r AC l o s s i s d i r e c t l y r e l a t e d t o R a c a n d h e n c e p r o p o r t i o n a l w i t h t h e
s q u a r e r o o t o f f r e q u e n c y.
Equation 7 is a skin depth expression with being the conductors
conductivity (inverse of resistivity ), 0 is permeability of free space, r
i s c o n d u c t o r s r e l a t i v e p e r m e a b i l i t y a n d f i s s i n e - w a v e f r e q u e n c y. W h e n f i s
in Hz, in Siemens/meter and 0 in Henries/meter (4E-7), then Equation
7 p r o d u c e s i n m e t e r. E q u a t i o n 8 i s a s i m p l i f i e d s k i n d e p t h f o r m u l a
applicable to copper ( = 5.6E7 Siemens/m and r =1), with fmhz being
frequency in MHz and cu in micron.
In Equation 9 diel represents attenuation associated with dielectric
loss 32 in dB/in, fghz is frequency in GHz and Er is substrate dielectric
constant.
FIGURE 10 presents dielectric loss - diel (based on Equation 9) for
several materials, generated with the aid of Mathcad. The curve RO4
( R o g e r s 4 3 5 0 ) d i s p l a ys t h e l e a s t a n d F R - 6 t h e m o s t a t t e n u a t i o n i n t h i s
comparison.
37
NeS (Nelco N4000-13SI), which utilizes S glass, is less lossy than NeE
(Nelco N4000-6 Hi Tg FR4), based on E glass.
A t h i g h f r e q u e n c i e s , f o r t yp i c a l P C B t r a c e d i m e n s i o n s , t h e d i e l e c t r i c l o s s e s
being proportional to frequency can become dominant over conductor DC
l o s s e s ( f r e q u e n c y i n d e p e n d e n t ) a n d AC l o s s e s ( p r o p o r t i o n a l t o f ) .
In addition to conductor and dielectric losses, the effects due to
roughness of conductor surface can be significant. Conductor roughness is
often expressed as tooth structure and the amount of surface variations is
p o r t r a ye d a s t o o t h s i z e . C o n d u c t o r s u r f a c e r o u g h n e s s c a n e f f e c t i v e l y
increase the material resistance when the mean surface roughness is a
38

significant percentage of skin depth. For instance, at a frequency of ~ 200
MHz, the skin depth of copper is 4.667 micron, which approximately equals
t h e t yp i c a l P C B s u r f a c e r o u g h n e s s ( ~ 4 m i c r o n s t o 7 m i c r o n ) . F r e q u e n c y
harmonics exceeding 200 MHz will then deviate from the ideal loss
formulae. For producing low loss interconnects, it is desirable to have
smooth copper foils.
Conclusion
When selecting PCB materials, some parameters that need to be considered
include the conductor and dielectric losses, the electrical characteristics,
the mechanical/thermal properties and the price.
There are other important contemplations involved when ascertaining
optimum materials for PCB stackup, such as impact of glass weave in PCB
laminates on Gigabit per second signals and also meeting standards (IPC
specifications).
39
40
41
42
43
44
Chapter
Asic & Systems Designing / Schematic Drafting

ASIC
An application-specific integrated circuit (ASIC) is an integrated
circuit (IC) customized for a particular use, rather than intended for
general-purpose use. For example, a chip designed solely to run a cell
p h o n e i s a n AS I C . I n t e r m e d i a t e b e t w e e n AS I C s a n d i n d u s t r y s t a n d a r d
integrated circuits, like the 7400 or the 4000 series, are application
specific standard products (ASSPs).
A s f e a t u r e s i z e s h a v e s h r u n k a n d d e s i g n t o o l s i m p r o v e d o v e r t h e ye a r s , t h e
m a x i m u m c o m p l e x i t y ( a n d h e n c e f u n c t i o n a l i t y) p o s s i b l e i n a n AS I C h a s
g r o w n f r o m 5 , 0 0 0 g a t e s t o o v e r 1 0 0 m i l l i o n . M o d e r n AS I C s o f t e n i n c l u d e
entire 32-bit processors, memory blocks including ROM, RAM, EEPROM,
F l a s h a n d o t h e r l a r g e b u i l d i n g b l o c k s . S u c h a n AS I C i s o f t e n t e r m e d a S o C
( S ys t e m - o n - a - c h i p ) . D e s i g n e r s o f d i g i t a l AS I C s u s e a h a r d w a r e d e s c r i p t i o n
l a n g u a g e ( H D L ) , s u c h a s Ver i l o g o r V H D L , t o d e s c r i b e t h e f u n c t i o n a l i t y o f
ASICs.
Field-programmable
gate
a r r a ys
(FPGA)
are
the
modern-day
t e c h n o l o g y f o r b u i l d i n g a b r e a d b o a r d o r p r o t o t yp e f r o m s t a n d a r d p a r t s ;
programmable logic blocks and programmable interconnects allow the same
FPGA to be used in many different applications. For smaller designs and/or
l o w e r p r o d u c t i o n v o l u m e s , F P G A s m a y b e m o r e c o s t e f f e c t i v e t h a n a n AS I C
d e s i g n e v e n i n p r o d u c t i o n . T h e n o n - r e c u r r i n g e n g i n e e r i n g c o s t o f a n AS I C
can run into the millions of dollars.
45
Figure 1: Conventional Circuit
F i g u r e 2 : An AS I C o f a b o v e c i r c u i t
46

T h i n g s t o l o o k a f t e r w h i l e d e s i g n i n g a n AS I C
A n AS I C d e s i g n e r, s e e k i n g t o c r e a t e a n e w d e s i g n , s h o u l d c o n s i d e r t h e
following criteria:
ASIC library content and characteristics:

Does the library contain the logic circuits needed to implement the
d e s i g n ? Ar e t h e c i r c u i t s f a s t e n o u g h ? H o w m a n y c a n f i t o n a s i n g l e d i e ?
Design turn-around-time (TAT):

H o w l o n g d o e s t h e AS I C v e n d o r t a k e t o f a b r i c a t e , p a c k a g e , a n d t e s t
the part once the design is completed?
Price of the die:

H o w m u c h d o e s t h e AS I C c o s t ?
This is an important factor to all designers, but is more crucial to some
customers than others. Those in the consumer market may have this as their
n u m b e r o n e c r i t e r i a w h e n e v a l u a t i n g a n AS I C v e n d o r, w h e r e a s a h i g h - e n d
workstation customer may put performance or function ahead of price.
Pow er consumption:
H o w m u c h p o w e r d o e s t h e AS I C c o n s u m e ?
The importance of power utilization has greatly increased over the past
s e v e r a l ye a r s , a n d s u r p a s s e s t h e i m p o r t a n c e o f c o s t i n s o m e c a s e s , s u c h a s
i n b a t t e r y- p o w e r e d a p p l i c a t i o n s l i k e c e l l p h o n e s a n d l a p - t o p c o m p u t e r s .
Miscellaneous aspects:
P a c k a g i n g o p t i o n s , r e l i a b i l i t y, s u p p l y a s s u r a n c e a n d s e c o n d - s o u r c e
capabilities are absolutely critical to some customers, and of secondary
importance to others.
47
Design methodology:
Design methodology is the process that a designer must follow to
i m p l e m e n t a d e s i g n i n a n AS I C v e n d o r s l i b r a r y. T h e e a s e w i t h w h i c h a
designer
can
execute
this
process
can
affect
time-to-market,
design
v e r i f i c a t i o n a n d r e l i a b i l i t y, a n d t h e c o s t o f t h e o v e r a l l d e s i g n p r o c e s s .
Basic Methodology
T h e r e a r e f o u r b a s i c s t e p s t h a t a n AS I C d e s i g n m u s t g o t h r o u g h i n
order to create working silicon:
1 . d e s i g n e n t r y a n d a n a l ys i s
2. technology optimization and floorplanning
3. design verification
4 . l a yo u t
Advantages
Great er Fu n ct i on al i t y
It is possible to achieve greater functionality with a simpler hardware
design. The required logic can be stored in memory and hence the cost of
supporting additional features is reduced to the cost of the memory
required to store the logic design. This is very much useful in mobile
communication domain where protocol can be easily modified to newer
protocol and stored in memory and then hardware can be reconfigured to
achieve
the
required
f u n c t i o n a l i t y.
Compelling
advantage
includes
increased speed, reduced energy and power consumption. A study reports

that depending on the particular device used moving critical software loops
to reconfigurable hardware results in average energy savings of 35% to
70% with an average speedup of 3 to 7 times. [4]
48
Em bedded Ch aract eri st i c s

In general-purpose computing processors common piece of silicon
could be configured, after fabrication , to solve any computing task. This
meant
many
applications
could
share
commodity
economics
for
the
production of a single IC and the same IC could be used to solve different

problems at different points in time. General-purpose computing meant
e n g i n e e r s c o u l d p r og r a m t h e c o m p o n e n t t o d o t h i n g s w h i c h t h e o r i g i n a l I C
m a n u f a c t u r e r s n e v e r c o n c e i v e d . E m b e d d e d s ys t e m s d e v e l o p e r s a r e m u c h
b e n e f i t e d f r o m r e c o n f i g u r a b l e c o m p u t i n g s ys t e m s , e s p e c i a l l y w i t h t h e
introduction of soft cores which can contain one or more instruction
processors. [4]
All of these "general-purpose" characteristics are shared by reconfigurable
computing. Instead of computing a function by sequencing through a set of
operations in time (like a processor), reconfigurable computers compute a
function by configuring functional units and wiring them up in space. This
allows parallel computation of specific, configured operations, like a
c u s t o m AS I C . Al s o
it
can
also
be
reconfigured.
The
reconfigurable
hardware fabric can be easily and quickly modified from a remote location
to upgrade its performance. It can be modified to perform a completely
different
function.
Hence,
non-recurring
engineering
(NRE)
costs
of
r e c o n f i g u r a b l e c o m p u t i n g a r e l o w e r t h a n t h a t o f a c u s t o m AS I C .
L ower S yst em Cost

B y e l i m i n a t i n g t h e AS I C d e s i g n l o w e r s ys t e m c o s t o n a l o w - v o l u m e
product is achieved. For higher-volume products, the production cost of
f i x e d h a r d w a r e i s a c t u a l l y v e r y m u c h l o w e r. I n t h e c a s e o f AS I C a n d
general purpose hardware designs technical obsolescence drives up the cost
o f s ys t e m s . R e c o n f i g u r a b l e c o m p u t i n g s ys t e m s a r e u p g r a d e a b l e a n d e x t e n d
t h e u s e f u l l i f e o f t h e s ys t e m . T h i s r e d u c e s l i f e t i m e c o s t s .
49
Redu ced Tim e t o Market

Reduced time-to-market is the final advantage of reconfigurable
c o m p u t i n g . S i n c e AS I C i s n o l o n g e r u s e d i n r e c o n f i g u r a b l e c o m p u t i n g l a r g e
amount of development effort is reduced. The logic design remains flexible
even after the product is shipped. Design can be sent to market with
minimum requirements and later additional features can be added without
a n y c h a n g e i n p h ys i c a l d e v i c e ( o r s ys t e m ) . T h u s r e c o n f i g u r a b l e c o m p u t i n g
a l l o w s i n c r e m e n t a l d e s i g n f l o w.
These advantages lead reconfigurable computers to serve as powerful tools
for many applications. The applications include research and development
t o o l s f o r s o p h i s t i c a t e d e l e c t r o n i c s ys t e m s s u c h a s AS I C s a n d p r i n t e d c i r c u i t
b o a r d s ( P C B s ) . S i m u l a t i o n t o o l s f o r t h e s e s ys t e m s d o n o t e x i s t . Al s o
p r o t o t yp e f a b r i c a t i o n i s e x p e n s i v e a n d t i m e c o n s u m i n g . A r e c o n f i g u r a b l e
c o m p u t e r c a n s e r v e a s a n a f f o r d a b l e , f a s t , a n d a c c u r a t e t o o l f o r v e r i f yi n g
electronic designs
Disadvantages
Two
severe
disadvantages
of
reconfigurable
computing
can
be
observed. They are the time that the chip takes to reconfigure itself to a
given
task,
and
the
difficulty
in
programming
such
chips.
D yn a m i c
reconfigurable computing has several different complex issues. They are

design space, placement, routing, timing, consistency and development
t o o l s . E a c h o f t h e s e i s d i s c u s s e d b e l o w.
P l acem en t Issu es
In order to reconfigure a new hardware, it requires having ample
space to place the new hardware. The component placement issue becomes
complex if the component needs to be placed near special resources like
b u i l t - i n m e m o r y, I / O p i n s o r D L L s o n t h e F P G A .
50
Rou t i n g Issu e s
Existing components has to be connected to the components newly
reconfigured. The ports must be available to interface new components. The
s a m e p o r t s m u s t h a v e a l s o b e e n u s e d u n d e r t h e o l d c o n f i g u r a t i o n . To
accomplish this orientation of the components should be in a workable
fashion.
Tim i n g Issu e s
Newly configured hardware must meet the timing requirement for the
efficient operation of the circuit. Longer wires between components may
a f f e c t t h e t i m i n g . O p t i m a l s p e e d s h o u l d b e a t t a i n a b l e a f t e r d yn a m i c a l l y
reconfiguring the device. Over timing or under timing the new added
d e s i g n m a y yi e l d e r r o n e o u s r e s u l t .
Con si st en cy Issu es
S t a t i c o r d yn a m i c r e c o n f i g u r a t i o n o f t h e d e v i c e s h o u l d n o t d e g r a d e
computational consistency of the design. This issue becomes critical when
the FPGA is partially reconfigured and interfaced with existing design.
Adding new components to the device by reconfigurable fabric should not
e r a s e o r a l t e r t h e e x i s t i n g d e s i g n i n t h e d e v i c e . ( O r m e m o r y) . T h e r e s h o u l d
b e s o m e s a f e m e t h o d s t o s t o r e t h e b i t s t r e a m t o t h e m e m o r y.
Devel opm en t Tool s

C o m m e r c i a l d e v e l o p m e n t t o o l s f o r d yn a m i c r e c o n f i g u r a b l e c o m p u t i n g
are still under development stage. The lack of commercially available tools
for the specification to implementation stages of the digital design is still a
bottleneck. The available tools require enormous human intervention to
i m p l e m e n t t h e c o m p l e t e s ys t e m .
51
Electronic System Level ( ESL )

Electronic
emerging
System
electronic
Level
design
(ESL)
design
methodology
that
and
verification
focuses
on
the
is
an
higher
a b s t r a c t i o n l e v e l c o n c e r n s f i r s t a n d f o r e m o s t . T h e t e r m E l e c t r o n i c S ys t e m
Level or ESL Design was first defined by Gartner Dataquest, a leading
E D A - i n d u s t r y- a n a l ys i s f i r m , o n F e b r u a r y 1 s t 2 0 0 1 [ 1 ] . I t i s d e f i n e d i n t h e
E S L D e s i g n a n d Ver i f i c a t i o n b o o k [ 2 ] a s : " t h e u t i l i z a t i o n o f a p p r o p r i a t e
a b s t r a c t i o n s i n o r d e r t o i n c r e a s e c o m p r e h e n s i o n a b o u t a s ys t e m , a n d t o
enhance the probability of a successful implementation of functionality in a
c o s t - e f f e c t i v e m a n n e r."
T h e b a s i c p r e m i s e i s t o m o d e l t h e b e h a v i o r o f t h e e n t i r e s ys t e m u s i n g
a h i g h - l e v e l l a n g u a g e s u c h a s C , C + + , o r M ATL A B . R a p i d a n d c o r r e c t - b yc o n s t r u c t i o n i m p l e m e n t a t i o n o f t h e s ys t e m c a n b e a u t o m a t e d u s i n g E D A
t o o l s s u c h a s H i g h L e v e l S yn t h e s i s a n d e m b e d d e d s o f t w a r e t o o l s , a l t h o u g h
m u c h o f i t i s p e r f o r m e d m a n u a l l y t o d a y. E S L c a n a l s o b e a c c o m p l i s h e d
t h r o u g h t h e u s e o f S ys t e m C a s a n a b s t r a c t m o d e l i n g l a n g u a g e .
E l e c t r o n i c S ys t e m L e v e l i s n o w a n e s t a b l i s h e d a p p r o a c h a t m o s t o f
t h e w o r l d s l e a d i n g S ys t e m - o n - a - c h i p ( S o C ) d e s i g n c o m p a n i e s , a n d i s b e i n g
u s e d i n c r e a s i n g l y i n s ys t e m d e s i g n . F r o m i t s g e n e s i s a s a n a l g o r i t h m
modeling methodology with no links to implementation, ESL is evolving
i n t o a s e t o f c o m p l e m e n t a r y m e t h o d o l o g i e s t h a t e n a b l e e m b e d d e d s ys t e m
design, verification, and debugging through to the hardware and software
i m p l e m e n t a t i o n o f c u s t o m S o C , s ys t e m - o n - F P G A , s ys t e m - o n - b o a r d , a n d
e n t i r e m u l t i - b o a r d s ys t e m s .
52
VARIOUS STEPS OF A DESIGN PROCESS

1. Bl oc k Di agram
Include all major sub-section
Discuss
with
other
departments
(HW (FPGA design),
S W,
Mechanical)
Meets
all
requirements
of
the
PRD
(Product
Requirement
Document)
Wri t e H W F u n c t i o n a l S p e c i f i c a t i o n
2. Co mp on en t S el ect i on
F i r s t s e l e c t c o m p o n e n t s f r o m c o m p a n ys AVL ( A p p r o v e Ven d o r
List)
Select new components
Note price and availability (lead-time)
A r e s a m p l e s a v a i l a b l e f o r p r o t o t yp e t i m e f r a m e ?
P u b l i s h b i l l - o f - m a t e r i a l t o b u ye r s
Identify long lead-time components
Request
evaluation
boards
when
necessary
(HW
and
SW
development)
3. P ow er Est i mat e
Prepare table showing min/max power per component on power

rail basis
53
4. S W d r i v e r s a v a i l a b i l i t y
5. P ow er Su p p ly Desi gn
Is power sequencing required?
Identify input voltage
I d e n t i f y a l l p o w e r r a i l s ( + 1 V, + 1 . 1 V, + 1 . 2 V, + 1 . 2 5 V, + 2 . 5 V,
+ 3 . 3 V, + 5 V )
6. S u b- b l oc k Di agra ms
Power supply
Reset
Clocks
J TAG
7. Mech an i cal
PCB Outline
I d e n t i f y f i x e d l o c a t i o n c o m p o n e n t s ( L E D s , c o n n e c t o r s , S F P,
mounting holes location)
PCB thickness
Airflow
Power supply location
External connector location
54
8. Lay out G u i d el in es
Critical components placement
Critical trace routing requirements (data and clock lines, diff

pairs)
L a ye r s s t a c k - u p
PCB impedance requirements
Special impedance requirement for certain traces (Ethernet,

etc.)
Clocks (max. length)
Identify matched length traces
EMI control
9. S i mu l at i on for co mponent s heat prof i l e
Using max power and air-flow (linear feet)
10. Man u f actu ri n g Ap proval s
L a yo u t v e r i f i c a t i o n ( c o m p o n e n t p l a c e m e n t )
11. Test i n g P roced u res
S t e p - b y- s t e p i n s t r u c t i o n s f o r t e s t i n g v o l t a g e s , c l o c k s a n d d a t a
& control paths
55
SCHEMATIC DRAFTING
Schematic diagram are used to represent graphically the components
and interconnections
of electrical
circuits. A schematic
is the ideal
representation of a circuit. Engineer usually drew up rough schematic by

h a n d . T h e c i r c u i t w a s t h e n p r o t o t yp e d o n w i r e - w r a p b o a r d . O n c e t h e c i r c u i t
was debugged, the drafting department redraw the schematic and start the
P C B l a yo u t . F o r s c h e m a t i c d r a f t i n g , d i f f e r e n t t o o l s a r e u s e d l i k e C o n c e p t
H D L , O r C a d a n d v i e w d r a w, e t c .
S o s ym b o l s d e v e l o p m e n t & s ym b o l s w i r i n g w i t h t h e i r e l e c t r i c a l
attributes is called Schematic Drafting. Netlist and BOM (Bill of Material)
are exported from Schematic.
56
Netlist
Netlist is the file which is generated from schematic (.dsn) file and
imported into the board (.brd or .pcb, etc) file. This is a numerical form of
the graphical work of the schematic. Board file reads netlist (.net or .txt or
.tel or .dat) file and collects all data in its database, meaning the data
which board file gets from netlist is used for further work on the board
file. Netlist file contains following information:
1- Footprint names.
2- Device names (The device file has the information of quantity of used
pins of the footprints, pin functions and pin names).
57

3 - Q u a n t i t i e s o f t h e d i f f e r e n t t yp e s o f f o o t p r i n t s .
4- Pin functions & pins properties
5- Information of nets
BOM
Bill Of Material contains following information:
1- Quantity of the components which are going to be used in board.
2 - Typ e s o f c o m p o n e n t s .
3 - C o m p o n e n t Val u e s .
4- Manufacturer & Manufacturer part number of the components which
are going to be soldered on board.
5- Descriptions of the components (information about the components,
i t s t yp e s , e t c . )
6- Board Footprint names.
B O M i s g e n e r a t e d f r o m s c h e m a t i c a n d t h i s i s u s e d i n b u yi n g
components of the board. Microsoft Excel is used for the BOM.
Chapter
the
PCB Components & Board Mechanical

Footprint generation & Types of Components
58

Nearly all PCBs will use some components that must be soldered to
the board. Each of these components must have a footprint. Most PCB
l a yo u t s o f t w a r e c o m e s w i t h a l i b r a r y o f p a r t s , b u t yo u w i l l o f t e n n e e d t o
m a k e n e w f o o t p r i n t s f o r p a r t s n o t i n t h e l i b r a r y.
T h e r e a r e t h r e e t yp e s o f t e c h n o l o g i e s u s e d f o r c o m p o n e n t s . T h e s e a r e
S M T t e c h n o l o g y, P T H t e c h n o l o g y a n d D u a l t e c h n o l o g y ( S M T & P T H ) . T h e
details of them are given as follows:
SMT Components:
S M T s t a n d s f o r S u r f a c e m o u n t t e c h n o l o g y. T h e s e c o m p o n e n t s a r e
mounted on footprint on top OR bottom side of the board. They are placed
59

on the board by pick and place machine and stick on the board via solder
paste material.
PTH Components:
P T H s t a n d s f o r p l a t e d t h r o u g h h o l e t e c h n o l o g y. T h e s e c o m p o n e n t s a r e
mounted on footprint on top OR bottom side of the board but the pins are
inserted all through the board. These components can be placed manually or
with special clamping tools. Pins are soldered on the side opposite to the
mounted side.
60
Dual technology (PTH & SMT):

T h e s e c o m p o n e n t s h a v e b o t h S M T a n d P T H p i n s . G e n e r a l l y d i f f e r e n t t yp e s
o f c o n n e c t o r s h a v e b o t h ( S M T & P T H ) t yp e s o f p i n s .
61
Board Mechanical
T h e r e a r e d i f f e r e n t t yp e s o f P C b o a r d u s e d i n d e f e r e n t t yp e s o f
products like mother boards, mobile boards, router boards and other
e l e c t r o n i c b o a r d s , e t c . D u e t o p h ys i c a l a n d e l e c t r i c a l l i m i t a t i o n s b o a r d s i z e
in X axis, Y axis and thickness varies. Components interfacing or
connecting to other boards or devices which have fixed locations are shown
i n t h e M O C ( M e c h a n i c a l o u t l i n e c o n t r o l ) . Too l i n g h o l e s a n d m o u n t i n g h o l e s
locations are also included in MOC.
62
Post PCB Designing
Chapter
DFM
'''Design
for
manufacturability
(DFM) '''
is
the
general
engineering art of designing products in such a way that they are

easy to manufacture.
The basic idea exists in almost all engineering
disciplines, but of course the details differ widely depending on the

m a n u f a c t u r i n g t e c h n o l o g y.
As described above that DFM is a technical term and abbreviation of
D e s i g n f o r M a n u f a c t u r a b i l i t y, w h i c h m e a n s t h a t w e a r e t o c h e c k t h e
given design (PCB) from every aspect and to verify that the given
data is issue less.
T h e r e a r e s e v e r a l c h e c k s t h a t w e r u n t o f i n d t h e i s s u e s i f a n y, t h e s e
checks are called DFM analysis checks. Given below are the main
checks that we run prior to PCB fabrication.
1- Signal layers checks.
2- Power/ground checks.
3- Solder mask checks.
4- Drill checks.
T h e r e a r e s o ma n y o t h e r t h i n g s i n D F M w e h a v e t o c h e c k m a n u a l l y
like
thermal
design;
plane
split
width,
isolated
connections,
reference plane for the impedance traces and etc.
63
GERBER DATA
A PCB is fabricated as a series of layers that the manufacturer
assembles into a board through a variety of chemical and mechanical
processes.
To
fabricate
each
physical
layer
in
the
PCB
the
manufacturer uses an image of that layer -- this image is referred to

as a phototool. A phototool is a piece of clear film, with black lines,
circles and other shapes forming exactly the same patterns as the
c o n t e n t o f t h a t l a y e r i n Au t o T R A X .
Gerber data is a simple, generic means of transferring printed circuit
board information to a wide variety of devices that convert the
e l e c t r o n i c P C B d a t a t o a r t w o r k p r o d u c e d b y a p h o t o p l o t t e r. Vir t u a l l y
every
PCB
CAD
system
generates
Gerber
data
because
all
photoplotters read it. It is a software structure consisting of X,Y

coordinates supplemented by commands that define where the PCB
image starts, what shape it will take, and where it ends. In addition
to the coordinates, Gerber data contains aperture information, which
defines the shapes and sizes of lines, holes, and other features.
After finalizing the design, Gerber files are generated to send to
Fabrication House. The machines read these file and prepare the
board.
Fabrication
This is the process to make the printed circuit boards. Printed
circuit board (PCB) fabrication services design and fabricate circuit
boards. They differ from electronic manufacturing services, which
p o p u l a t e a n d a s s e m b l e b o a r d s . Al t h o u g h c a p a b i l i t i e s v a r y f r o m
64

supplier
to
supplier,
printed
circuit
board
fabrication
services
perform activities such as PCB design and layout, prototyping and

production,
and
testing
and
evaluation.
Some
PCB
fabrication
services offer just-in-time ca pa bi lit ies. Ot he rs specializ e in si nglesided,
double-sided,
mul ti-layer,
or
flexible
boards.
Board
components are mounted with either through-hole technology (THT)

or surface mount technology (SMT).
65
Board Tes ting

Unpopulated boards may be subjected to a bare-board test
where each circuit connection (as defined in a netlist) is verified as
correct on the finished board. For high-volume production, a Bed of
nails test er, a fi xt ure or a Ri gi d nee dle ada pter is used t o make
contact with copper lands or holes on one or both sides of the board
to facilitate testing. A computer will instruct the electrical test unit
to apply a small voltage to each contact point on the bed-of-nails as
required, and verify that such voltage appears at other appropriate
contact points. A "short" on a board would be a connection where
there should not be one; an "open" is between two points that should
be connected but are not. For small- or medium-volume boards,
flying-probe and flying-grid testers use moving test heads to make
contact with the copper/silver/gold/solder lands or holes to verify
the electrical connectivity of the board under test.
66
Ass em bly
The process to place/solder the components on the board file is
c a l l e d As s e m b l y. Af t e r t h e p r i n t e d c i r c u i t b o a r d ( P C B ) i s c o m p l e t e d ,
electronic components must be attached to form a functional printed
circuit assembly or PCA (sometimes called a "printed circuit board
assembly" PCBA). In through-hole construction, component leads are
inserted in holes. In surface-mount construction, the components are
placed on pads or lands on the outer surfaces of the PCB. In both
kinds
of
construction,
component
leads
are
electrically
and
m e c h a n i c a l l y f i x e d t o t h e b o a r d w i t h a m o l t e n m e t a l s o l d e r.
67
Final product ready for shipment

After final test the final product OR Master board is ready to work.
When the final board works successfully it means this design is
r e a d y f o r m a s s p r o d u c t i o n . H o w e v e r, t h i s d e s i g n c a n i m p r o v e w i t h
minor changes to meet the current market requirements like to get
more functions and better performance etc.
Finally the manufactured board is packed and handed over manually
or sent to customer via shipment.
68
PCB GLOSSARY
Chapter
GLOSSARY OF SMT INDUSTRY TERMS
A
Acceptance tests
A set of tests performed to determine the acceptability of a PCB.
Additive process
A method for manufacturing PCB conductive patterns via selective
deposition
of
conductive
material
( c o p p e r,
s o l d e r,
etc.)
on
substrate.
Adhesion
The attraction force between materials of unlike composition.
Angle of attack
The angle between the squeegee's face and the stencil plane.
Anisotropic adhesive
A material filled with particles that will conduct current in the Z-axis
o n l y. ( A l s o c a l l e d Z - a x i s a d h e s i v e . )
Application-specific integrated circuit (ASIC)

An IC designed for a specific function or product.
Aqueous cleaning
A water-based cleaning methodology which may include the addition
of the following chemicals: neutralizers, saponifiers and surfactants.
Array
A group of components arranged in rows and columns.
69
Artw ork
T h e P C B c o n d u c t i v e p a t t e r n t o p r o d u c e t h e p h o t o g r a p h i c m a s t e r. I t
can be made at any scale but generally is 3:1 or 4:1.
Aspect ratio
The ratio of the thickness of the PCB to the diameter of its smallest
via hole. A via hole with aspect ratio greater than three may be
susceptible to cracking.
Automatic test equipment (ATE)

H a r d w a r e t h a t a u t o m a t i c a l l y a n a l yz e s f u n c t i o n a l o r s t a t i c p a r a m e t e r s
for performance. It also may be designed to automatically check
assemblies
for
fault
isolations
or
individual
components
for
f u n c t i o n a l i n t e g r i t y.
Azeotrope
A mixture of two or more polar and nonpolar solvents that acts as a
single solvent (boiling point is lower than that of either of its
components) to remove both polar and nonpolar contaminants.
B
Ball grid array (BGA)
An IC package with solder balls that are arranged in a grid pattern
and act as the input/output points.
Bed-of-nails test
A volume PCB test method in which a fixture containing springloaded contact probes engages specific points on a board to identify
defective parts.
Blind via
A c o n d u c t i v e c o n n e c t i o n b e t w e e n t h e o u t e r l a ye r o f a P C B t o a n i n n e r
l a ye r t h a t d o e s n o t c o n t i n u e t o t h e o p p o s i t e s i d e .
70
Blowhole
A large void in the solder connection created by rapid outgassing
during the soldering process.
Bonding agent
A n a d h e s i v e f o r b o n d i n g i n d i v i d u a l l a ye r s t o f o r m a m u l t i l a ye r
laminate.
Bonding layer
An
adhesive
l a ye r
for
laminating
the
separate
substrates
of
m u l t i l a ye r b o a r d .
Boundary scan
A self-test method for active components in which a built-in test bus
is used to access input/output pins.
Breakaway panels
PCBs held together with breakaway tabs to make handling, placement
and soldering easier and more efficient. Boards are snapped apart at
the end of processing.
Bridging
Errant molten solder that spans two conductors (bridges) to complete
an unwanted connection, causing an electrical short.
Buried via
A c o n d u c t i v e c o n n e c t i o n b e t w e e n t w o o r m o r e i n n e r l a ye r s o f a P C B
( i . e . , i t i s i n v i s i b l e f r o m t h e o u t e r l a ye r s ) .
Burn-in
A technique to electrically stress devices to detect possible failures
before mounting them in assemblies.
Butt joint
A surface mount device lead that is sheared so that the end of the
lead contacts the board land pattern.
71
C
CAD/CAM systems
A computer-aided design/manufacturing method for translating circuit
designs into actual products. They may assist in performing all steps
in artwork generation.
Capillary action
The combination
of force, adhesion and cohesion that prompts
l i q u i d s , s u c h a s m o l t e n s o l d e r, t o f l o w u p w a r d b e t w e e n c l o s e l y s p a c e d
solid surfaces, e.g., lead (contact) and pad.
Carriers
Holding devices for PCBs and other parts to facilitate handling
during component placement, soldering and other processing.
Castellation
Metallized semicircular radial features on the edges of LCCCs that
i n t e r c o n n e c t c o n d u c t i n g s u r f a c e s . C a s t e l l a t i o n s t yp i c a l l y a r e f o u n d o n
a l l f o u r e d g e s o f a l e a d l e s s c h i p c a r r i e r. E a c h l i e s w i t h i n t h e
termination area for direct attachment to the land patterns.
Chip component
A generic term for any two-terminal leadless surface mount passive
devices, such as resistors and capacitors.
Chip-on-board (COB) technology

Generic term for any component assembly technology in which an
unpackaged silicon die is mounted directly on PCB. Connections to
the board can be made by wire bonding, tape automated bonding
( TAB ) o r f l i p c h i p b o n d i n g .
72
Chip scale package (CSP)

A high-density IC packaging process in which the package is slightly
larger than the chip (less than 1.5 times the chip area).
Chlorinated fluorocarbon (CFC)

C a u s e s d e p l e t i o n o f o z o n e l a ye r a n d s c h e d u l e d f o r r e s t r i c t e d u s e b y
the
Environmental
Protection
Ag e n c y.
CFCs
are
used
in
air
conditioning, foam insulation and solvents.
Cladding
A t h i n l a ye r o f m e t a l f o i l b o n d e d t o a s u b s t r a t e t o f o r m t h e
conductive PCB pattern.
Clamshell fixture
An in-circuit test fixture that permits probing both sides of a board at
once. The top probe section is hinged to allow PCB insertion.
Coefficient of thermal expansion (CTE)

The rate of material expansion measured in ppm per C when the
material's surface temperature is increased.
Cold joint
A
solder
connection
exhibiting
poor
adhesion
and
g r a yi s h
appearance because of insufficient heat, poor fluxing or solder

impurities.
Column grid array (CGA)

IC package in which the input and output points are high-temperature
s o l d e r c yl i n d e r s o r c o l u m n s a r r a n g e d i n a g r i d p a t t e r n .
Condensation inert curing

An adhesive curing method using an inert atmosphere as the heattransfer medium.
73
Condensation inert heating

A general term referring to condensation heating where the part to be
h e a t e d i s s u b m e r g e d i n t o a h o t , r e l a t i v e l y o x yg e n - f r e e v a p o r. T h e
p a r t , b e i n g c o o l e r t h a n t h e v a p o r, c a u s e s t h e v a p o r t o c o n d e n s e o n t h e
p a r t , t r a n s f e r r i n g i t s l a t e n t h e a t o f v a p o r i z a t i o n t o t h e p a r t . Al s o
known as vapor phase soldering.
Conductive adhesive
A
bonding
material
with
metallic
powders
added
to
establish
e l e c t r i c a l c o n d u c t i v i t y.
Conductive ink
The paste used on thick film materials to form the circuit pattern,
usually containing metal, metal oxide and solvent.
Constraining core substrate

A c o m p o s i t e P C B c o n s i s t i n g o f e p o x y- g l a s s l a ye r s b o u n d t o a l o w
thermal expansion core material, such as copper-invarc o p p e r, g r a p h i t e - e p o x y a n d a r a m i d f i b e r - e p o x y. T h e c o r e c o n s t r a i n s
t h e e x p a n s i o n o f t h e o u t e r l a ye r s t o m a t c h t h e e x p a n s i o n c o e f f i c i e n t
of ceramic chip carriers.
Continuity test
A test for the presence of current flow between two or more
interconnected points.
Convection/IR
A solder reflow oven for SMD interconnect that combines convection
and infrared (IR) radiation heating.
Conveyor
A
PCB
transporting
s ys t e m
for
moving
assemblies
to
various
p r o c e s s e s . An e d g e c o n v e yo r s u p p o r t s t h e b o a r d s a t o p p o s i t e s i d e s ;
74

t h e m e s h c o n v e yo r f u l l y s u p p o r t s t h e b o a r d ; t h e s e c o n d a r y c o n v e yo r
is located below the edge mechanism to catch fallen components
d u r i n g s o l d e r r e f l o w.
Curing agent
A chemical added to a resin to stimulate a final set or hardening.
D
Delamination
A s e p a r a t i o n o f t h e l a ye r s o f a s u b s t r a t e o r b e t w e e n i t a n d t h e
conductive cladding.
Dendritic grow th
A branching of solder filaments ("whiskers") at interconnect
sites because of the presence of moisture or electrical
threatening an electrical short.
bias,
Design for manufacturability (DFM)

Designing a product to be produced in the most efficient manner
possible
in
terms
of
time,
cost
and
resources,
taking
into
consideration how the product will be processed, and using the

e x i s t i n g s k i l l b a s e t o a c h i e v e t h e h i g h e s t yi e l d s p o s s i b l e .
Desoldering methods
Disassembling solder parts to repair or replace by wicking, sucking,
heat and pull, or solder extraction.
Dewetting
A defect owing to inadequate cleaning via flux in which the solder
coating recedes, leaving irregular material deposits.
Dielectric constant
A m e a s u r e o f a m a t e r i a l ' s a b i l i t y t o s t o r e e l e c t r i c a l e n e r g y, e . g . , t h e
b a s i c q u a l i t y o f a c a p a c i t o r.
75
Direct chip attach (DCA)

The bonding of a die to a substrate.
Dispensing (syringe)
A p p l i c a t i o n o f a d h e s i v e s b y p r e s s u r i z e d ( h yd r a u l i c o r p n e u m a t i c )
force for a specific period required to emit an "appropriate" amount
of material through the needle and onto the target location.
Dispersant
A c h e m i c a l a d d i t i v e t o w a t e r t o i m p r o v e p a r t i c u l a t e r e m o v a b i l i t y.
Documentation
Information for a PCB that explains the electromechanical design
c o n c e p t , t yp e s a n d q u a n t i t i e s o f p a r t s a n d m a t e r i a l s , s p e c i a l
instructions, and revisions.
Drawbridging
A soldering defect in which a chip is drawn into an upright position
r e p r e s e n t i n g a n o n c o n n e c t i o n . Al s o c a l l e d t o m b s t o n i n g .
Dual in-line package (DIP)

A package intended for through-hole mounting that has two rows of
leads extending at right angles from the base with standard spacing
b e t w e e n l e a d s a n d r o w.
Dual solder wave

A wavesoldering process in which an initial "wave" of molten solder
covers all PCB surfaces contacted. It is followed by a second laminar
or "flat" wave that serves to "finish" the board by removing all solder
bridges and icicles.
E
Electroless copper
Copper plating deposited from a plating solution as a result of a
chemical reaction and without the application of an electrical current.
76
Electrolytic copper
Copper plating deposited from a plating solution by the application of
an electrical current.
Epoxy
A p o l ym e r i c f a m i l y o f t h e r m o s e t t i n g r e s i n s g e n e r a l l y
adhering components to metallic or substrate surfaces.
used
for
Eutectic
The alloy of two or more metals that has a lower melting point than
e i t h e r o f i t s c o n s t i t u e n t s . E u t e c t i c a l l o ys , w h e n h e a t e d , t r a n s f o r m
directly from a solid to a liquid and do not show pasty regions.
F
Fabrication
The bare-board manufacturing process, which begins after design but
b e f o r e a s s e m b l y. I n d i v i d u a l p r o c e s s e s i n c l u d e l a ye r l a m i n a t i o n , m e t a l
addition/subtraction, drilling, plating, routing and cleaning.
Fiducial
A specific mark along the edge of a PCB's circuit pattern used by
m a c h i n e v i s i o n s ys t e m s t o c o n f i r m p r o p e r a r t w o r k o r i e n t a t i o n .
Fillet
(1) A radius or curvature imparted to inside meeting surfaces. (2) The
concave junction formed by the solder between the footprint pad and
the SMD lead or pad.
Fine pitch
A center-to-center lead distance of surface mount packages of 0.025"
or less.
Flatpack
An IC package with gull wing or flat leads on two or four sides, with
s t a n d a r d s p a c i n g b e t w e e n l e a d s . C o m m o n l y, t h e l e a d p i t c h e s a r e a t
0.05" centers, but lower pitches also may be used.
77
Flip chip
A leadless structure that is electrically and mechanically connected to
the substrate via contact lands or solder bumps.
Flip chip technology

A COB technology in which the silicon die is inverted and mounted
directly to the PCB. Solder is deposited on the bonding pads in
vacuum. When inverted, they make contact with the corresponding
board lands and the die rests directly above the board surface. It
p r o v i d e s t h e u l t i m a t e i n d e n s i f i c a t i o n . Al s o k n o w n a s C 4 ( c o n t r o l l e d
collapse chip connection).
Flood bar
A d e v i c e o n a s t e n c i l p r i n t i n g s ys t e m t h a t d r a g s s o l d e r p a s t e
back to the starting point after the squeegee has made a printing
stroke.
Flying probe tester

C o m p u t e r - c o n t r o l l e d s ys t e m s i n w h i c h c o n t a c t s a r e
specific nodes on a board to complete an electrical test.
directed
to
Footprint
A nonpreferred term for land pattern.
Functional test
An electrical check of the entire assembly that simulates its intended
operating environment.
G
Glass transition temperature (Tg)
T h e t e m p e r a t u r e a t w h i c h a p o l ym e r c h a n g e s f r o m a h a r d a n d
relatively brittle condition to a viscous or rubbery condition. This
transition generally occurs over a relatively narrow temperature
range. It is not a phase transition. In this temperature range, many
p h ys i c a l p r o p e r t i e s u n d e r g o s i g n i f i c a n t a n d r a p i d c h a n g e s , s u c h a s
hardness, brittleness, thermal expansion and specific heat.
Golden
A component or assembly already tested as functional to spec and used, via
c o m p a r i s o n s , t o t e s t s i m i l a r u n i t s . Al s o k n o w n a s a k n o w n g o o d b o a r d .
78
Gull wing lead

A l e a d c o n f i g u r a t i o n t yp i c a l l y u s e d o n s m a l l o u t l i n e p a c k a g e s w h e r e
l e a d s a r e b e n t o u t w a r d l y. An e n d v i e w o f t h e p a c k a g e r e s e m b l e s a
gull in flight.
H
Halides
Compounds containing fluorine, chlorine, bromine, iodine or astatine.
T h e s e m a t e r i a l s m a y b e p a r t o f a s o l d e r f l u x s ys t e m a c t i n g a s t h e
a c t i v a t o r. T h e r e s i d u e s a r e c o r r o s i v e a n d m u s t b e r e m o v e d .
Hardener
A chemical added to a thermosetting resin to assist its cure.
Heat-and-pull
A desoldering technique using a soldering iron equipped with a
device that heats, grasps and pulls component leads to be removed.
Hi-pot test
A test for high potential, generally conducted at 40 V or more.
Hot-air solder leveling (HASL)

A process in which a solder-coated board is subjected to heated highvelocity air to blow the molten material from plated through-holes
and to even-out solder thickness.
I
Icicle
An unacceptable solder point that protrudes out of a solder joint, but
d o e s n o t m a k e c o n t a c t w i t h a n o t h e r c o n d u c t o r.
In-circuit test (ICT)

A
c o m p o n e n t - b y- c o m p o n e n t
test
within
circuit
for
electrical
function to verify proper placement and orientation.
In-line placement
A m e t h o d o f P C B a s s e m b l y p e r m i t t i n g c o n v e yo r i z e d b o a r d h a n d l i n g
into and out of the component placement equipment.
79
Induction soldering
A n i n t e r c o n n e c t m e t h o d i n w h i c h s o l d e r, g e n e r a l l y p r e f o r m s , i s
reflowed.
Inductor
A p a s s i v e c o m p o n e n t , m e a s u r e d i n H e n r ys , t h a t c a u s e s c h a n g e s i n
current flow to lag behind changes in voltage.
Input/Output (I/O)
Refers to a device's number of interfaces (pins) to receive or transmit
data.
Integrated circuit (IC)

A combination of interconnected circuit elements
associated on or within a continuous substrate.
inseparably
J
J-lead
A l e a d c o n f i g u r a t i o n t yp i c a l l y u s e d o n p l a s t i c c h i p c a r r i e r p a c k a g e s
w h i c h h a v e l e a d s t h a t a r e b e n t u n d e r n e a t h t h e p a c k a g e b o d y. A s i d e
view of the formed lead resembles the shape of the letter "J."
Jumper
An electrical connection between points on a board, generally added
after its fabrication.
Just-in-time (JIT)
M i n i m i z i n g i n v e n t o r y b y s u p p l yi n g m a t e r i a l a n d c o m p o n e n t s d i r e c t l y
to the manufacturing line just before incorporating them into the
product.
K
Known good die (KGD)
Semiconductor die that has been tested and is known to function to
specification.
L
Land
A p o r t i o n o f a c o n d u c t i v e p a t t e r n u s u a l l y, b u t n o t e x c l u s i v e l y, u s e d
for component connection, attachment or both.
80
Land pattern
Component mounting sites located on the substrate that are intended
for the interconnection of a compatible surface mount component.
Leadless ceramic chip carrier (LCCC)

A ceramic, hermetically sealed IC package commonly used for
military applications. The package has metallized castellations on
four sides for interconnecting to the substrate.
Leaching
The dissolution of a metal coating, such as silver and gold, into
l i q u i d s o l d e r. N i c k e l b a r r i e r u n d e r p l a t i n g i s u s e d t o p r e v e n t l e a c h i n g .
Also known as scavenging.
Lead configuration
The solid formed conductors that extend from a component and serve
as a mechanical and electrical connection that is readily formed to a
desired configuration. The gull wing and J-lead are the most common.
Lead pitch
The distance between successive center of the leads of a component
package. The lower the lead pitch, the smaller the package area for a
given pin count in a package.
Line certification
Assurance that a production line sequence is under management and
will produce reliable PCBs in compliance with requirements.
Liquidus
The temperature at which a solder becomes molten (vs. solidus).
M
Mean time between failure (MTBF)
The statistical average time interval, usually in hours, to be expected
between operating unit failures.
Metal electrode leadless face (MELF)

A s u r f a c e m o u n t d e v i c e t h a t i s a r o u n d , c yl i n d r i c a l , p a s s i v e
component with a metallic cap termination located at each end.
81
Multichip module (MCM)

A circuit comprised of two or more silicon devices bonded directly to
a s u b s t r a t e b y w i r e b o n d , TAB o r f l i p c h i p .
Multilayer board
A P C B t h a t u s e s m o r e t h a n t w o l a ye r s f o r c o n d u c t o r r o u t i n g . I n t e r n a l
l a ye r s a r e c o n n e c t e d t o t h e o u t e r l a ye r s b y w a y o f p l a t e d v i a h o l e s .
N
No-clean paste
A very low-residue soldering paste having a solids content between
2.1 and 2.8 percent by weight.
No-clean soldering
A soldering process that uses a specially formulated solder paste that
does not require the residues to be cleaned after solder processing.
O
Odd-form
The form or configuration of a nonstandard component (e.g., various
transformers, coils, large connectors) that may be difficult to handle
by automatic placement equipment.
Omegameter
An instrument that measures ionic residues on PCBs by immersing an
assembly into a water/alcohol mixture having a known high
r e s i s t i v i t y, a n d b y m e a s u r i n g a n d r e c o r d i n g t h e d r o p i n r e s i s t i v i t y
because of ionic residue taken over a specified period.
Outgassing
A deaeration or gaseous adhesive emission on a PCB under reduced
pressure or heat.
P
Packaging density
The number of parts (passive/active components, connectors, etc.)
p l a c e d o n a P C B ; e x p r e s s e d a s l o w, m e d i u m o r h i g h .
82
Pad
A p o r t i o n o f a c o n d u c t i v e p a t t e r n u s u a l l y, b u t n o t e x c l u s i v e l y, u s e d
for the connection, attachment or both of components.
Photoplotter
Basic artwork processing equipment for producing
patterns (usually actual size) on photographic film.
master
PCB
Pick-and-place
A programmable method of component placement using machines to
a u t o m a t i c a l l y p i c k p a r t s f r o m a f e e d e r, t h e n m o v e t o a p r e c i s e
location on a PCB and place them in the correct site.
Pin grid array (PGA)

IC package in which the input and output points are through-hole pins
arranged in a grid pattern.
Placement rate
T h e s p e e d o f a c o m p l e t e c o m p o n e n t p l a c e m e n t c yc l e b e g i n n i n g w i t h
component/part pick-up, move to the placement site and the return to
the feeding source.
Plastic leaded chip carrier (PLCC)

A component package that has J-leads on four sides with standard
spacing between leads.
Preheat
That part of the solder reflow process at which a board is conditioned
for peak temperatures via heating from ambient.
Prepreg
Sheet material (e.g., glass fabric) impregnated with a resin cured to
an intermediate stage (B-stage).
Pretinning
The coating of a component's leads or board pads with a material,
u s u a l l y s o l d e r, t o i m p r o v e o v e r a l l s o l d e r a b i l i t y d u r i n g a s s e m b l y o r
r e p a i r.
Printed circuit assembly (PCA)

General
term
for
PCB
fully
assembled
with
all
electrical,
electromechanical and mechanical components.
83
Printed circuit board (PCB)

The
general
term
for
It
includes
configurations.
completely
rigid
or
processed
flexible,
printed
single,
circuit
double
or
m u l t i l a ye r b o a r d s . A s u b s t r a t e o f e p o x y g l a s s , c l a d m e t a l o r o t h e r
material upon which a pattern of conductive traces is formed to
interconnect components. (Also called a printed wiring board.)
Probing systems
Equipment for high-reliability testing of PCBs, components and
assemblies. Probing devices range from manual for lab use to lowv o l u m e t e s t v i a c o m p u t e r - c o n t r o l l e d s ys t e m s .
Q
Quad flat pack (QFP)
A term used for SMT packages with leads on all four sides. Most
c o m m o n l y u s e d t o d e s c r i b e p a c k a g e s w i t h g u l l w i n g l e a d s . Al s o
known as a flat pack, but flat packs may have gull wing leads on
either two or four sides.
R
Reflow soldering
A
process
of
joining
metallic
surfaces
through
the
mass
heating/cooling of preplaced solder paste between two surfaces (i.e.,

component leads and PCB pads).
Repair
Restoring the functional capability of a defective.
Resist
Coating material used to mask or protect selected areas of a pattern
from the action of an etchant, solder or plating.
84
Rework
Repetition of a manufacturing process to bring an assembly into
compatibility with a spec or contract requirement.
Rheology
A term describing the viscosity and surface tension properties of
solder pastes or adhesives.
Rosin flux
The mildest (and least effective) of solder fluxes, generally used in
no-clean soldering. A variant, RMA (rosin mildly active), is the most
used material for electrical interconnect.
Rotational error
The angular displacement of a component's axes as a result of
c e n t e r i n g m e c h a n i s m i n a c c u r a c y.
S
Saponifier
An aqueous solution of organic or inorganic base and additives for
dispersing and removing rosin and water-soluble flux residues via
chemical reaction as a detergent solution.
Schematic
A d r a w i n g ( p l a n ) t h a t u s e s s ym b o l s t o r e p r e s e n t c i r c u i t p a t t e r n s ,
including electrical connections, parts and functions.
Semi-aqueous cleaning
This cleaning technique involves a solvent cleaning step, hot water
r i n s e s a n d a d r yi n g c yc l e .
Single-center reflow soldering

A process in which both surface mount, held by adhesives, and
through-hole components are reflow soldered.
Skew
Describing the misalignment of a component or device to its proper
mounting site.
85
Slump
A spreading of material (solder paste, adhesive, thick film, etc.) after
s t e n c i l p r i n t i n g b u t b e f o r e c u r i n g . An e x c e s s i v e s l u m p d e t r a c t s f r o m
d e f i n i t i o n . I f l o s s o f d e f i n i t i o n i s t h e r e s u l t a f t e r r e f l o w, i t i s c a u s e
for rework.
Small-outline integrated circuit (SOIC)

An IC surface mount package with two parallel rows of gull wing
leads with standard spacing between leads and rows.
Small-outline transistor (SOT)

A discrete semiconductor surface mount package that has two gull
w i n g l e a d s o n o n e s i d e o f t h e p a c k a g e a n d o n e o n t h e o t h e r.
Snapback
The return of a stencil to normal (flat plane) after its deflection by a
squeegee across its surface.
Soak
That part of the solder reflow process in which internal temperature
differences
between
components
are
permitted
to
equalize
(stabilization).
Solder ball
A defect in which small spheres of solder separate from the main
body of material forming the solder joint. Causes include excessive
oxides or moisture in the solder paste.
Solder bumps
The spherical solder materials bonded to a passive or active device
contact area that serves as connections to circuit pads.
Solder paste
A h o m o g e n e o u s a m a l g a m o f s o l d e r p a r t i c l e s o r p o w d e r, f l u x , s o l v e n t
a n d a g e l o r s u s p e n s i o n a g e n t f o r a u t o m a t e d s o l d e r j o i n t a s s e m b l y.
86
Solder preforms
Special solder forms or configurations, frequently coming as stamped
washers,
spheres
or
formed
wire,
that
generally
contain
predetermined alloy and a flux core or coating.
Solder side
In assembly of plated through-hole components, the term refers to the
s o l d e r e d s i d e o f t h e P C B . Wit h S M T, i t m e a n s t h e s e c o n d a r y s i d e
generally is limited to passive chip parts.
Solderability
The ability of a conductor (lead, pad or trace) to be wetted (become
solderable) to form a strong bond.
Soldermask
A PCB processing technique in which all surfaces are covered by a
plastic coating except those for connections to be soldered.
Solids content
The weight percentage of rosin (solids) in a flux formula.
Solidus
The temperature at which some components of the solder alloy begin
to melt (liquidus).
Solvent
Any solution capable of dissolving a solute. In the electronics
i n d u s t r y, a q u e o u s , s e m i - a q u e o u s a n d n o n o z o n e - d e p l e t i n g s o l v e n t s a r e
used.
Solvent cleaning
The removal of organic and inorganic soils using a blend of polar and
nonpolar organic solvents.
Squeegee
A rubber or metal blade used in stencil printing to wipe solder paste
across the stencil's face, forcing the material through the patterned
apertures and onto the PCB.
87
Stencil
A metal sheet bearing a circuit pattern cut into the material. Common
materials are stainless steel and brass.
Surface Insulation Resistance (SIR)

A test for surface insulation resistance, a measure in ohms of the
material's electrical resistance between conductors.
Surface mount device (SMD)

A
registered
service
mark
of
North
Am e r i c a n
Philips
Corp.
( A s s e m b l e o n ) t o d e n o t e r e s i s t o r s , c a p a c i t o r s , S O I C s a n d S O Ts.
Surface mount technology (SMT)

A m e t h o d o f a s s e m b l i n g P C B s o r h yb r i d c i r c u i t s i n w h i c h c o m p o n e n t s
are mounted onto the surface rather than inserted into through-holes.
Surfactant
A chemical added to water to lower its surface tension to improve
wetting for cleaning.
T
Tape automated bonding (TAB)
The process of bonding the IC die to patterned inner leads on plastic
tape and, in a subsequent operation, positioning and bonding the
outer leads to the surface of the substrate.
Tape-and-reel
Method of housing parts in separate cavities in a long continuous
strip. The cavities are covered with a plastic sheet to facilitate
winding the strip around a reel for component presentation or
"feeding" to automated placement equipment.
Test coupon
A test pattern as an integral part of a PCB on which nondestructive
e l e c t r i c a l c h e c k s m a y b e m a d e t o e v a l u a t e a n a s s e m b l y.
88
Thixotropic
T h e c h a r a c t e r i s t i c o f a l i q u i d o r g e l t h a t i s v i s c o u s w h e n s t a t i c , ye t
f l u i d w h e n p h ys i c a l l y " w o r k e d . "
Through-hole (plated)
A drilled or punched hole through a substrate, which is metallized to
electrically
connect
the
board's
two
sides
and
inner
l a ye r s
of
c i r c u i t r y.
Tombstoning
A s o l d e r i n g d e f e c t i n w h i c h a c h i p - t yp e p a r t i s " p u l l e d " i n t o a
vertical or near-vertical position with only one of its terminals
c o n n e c t e d . I t i s c a u s e d b y f o r c e i m b a l a n c e s d u r i n g s o l d e r r e f l o w.
(Also called drawbridging.)
Tooling holes
Holes on a PCB or panel of boards for accurate positioning to
facilitate handling and component placement.
Tube feeder
A parts packaging method in which parts are inserted back-to-back in
a conductive (anti-static) plastic tube or stick. Indexing for feeding
to the placement tool may be accomplished by vibration or spring
action.
Type I, II, III assembly

Designating PCB assemblies: (I) SMDs mounted on one or both sides
of the board; (II) mixed technology having leaded (through-hole)
parts mounted on the primary side and SMDs on one or both sides;
and (III) mixed technology featuring passive SMDs on the secondary
side and leaded components mounted to the primary side.
89
U
Ultra-fine pitch
A center-to-center lead distance of surface mount packages of 0.4 mm
or less.
Underwriters Laboratories Inc. (UL)

An independent testing organization that evaluates performance and
safety of electrical equipment.
Unit under test (UUT)

A term applied to any component or assembly being tested by
automatic testing equipment.
V
Vacuum pickup
A parts handling instrument through which a vacuum force secures
and holds them for placement.
Vapor phase
A mass soldering technique in which the high-temperature vapor of a
h yd r o c a r b o n , c o n d e n s i n g o n t h e s o l d e r j o i n t s o f a P C B , i s t h e h e a t transfer medium.
Vapor phase reflow

A process in which the PCB is sent through a sealed chamber of
heated vaporized inert fluorocarbon that condenses on the joint,
c a u s i n g t h e s o l d e r t o r e f l o w.
Via hole
A p l a t e d t h r o u g h - h o l e c o n n e c t i n g t w o o r m o r e c o n d u c t o r l a ye r s o f a
m u l t i l a ye r p r i n t e d b o a r d . T h e r e i s n o i n t e n t i o n t o i n s e r t a c o m p o n e n t
lead inside a via hole.
90
Void
The absence of material in a localized area.
W
Wave soldering
A process of joining metallic surfaces by passing them through a
w a v e o f c o n t i n u o u s l y c i r c u l a t i n g m o l t e n s o l d e r. S M D s a r e h e l d i n
place during wave soldering with adhesives and are mounted on the
secondary side (wave side) of the PCB.
Wetting
In soldering, flux reduces the surface tension of the metal to achieve
the bonding of a relatively uniform, smooth film of solder to the
surface of the metal.
Wicking
Absorption of liquid by capillary action along the fibers of the base
metal.
Y
Yield
The ratio of good assemblies at the end of processing to the number
initially entered.
91

PCB Designing Final Project

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PRINTED CIRCUIT BOARD (PCB) DESIGNING

electronic packaging found in almost every consumer electronics product.

A c o r r e c t d e s i g n m i n i m i z e s w i r i n g l e n g t h s a n d l a ys o u t t h e b o a r d s o s i g n a l integrity issues are controlled. It also makes it much easier to find

PRINTED CIRCUIT BOARD (PCB) DESIGNING

EVOLUTION & INDUSTRY OVERVIEW

PRINTED CIRCUIT BOARD (PCB) DESIGNING

permitting top and bottom circuitry to be electri cally interconnected. These

LARGEST PCB PRODUCERS:

Samsung Electro -Mech

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

TABLE 1- 2. WO RLD ELECTRO N ICS EQ UIP MEN T

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

Regardless of what we call them, printed circuit boards provide a

PRINTED CIRCUIT BOARD (PCB) DESIGNING

competition, high capital equipment costs, and demanding environmental

There is no danger of PCBs being replaced in the next decade,

board is becoming more of

PRINTED CIRCUIT BOARD (PCB) DESIGNING

How PCB is Made

How to Make PCB's

relatively easy to make inexpensive high quality PCB's at home.

PRINTED CIRCUIT BOARD (PCB) DESIGNING

The Shopping List

PRINTED CIRCUIT BOARD (PCB) DESIGNING

The Artw ork

PRINTED CIRCUIT BOARD (PCB) DESIGNING

1. I cut the Press-n-Peel film in half for small boards

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PRINTED CIRCUIT BOARD (PCB) DESIGNING

PCB Designing Flow Process

products like Mobiles, Computers, toys, CNC machines, automobile

System designer design a system according to

Schematic diagram are used to represent graphically the

components and interconnections of electrical circuits.

Nearly all PCBs will use some components that must be

PRINTED CIRCUIT BOARD (PCB) DESIGNING

All information of schematic is imported into the board

To place all symbols/components according to circuit

wise and board requirement is called Placement.

Design For Manufacturing (DFM).

The checks which are run on tool level to notify the

After finalizing the design, Gerber files are generated

to send to Fabrication House. The machines read

PRINTED CIRCUIT BOARD (PCB) DESIGNING

The process to place/solder the components on the

This is final process which is performed on final

After final test the final product OR Master board will

be ready to work. When the final board works

PRINTED CIRCUIT BOARD (PCB) DESIGNING

STACKUP & IMPEDANCE CALCULATION

PRINTED CIRCUIT BOARD (PCB) DESIGNING

Use of 1.0 ounce copper foil is quite popular in PCB fabrication;

PRINTED CIRCUIT BOARD (PCB) DESIGNING

Ground and power planes perform multiple functions, one of which is to

interplane capacitance which is important in the stack-up design of highspeed PCBs.

PRINTED CIRCUIT BOARD (PCB) DESIGNING