PIC Part5 Interrupts

PIC Basic Interrupt Structure and
Programming
Interrupt I/O
Interrupts capabilities are desirable when a

system must be responsive to external,
asynchronous events
CpE 112 : Klinkhachorn
Polling I/O
Start device and poll for completion
Program Execution
.
.
Start Device
Input status
Poll and Wait
Until Device Ready
Interrupt I/O
Start device and continue program execution
Program Execution
.
.
Start Device
.
.
.
.
ISR
Procedure
For device
Service
Routine
.
RETURN
PIC Interrupt Sequence

When interrupt occurs
CPU automatically pushes the return address in
the Program Counter on to the stack
CPU clears the Global Interrupt Enable (GIE)
bit (disable further interrupts)
This is it ..no other registers or W are
automatically set aside!!!!!
16F87X Interrupt
The PIC16F87X family has up to 14
sources of interrupt.
Timer0 interrupt
External interrupt on RB0/INT (programmable edge trigger)
PortB change interrupt (RB7:RB4)
Parallel Slave Port interrupt
Analog to digital interrupt
UART Receive interrupt
UART Transmit Empty interrupt
Synchronous Serial Port interrupt
Compare/Capture/PWM-1 interrupt
Timer2 interrupt
Timer1 interrupt
EEPROM interrupt
Bus Collision(I2C) interrupt
Compare/Capture/PWM-2 interrupt
16F87X Interrupt Logic
Power-down Mode: SLEEP

Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running
the PD/ bit (STATUS<3>) is cleared
the TO/ (STATUS<4>) bit is set
the oscillator driver is turned off

the I/O ports maintain the status they had before the
SLEEP instruction was executed (driving high, low, or
hi-impedance)
Wake-up from SLEEP

One of the following events can wake
up the CPU
External reset input on MCLR/ pin
Watchdog Timer Wake-up (if WDT was
enabled)
Interrupt from INT pin, RB port change, or
some peripheral interrupts (e.g. PSP read/write,
TMR1, CCP, SSP, USART RX, TX, A/D, and
EEPROM write operation
Wake-up through an Interrupt Event

The corresponding interrupt enable bit must
be set
If global interrupt is disabled
The CPU continues execution at the instruction after
the SLEEP instruction
If global interrupt is enabled

The CPU executes the instruction after the SLEEP
instruction and then branches to the interrupt vector
(004h)
Wake-up from SLEEP through Interrupt
Interrupt Control Register

The interrupt control register (INTCON)
records individual interrupt requests in

flag bits
It also has individual and global interrupt
enable bits.
7
Global Interrupt Enable

A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts
When bit GIE is enabled, and an interrupts flag bit and mask
bit are set, the interrupt will vector immediately
Individual interrupts can be disabled through their
corresponding enable bits in various registers
Individual interrupt bits are set, regardless of the status of
the GIE bit
The GIE bit is cleared on RESET.

The return from interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit,

which reenables interrupts.
Code Template
Explanatory remarks
Assembler directives
Equates to give names to numbers
Variable definitions
Reset and interrupt vector
A table
Mainline code and its subroutines
Initialization code
Interrupt service routine
Systematic handling of W and STATUS
Polling routine
Specific interrupt handling subroutine
Reset and interrupt vector (same Page)
org H000
goto mainline
;Reset vector
;start main program
org H004
;Interrupt vector
goto IntService ;jump to ISR
;if the ISR is located in the same Program
; Memory bank of the main program otherwise
; save W, Status, PCLATH
; then select the proper bank (PCLATH<4:3>)
;before jump to ISR!
Initialization code for Interrupts

Mainline .
.
;initialize any required registers and variables
;Enable any required interrupt mask, e.g. INTE.
;
bsf INTCON, INTE ; Enable external interrupt
..
;Then enable Global Interrupt
bsf INTCON, GIE
; Enable global interrupts
Interrupt service routine (same Page)

IntService
;save W and Status Registers
movwf
swapf
W_temp
STATUS,W
; store W in W_Temp
;move status to W
;without affecting z bit!
movwf Status_Temp
;save STATUS
;Polling interrupt flag and goto specific interrupt handler routines
;do what it need to be done
.
;on exit
;restore STATUS and W then return
swapf
Status_Temp,W
;restore STATUS (swap nibbles)
movwf STATUS
;without affecting z bit!
swapf
W_temp,F
;swap W_temp
swapf
W_temp, W
;swap again to restore W
;without affecting z bit
retfie
;Return to . and reenable the interrupts
Reset and interrupt vector (different page)

org H000
goto mainline
;Reset vector
;start main program
org H004
;Interrupt vector
movwf
swapf
movwf
swapf
movwf
bsf
goto
;store W in W_Temp
;move status to W without affecting z bit!
;save STATUS
;move PCLATH to W without affecting z bit!
;save PCLATH
;Switch to page 1
W_temp
STATUS,W
Status_Temp
PCLATH, W
PCLATH_Temp
PCLATH,3
IntService
;jump to ISR
Interrupt service routine (different page)

IntService
;Polling interrupt flag and goto specific interrupt handler routines
;do what it need to be done
.
;on exit
; ON exit restore PCLATH, STATUS and W

swapf PCLATH_Te mp, W
;Restore PCLATH
m ovwf PCLATH
;Move W into PCLATH
swapf Status_Te mp,W
;Swap Status_Te mp register into
;(sets data me mory bank to original state)
m ovwf STATUS
swapf W_Tem p,F
swapf W_Tem p, W
Retif
;Move W into STATUS register

;Swap W_Tem p
;Swap W_Tem p into W
;Bye
Interrupt: Polling and Service Interrupt

IntService
;Polling routine
btfsc Register_Nam e,Flag_bit;Arrange from the
;highest priority
;interrupt source
goto Interrupt_A
;if set, do it!
btfsc ...
;check next highest
;priority
goto ...
;if set, go for it
.
.
;repeat until get to the lowest interrupt source
Done
;restore the necessary registers
Interrupt: CCS PIC C-Complier

#Priority rtcc,rb,.. ;set interrupt priority
;The highest is first
#INT_GLOBAL Na me()
{
//your codes
}
;replace the co mplier

;interrupt dispatcher
;you must take care
;all of registers saving
;and etc.

#INT_xxx Na me()
{
; your codes
}
CCS support the following:
INT_EXT (External Interrupt)
INT_RTCC (Timer0 [RTCC] overflow)
INT_RB
(Change on B4-B7 PIN)
INT_AD
(A/D Converter)
INT_TIMER1 (Timer1 overflow)
INT_SSP (S mart Serial Port (SPI,I2C))
INT_PSP (Parallel Slave Port)
...

DISABLE_INTERRUPTS(XXX)
W here XXX is
Global
(GIE)
INT_RB
INT_AD
(A/D Converter)
Exa mple: disable_interrupts(global);

ENABLE_INTERR UPTS(XXX)
W here XXX is
Global
(GIE)
INT_RB
INT_AD
(A/D Converter)
Exa mple: enable_interrupts(global);
INT Interrupt (External)

External interrupt on the RB0/INT pin is edge triggered
rising, if bit INTEDG (OPTION_REG<6>) is set
falling, if the INTEDG bit is clear
When a valid edge appears on the RB0/INT pin, flag bit
INTF(INTCON<1>) is set
can be disabled by clearing enable bit INTE (INTCON<4>)
Flag bit INTF must be cleared in software in the interrupt service
routine before reenabling this interrupt

The INT interrupt can wake-up the processor from SLEEP, if bit
INTE was set prior to going into SLEEP
The status of global interrupt bit decides whether or not the
processor branches to the interrupt vector following wakeup.
External Interrupt: CCS PIC C-Complier

EXT_INT_EDGE(edge)
W here edge is
L_to_H
H_to_L
Exa mple: ext_int_edge(L_to_H);
EXT Interrupt : Example

Rotary Encoder - rotary pulse generator (RPG)
Applications
Volume and Tone Control forAudio Visual Equipment
Tuner for Communication Units
Mode selection for Measurement
Rotary Encoder: Example

Available in mechanical (few $) or optical ($10+)
Rotary Encoder: Example

Phase Difference
One cycle
ON/OFF
determines CCW/CW
INT_EXT Interrupt : Example

Main Program
.
.
.
.
enable_interrupts(int_EXT);
enable_interrupts(global);
.
.
.
INT_EXT Interrupt : Example

#int_ext
EXT_INT_ISR()
{
// one interrupt per cycle
// determine direction by reading the another bit
// do what is necessary
// exit
}
Note: CCS will reset INTE flag and re-enable GIE.
These do not applied to #int_Global!
INT_RB Interrupt : Example

Port B <4:7>
External Inputs
PIC16F877

Main Program
.
.
.
.
enable_interrupts(int_RB);
enable_interrupts(global);
.
.
.

#int_rb
RB_ISR()
{ Byte changes;
changes = last_b ^ port_b;
last_b = port_b;
if (bit_test(changes,4) && !bit_test(last_b,4))
{ // bit 4 went low do something.}
.
.
delay_ms(10);
//debouncing! Not recommended!
}
Note: CCS will reset RBinterrupt flag and re-enable GIE.
These do not applied to #int_Global!
TIMERs/COUNTERs
PIC16F877
Timer0
Timer1
Timer2
Timer0 Module
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Timer0/WDT Block diagram
Timer0 - Prescaler Assignment
Watch Dog Timer

Run on internal RC
If enable during SLEEP mode, WDT will
continue running and will be able to wake up
the processor on Time-out!
With Prescaler (Post) set to 1:128, typical
maximum delay time can be approximately
18*128 ms or over 2 seconds!
Timer0 - TMR0 - Register

All instructions writing to the TMR0 will clear
the prescaler count, but not change the

prescaler assignment!
i.e. clrf TMR0, movwf TMR0, .etc.
The TMR0 interrupt is generated when the
TMR0 register overflows from FFh to 00h

TMR0 interrupt cannot awaken the processor
from SLEEP (the timer is off during the
SLEEP)
Timer0 - Registers associated
Timer1 Module
16-bit timer/counter (TMR1H,TMR1L)
Readable and writable (both)
Internal or external clock select
Interrupt on overflow from FFFFh to 0000h
Reset from CCP module trigger
Programmable Prescaler (1,2,4, and 8)
Sync and Asyn Counter mode
Timer1Block diagram
Timer1 - T1CON - Control Register
Timer1 Oscillator
Low power Oscillator rated upto 200kHz
Primary intended for a 32kHz
Will run during SLEEP
Timer1 - TMR1H:TMR1L
The register pair (TMR1H:TMR1L)
increments from 0000h to FFFFH and rolls

over to 0000H
Interrupt if enabled (TMR1IE) on overflow
(set TMR1IF)
Timer2 Module
8-bit timer (TMR2)
8-bit period register (PR2)
Readable and writable (both)
Interrupt on TMR2 match of PR2
Programmable Prescaler (1,4, and 16)
Programmable postscaler (1 to 16)
Can be use as the PWM time-base for PWM mode of the
CCP module
SSP module optional use of TMR2 output to generate clock
shift
Timer2 Block diagram
Timer2 - T2CON - Control Register
Timer2 - TMR2
The prescaler and postscaler counters are
cleared when any of the following occurs:

A write to the TMR2
A write to the T2CON
Any device reset
TMR2 is not cleared when T2CON is written

PIC Part5 Interrupts

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PIC Part5 Interrupts

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PIC Basic Interrupt Structure and

Interrupts capabilities are desirable when a

CpE 112 : Klinkhachorn

CpE 112 : Klinkhachorn

CpE 112 : Klinkhachorn

PIC Interrupt Sequence

automatically set aside!!!!!

CpE 112 : Klinkhachorn

16F87X Interrupt Logic

CpE 112 : Klinkhachorn

Power-down Mode: SLEEP

the oscillator driver is turned off

CpE 112 : Klinkhachorn

Wake-up from SLEEP

Wake-up through an Interrupt Event

If global interrupt is enabled

CpE 112 : Klinkhachorn

Wake-up from SLEEP through Interrupt

CpE 112 : Klinkhachorn

Interrupt Control Register

records individual interrupt requests in

CpE 112 : Klinkhachorn

Global Interrupt Enable

enables (if set) all unmasked interrupts, or disables (if

The GIE bit is cleared on RESET.

the interrupt routine, as well as sets the GIE bit,

CpE 112 : Klinkhachorn

Reset and interrupt vector (same Page)

CpE 112 : Klinkhachorn

Initialization code for Interrupts

Interrupt service routine (same Page)

Reset and interrupt vector (different page)

CpE 112 : Klinkhachorn

Interrupt service routine (different page)

; ON exit restore PCLATH, STATUS and W

;(sets data me mory bank to original state)

;Move W into STATUS register

CpE 112 : Klinkhachorn

Interrupt: Polling and Service Interrupt

CpE 112 : Klinkhachorn

Interrupt: CCS PIC C-Complier

;replace the co mplier

CpE 112 : Klinkhachorn

Interrupt: CCS PIC C-Complier

Interrupt: CCS PIC C-Complier

Exa mple: disable_interrupts(global);

CpE 112 : Klinkhachorn

Interrupt: CCS PIC C-Complier

Exa mple: enable_interrupts(global);

CpE 112 : Klinkhachorn

INT Interrupt (External)

routine before reenabling this interrupt

CpE 112 : Klinkhachorn

External Interrupt: CCS PIC C-Complier

CpE 112 : Klinkhachorn

EXT Interrupt : Example

CpE 112 : Klinkhachorn

Rotary Encoder: Example

CpE 112 : Klinkhachorn

Rotary Encoder: Example

INT_EXT Interrupt : Example

CpE 112 : Klinkhachorn

INT_EXT Interrupt : Example

CpE 112 : Klinkhachorn