Microprocessor

Microprocessor is programmable electronic device capable of operating on numerical data with

basic arithmetic and logic processing, guided by instructions presented to it in binary coded
form.
Components of microprocessor
Control unit
arithmetic-logic unit
temporary storage
internal electrical communication lines- bus.
The basic job of microprocessor
Data processing consists of
get instruction
get data
execute the instruction to process the data
store the result data.
Use of microprocessor
The automatic data processing capability of the microprocessor has been widely implemented in
Data processing system.
Components of data processing system
It consists of hardware and software components.
Hardware component
Electronic components connected together to process data- microprocessor, system memory,
input-output devices, system bus
Software component
Controlling software the operating system.
Function of components of microprocessor based system:
a) Microprocessor
1. Sequential control of system,
2. Arithmetic & logic processing of data,
3. Temporary storage of result data.
b) System memory
1. Program storage,
2. Numerical data storage.
c) Input / output devices
1. Accept program instructions & data from the outside world,
2. Outputs (display, print etc.) processed information.

d) Bus: Bus is the number of parallel signal lines by which the groups of modules of a computer
system are interconnected electrically.
Type of bus originating from microprocessor
a) data bus: used to transfer data between the connected units.
b) address bus: to specify the source or destination of data.
c) control bus: carries synchronization signals. Microprocessor uses them to provide control
and timing signals to peripheral devices.
interrupt line
The line contained in the control bus, which carries an interrupt request from IO controller
to microprocessor.
e) Operating system: The program which runs all the time and manages the resources of
computer i.e., IO devices, memory, CPU time etc., error handling, processes user commands,
controls program execution.
Representation of hardware components of microprocessor based system:
a. Basic system: Microprocessor / system memory / system bus.
i. Topological Representation:
System
bus

Microprocessor

System
memory

b. Complete system: Microprocessor / system memory / input output devices / system bus.
i. Topological Representation:
IO
devices

System
bus

Microprocessor

System
bus

ii. Connection diagram:

D

MPU
A C

IO devices

D- data bus
A- address bus
C- control bus
System
memory

System bus

System
memory

Basic Input Devices:

Key board, Mouse
Basic output Devices:
Display monitor, Printer

Digital information processing system

Use microprocessor based data processing system with appropriate IO devices for the purpose of
1. Data acquisition,
2. Process control manipulate data and create feedback signals to control various processes in
real time.
Advantages of microprocessor based system:
Digital information processing gives greater flexibility in
1. Easily reconfigurable information processing systems (no need of change in hardware
components)
2. evaluation of complex mathematical function,
3. creation of numerical models of engineering designs,
4. sequential switching operations involved in the control of equipment,
5. simple decision functions such as electronic code lock,
6. transmission / storage of data without deterioration,
7. saving in space, power due to microscopic digital circuits,
8. low cost, high speed, simplicity, reliability, etc.
Basic operations of digital information processing (refer to figure below)
i
Translation: requires the conversion of information into a suitable numerical code,
ii
Manipulation: results in the formation of new numbers related to the original numbers by
some mathematical operation,
iii Storage: requires recording of numbers on some storage medium,
iv Feed back: creation of signal to control the real time processes.
Components of digital information processing system (refer to figure below)
1) Transducers: Transducer is a device to translate one type of signal into an equivalent electrical
signal or vice versa.
2) Analog to digital converter [ADC]: Analog to digital converter translates analog signals
over a specified range into binary coded number.
3) Digital to analog converter [DAC]: Digital to analog converter produces an electrical
voltage output from a binary coded number input.
4) Basic data processing system: Microprocessor & system memory
General representation of digital information processing

4 Basic data
processing
system
System
memory

i Translation

Input
(Nonelectric
signal)

1 Transducer

1Transducer
Output
(Nonelectric
signal
for process control)

Analog
signal
(electrical)

2 A/D
converter

Digital signal
(sequence of
numbers)

Microprocessor

ii manipulation
Analog
signal
(electrical)

3 D/A
converter

iv feedback

Digital signal
(processed)

iii storage

Interface
Boundary (signal connection point) between two parts of a system so that information can be
transferred between them.
Microprocessor interfacing
Linking the microprocessor and input / output [IO] devices through system bus.
Components of microprocessor interface with IO devices
a) Micro-processor, b) IO controller, d) IO device.
.
Microprocessor interface with IO devices diagram
Microprocessor

IO
Controller

IO
device

IO Controller: It converts data & control information from microprocessor interface to the
specific signal required by the peripheral device. They are also known as port memory.
Functions of IO controller
a) Data conversion : match signal format,
b) Synchronization : match timing characteristic of microprocessor and IO device.
c) Device selection.
Popular interface controllers:
1
Parallel IO controller - (parallel port)
2
Serial synchronous / asynchronous IO controller - (serial port)
3
Universal Serial Bus controllers
4
Programmable timer
5
Programmable interrupt controller
Types of digital information processing system:
a. Microprocessor based system
b. Microcontroller based system
Microprocessor based system
A microprocessor system consists of a microprocessor with memory, input ports and output ports
connected to it externally. It is used in systems dealing with large code and data.
Diagram of microprocessor [MPU] based system
D
A
MPU

System
memory
C

Parallel
port

Serial
port

Timer

Microcontroller [MCU] based system

A microcontroller is a single chip containing a microprocessor, memory, input ports and output
ports. Since all four blocks reside on the one chip, a microcontroller is much faster than a
microprocessor system but code and data are very concise.
Diagram of microcontroller
Control
Unit

RAM

Timer

Arithmetic
logic unit

ROM

Interrupt

Parallel port

Serial port

External
memory
Interface

8051 microcontroller based system design

a) Very simple architecture, b) Versatile features of data processing and process control.
Information necessary to use a microprocessor / microcontroller
a) pinout diagram of MPU / MCU, b) register set (programming model), c) instruction set
(opcode / mnemonics ) and addressing modes, and d) typical circuit diagram.
These information are provided by the manufacturer of the MPU / MCU .
Schemetic inputs and outputs of 8051
VCC

GND

XTAL1
System
Inputs

RESET
EA
Control
Signals

Port 0

Port 1

Port 2

Port 3

XTAL2

8051

External
World
Interface

PSEN
ALE

1 System inputs
Vcc power supply and GND ground.
XTAL 1 and XTAL 2 - system clock inputs from crystal clock circuit.
RESET - to initialize microcontroller to default values and to make a new start.

2 control signals for external memory interfacing

EA- External Access
PSEN- Program Store Enable
ALE- Address Latch Enable (ALE).
If there is no requirement of external memory interfacing then, EA pin is pulled high (connected
to Vcc) and PSEN and ALE are not connected
3 Ports for external interfacing.
Port 0, Port 1, Port 2 and Port 3
Each port has 8 I/O lines and they all are bit programmable.
Pinout diagram of 8051
Pinout diagram shows the
designation of the pins
originating from the MCU
chip (pin number and
signal).

Pin configuration of 8051,

Pin #
Designation
Pins 1 8
Port 1: Quasi bi directional I/O port with internal pull up resistors.
Pin 9
RESET: Sets the 8051 microcontroller to its initial values. The RESET
pin must be set high for 2 machine cycles.
Pins 10 17
Port 3: Quasi bi directional port with internal pull up resistors and
multiplexed with signals shown below
P 3.0 [RxD]: serial communication signals RxD
P 3.1 [TxD]: serial communication signals TxD
P 3.2 [/INT0]: external interrupt # 0
P 3.3 [/INT1]: external interrupt # 1
P 3.4 [T0]: timer input # 0
P 3.5 [T1]: timer input # 1
P 3.6 [/WR]: control signals for external memory interfacing WR

P 3.7 [/RD]: control signals for external memory interfacing RD

Pins 18 and 19 Crystal: to provide system clock.
Pin 20
Vss: ground (0 V).
Pins 21-28
Port 2 (P2.0 [A8] to P2.7 [A15]) : Quasi bi directional I/O port and
multiplexed with higher order address bus signals.
Pin 29
PSEN: Program Store Enable used to read signal from external
program memory.
Pin 30
/EA: External Access - used to enable external memory interfacing. If
there is no external memory requirement, this pin is pulled high by
connecting it to Vcc.
Pin 31
ALE: - Address Latch Enable - used to demultiplex the address-data
signal of port 0 (for external memory interfacing.) 2 ALE pulses are
available for each machine cycle.
Pins 32-39
Port 0 (P0.0 [AD7] to P0.7 [AD0]): I/O port multiplexed with lower
order address and data bus signals (to serve the purpose of external
memory interfacing). This is a bi directional I/O port and external pull
up resistors are required to function this port as I/O.
Pin 40
Vcc: Main power source.
Simplified internal Architecture of 8051
External
Interrupts

Interrupt
control

Program
Memory
(4KB)

RAM
(128 Bytes)

Bus
Control

I/O Ports

Timer 0
Timer 1

Counter
Inputs

Central
Processing
Unit

OSC

(P0 P1 (P2 P3)

Serial
Port
TxD RxD

Crystal
P0 P1 P2 P3
Address
Data

Register set
These are the registers contained in the MPU which can be accessed by a programmer with the
help of instructions provided by manufacturer of the MPU. These registers are also known as
programming model.
Memory Architecture of 8051
8051 has a separate memory space for code (program) and data referred to as Harvard
architecture.

Types of 8051 memory

On-chip memory contained in the MCU,
External memory can be connected to MCU using interface circuits.
8051 chip

FFFFh

Internal
Memory

0000h

External Data
Memory
(max. 64 KB)
RAM

Internal
SFRs
FFFFh

Internal
RAM

0000h

External Code
Memory
(max. 64 KB)
ROM

Internal Memory
The on-chip memory of 8051 consists of 256 bytes of memory:
First 128 bytes:
00h to 1Fh
Register Banks
20h to 2Fh
Bit addressable RAM
30h to 7Fh
General purpose RAM
Next 128 bytes:
80h to FFh
Special function Registers

The first 128 bytes is also

known as internal RAM
(IRAM)

Representation of Internal RAM

Byte addressBit addressb7 b6 b5 b4
b3 b2 b1 b07Fh

Internal
Memory

30h
General Purpose
RAM area
80 bytes

FFh

Special
Function
Registers
[SFR]

2Fh7F 7E 7D 7C 7B 7A 79 78Bit

addressable memory
area2Eh77 76 75 74 73 72 71

70

2Dh6F 6E 6D 6C 6B 6A

80h
7Fh
Internal
RAM
[IRAM]

69 682Ch67 66 65 64 63 62 61 60
2Bh5F 5E 5D 5C

00h

5B 5A 59 582Ah57 56 55 54 53 52
51 50

29h4F 4E

4D 4C 4B 4A 49 4828h47 46 45 44
43 42 41 40
27h3F 3E 3D 3C 3B 3A 39 3826h37
36 35 34 33 32 31 30
25h2F 2E 2D 2C 2B 2A 29
2824h27 26 25 24 23 22 21 20
23h1F 1E 1D 1C 1B
1A 19 18
22h17 16 15 14 13 12 11 10
21h0F 0E 0D 0C
0B 0A 09 08

20h07 06

05 04 03 02 01 001Fh
18hREGS 0..7 (bank 3)Register

banks17h
10hREGS 0..7 (bank 2)0Fh

Register bank 0
07h
06h
05h
04h
03h
02h
01h
00h

REG.7
REG.6
REG.5
REG.4
REG.3
REG.2
REG.1
REG.0

00hREGS 0..7 (bank 0)

Register Banks: 00h to 1Fh (32 bytes)

The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5, R6, and R7).
These registers are used in instructions such as:
ADD A, R2 ; adds the value contained in R2 to the accumulator
Also
ADD A, 02h : R2 can also be referred to by its location 02h in the Internal RAM
There are 4 register banks- 0 to 3 in the Internal RAM each containing registers R0 through R7.
Register bank switching is done through PSW (flag) register.
Bit Addressable RAM: 20h to 2Fh (16 bytes)
Starting from address 20h to 2Fh there are 128 memory bits numbered 00h to 7Fh that can be set
(1) or cleared (0) individually - known as bit variables
A bit variable can be set with a command SETB and cleared with a command CLR.
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)
Note, bit 25h is actually bit b5 of Internal RAM location 24h.
But if a program writes a byte to location 20h, for example, it writes 8 bit variables, bits 00h to
07h at once.
General Purpose RAM: 30h to 7Fh (80 bytes)
These 80 bytes of Internal RAM memory are available for general-purpose data storage.
These can also be used by the system stack.
The general purpose RAM can be accessed using direct or indirect addressing modes.

Direct addressing mode

MOV A, 6Ah ; reads contents of address 6Ah to accumulator

Indirect addressing modes (using registers R0 or R1)

MOV R1, #6Ah ; move value 6Ah to R1
MOV A, @R1 ; R1 contains address of Internal RAM from where data is moved to A.
(Prefix - # specifies data constant and - @ specifies pointer)

Special Function Registers [SFR]

The SFR registers are located within the Internal Memory in the address range 80h to FFh,
Each SFR has an address (within the range 80h to FFh) and a name which reflects the
purpose of the SFR.
Only 21 SFR registers are defined in the 128 byes of the SFR address space in the standard
8051 MCU,

Some of the SFR registers are bit addressable,

SFRs are accessed just like normal Internal RAM locations.

Representation of SFR registers

Byte addressBit addressSFR
Namesb7 b6 b5 b4 b3 b2 b1 b0 FFhF0hF7
F5

F4

F3

F2 F1 F0B*E0hE7

E6 E5

F6

E4 E3

E2 E1 E0A* (accumulator)D0hD7 D6 D5 D4 D3
D2 D1 D0PSW*B8h-B8IP*B0hB7 B6
(P3*)A8hAF
A6
A5

--

--

B5 B4 B3

BC BB BB B9
B2 B1 B0Port 3

--- AC AB AA A9 A8IE*A0hA7
A4
A3
A2
A1
A0Port 2

(P2*)99hSBUF98h9F

9E

9D

98SCON*90h97 96

95 94

9C

9B

9A

Internal
Memory

99

93 92 91 90Port 1

(P1*)8DhTH18ChTH08BhTL18AhTL089hTMOD88h8F
8E
8D
8C
8B
8A
89

FFh

88TCON*87hPCON83hDPH82hDPL81hSP80h87 86
85 84 83 82 81 80Port 0 (P0*)
* indicates the bit addressable SFR registers

Special
Function
Registers
[SFR]

80h
7Fh

00h

Internal
RAM
[IRAM]

Port Registers SFR

The standard 8051 has four 8 bit I/O ports: P0, P1, P2 and P3.
For example Port 0 is a physical 8 bit I/O port on the 8051.
Read (input) and write (output) access to this port is done in software by accessing the SFR P0
register which is located at address 80h.
SFR P0 is also bit addressable. Each bit corresponds to a physical I/O pin on the 8051.
Example: Access to port 0
SETB P0.7 ; sets the MSB bit of Port 0
CLR P0.7 ; clears the MSB bit of Port 0

The operand P0.7 refers to bit 7 of SFR P0.

The P0.7 bit can also be addressed by accessing bit location 87h.
CLR 87h
PSW Program Status Word
PSW, the Program Status Word is at address D0h and is a bit-addressable register.
Program status word (PSW) flags
Symbol
Bit
Address
C (or CY)
PSW.7
D7h
AC
PSW.6
D6h
F0
PSW.5
D5h
RS1
PSW.4
D4h
RS0
PSW.3
D3h
OV
PSW.2
D2h
PSW.1
D1h
P
PSW.0
D0h

Description
Carry flag
Auxiliary carry flag
Flag 0
Register bank select 1
Register bank select 0
Overflow flag
Reserved
Even Parity flag

Carry flag. C
This is a carry, or borrow flag used in arithmetic operations.
The carry flag is also used as the Boolean accumulator for Boolean instruction operating at the
bit level.
Auxiliary carry flag. AC
This is a auxiliary carry (half carry) for use in BCD arithmetic.
Flag 0. F0
This is a general-purpose flag for user programming.
Register bank select 0 and register bank select 1. RS0 and RS1
These bits define the active register bank (bank 0 is the default register bank).
Overflow flag. OV
Determines if the result of a signed arithmetic operation is out of range.
Even Parity flag. P
The parity flag is the accumulator parity flag, set to a value, 1 or 0, such that the number of 1
bits in the accumulator plus the parity bit add up to an even number.
Stack Pointer
The Stack Pointer, SP, is an 8-bit SFR register at address 81h.
The SP contains the 8 bits address of the data byte currently on the top of the stack.
At start-up the SP is initialized to 07h, so the stack will start at 08h and expand upwards in
Internal RAM.
The SP pointer can be initialized to a defined address by instruction MOV SP, #addr8

Typical instructions with the stack are: PUSH, POP, LCALL, RET, RETI etc.
With PUSH instruction a byte of data is written on to the stack to address SP + 1.

Data Pointer [DPTR]

The Data Pointer is a 16-bit register used to address the external code or external data memory.
The DPTR consists of two registers, where DPL (82h) holds the low byte of the DPTR and
DPH (83h) holds the high byte of the DPTR.
Example: Write the value 46h to external data memory location 2500h:
MOV A, #46h ; Move immediate 8 bit data 46h to A (accumulator)
MOV DPTR, #2504h ; Move immediate 16 bit address value 2504h to DPTR.
; Now DPL holds 04h and DPH holds25h.
MOVX @DPTR, A ; Move the value in A to external RAM location 2500h.
(MOVX instruction is used to access external memory).
Accumulator [ACC or A]
The accumulator is a 8 bit SFR register at address E0h which is bit-addressable. .
It is used to the hold result of various arithmetic and logic operations.
The accumulator can be accessed explicitly using instructions :
MOV A, #52h ; Move immediate the value 52h to the accumulator
MOV E0h, #52h ; the accumulator is accessed by its Internal RAM location E0h
B Register
The B register is an SFR register at addresses F0h which is bit-addressable.
The B register is used in only: i.e. MUL (multiply) and DIV (divide) instructions.
The B register can also be used as a general-purpose register.
Program Counter [PC]
The Program Counter is a 2 byte register which contains the memory address of the next
instruction to be executed. It does not has any address.
Upon reset of 8051 the PC is initialized to 0000h.
SFR Registers for the Internal Timer
TCON - the Timer Control register at address 88h, which is bit-addressable.
Used to configure and monitor the 8051 timers.
Also contains some interrupt control bits.
TMOD - the Timer Mode register at address 89h
Used to define the operational modes for the timers.
TL0 (Timer 0 Low) and TH0 (Timer 0 High) - addressed at 8Ah and 8Bh respectively.
They are associated with Timer 0.
TL1 (Timer 1 Low) and TH1 (Timer 1 High) - addressed at 8Ch and 8Dh respectively.

They are associated with Timer 1.

SFR Register for Power Control

PCON - The Power Control register at address 87h.
Contains various control bits including a control bit, which allows the 8051 to go to sleep so
as to save power when not in immediate use.
Serial Port Registers
SCON - Serial Control register at addresses 98h, and it is bit addressable.
Configures the behavior of the on-chip serial port,
Setting up parameters such as the baud rate of the serial port, activating send and/or receive
data,
Setting up some specific control flags.
SBUF - Serial Buffer register at address 99h.
A single byte buffer used for sending and receiving data via the on-chip serial port .
Interrupt Registers
IE - Interrupt Enable register at addresses A8h
Used to enable and disable specific interrupts.
(The MSB bit (bit 7) is used to disable all interrupts. )
IP - Interrupt Priority register at addresses B8h and it is bit addressable.
It specifies the relative priority (high or low priority) of each interrupt.
Addressing Modes
Type of addressing modes in 8051:
1. Immediate Addressing
2. Register Addressing
3. Direct Addressing
4. Indirect Addressing
5. Relative Addressing
6. Absolute addressing
7. Long Addressing
8. Indexed Addressing
Immediate Addressing
The operand is a constant and is obtained in the instruction:
(The operand immediately follows the opcode.)
Example:
MOV A, #99d ; copies the value 99 into the accumulator
The # symbol specifies the data as immediate value.
Accumulator
Number 99d

Register Addressing
Transfer of data from register to register.
The instruction operand can be one of the eight general-registers, R0 to R7 (Rn).
In register addressing the instructions are single byte.
Example
ADD A, R5 ; Adds register R5 to A (accumulator)
Here the contents of R5 is added to the accumulator.
Accumulator

R5

Direct Addressing
In direct addressing mode the operand is memory address and is contained in the instruction.
The data value is obtained directly from the memory location specified in the operand.
Direct addressing can be used to access Internal RAM , including the SFR registers.
Example
MOV A, 47h ; Copy into accumulator the data from Internal RAM address 47h
.
Internal RAM

Accumulator

48h
47h
46h

Indirect Addressing
Address of operand is contained in R0 or R1 registers The register acts as pointer to memory
location.
Indirect addressing refers to Internal RAM only and cannot be used to refer to SFR registers.
The 8052 has an additional 128 bytes of internal RAM. These 128 bytes of RAM can be
accessed only using indirect addressing.
Example
MOV A, @R0 ; copy data from internal RAM whose address is contained in R0 register

The @ symbol indicated that the indirect addressing mode is used.

Internal RAM

Accumulator

55h

R0

54h

54h

53h

R0 contains a value, for example 54h, which is to be used as the address of the internal RAM
location, which contains the operand data.
Relative Addressing
This is a special addressing mode used with certain jump instructions.
The relative address, often referred to as an offset, is an 8-bit signed number, which is added to
the PC to make the address of the next instruction.
The 8-bit signed offset value gives an address range of + 127 to 128 locations.
Advantage of relative addressing is that the program code is easy to relocate in
memory in that the addressing is relative to the position in memory.
Example:
SJMP LABEL_X

Absolute addressing
Absolute addressing within the 8051 is used only by the AJMP (Absolute Jump) and ACALL
(Absolute Call) instructions.
Long Addressing
The long addressing mode within the 8051 is used with the instructions LJMP and LCALL.
The address is a full 16 bit destination address so that a jump or a call can be made to a location
within a 64KByte code memory space (216= 64K).
Example
LJMP 5000h ; full 16 bit address is specified in operand
Indexed Addressing
With indexed addressing a separate register, either the program counter, PC, or the data pointer
DTPR, is used as a base address and the accumulator is used as an offset (index) address.
The effective address is formed by adding the value from the base address to the value from the
offset address.
Indexed addressing in the 8051 is used with the JMP or MOVC instructions.

Example
MOVC A, @A+DPTR
MOVC is a move instruction, which moves data from the external code memory space.
The address operand in this example is formed by adding the content of the DPTR register to the
accumulator value.
instruction
The instruction set consists of machine codes in order to instruct the MPU to perform various
data processing job, provided by manufacturer of the MPU.
mnemonics
The manufacturer of the MPU also provides the english like names (memory aid or mnemonics)
of the machine codes. Using these mnemonics assembly language programs are written.

Types of Instructions
1. Data transfer instructions,
2. Arithmetic instructions,
3. Logical instructions,
4. Program control instructions,
5. Some special instructions such as the rotate instructions.
Data Transfer
The 8051 uses five different types of instruction to move data:
MOV
MOVX
MOVC
PUSH and POP
XCH
MOV
The MOV instruction is concerned with moving data between Internal RAM, SFR registers,
general registers etc.
MOVX and MOVC are used in accessing external memory data.
Format of MOV instruction :
MOV destination, source
The instruction copies data from a defined source location to a destination location.
Examples
MOV R2, #80h ; Move immediate data value 80h to register R2
MOV R4, A ; Copy data from accumulator to register R4
MOV DPTR, #0F22Ch ; Move immediate value F22Ch to the DPTR register
MOV R2, 80h ; Copy data from 80h (Port 0 SFR) to R2

MOV 52h, #52h ; Copy immediate data value 52h to RAM location 52h
MOV 52h, 53h ; Copy data from RAM location 53h to RAM 52h
MOV A, @R0 ; Copy contents of location addressed in R0 to A (indirect addressing)
MOVX
The MOVX instruction is used to access the external memory.
All external moves must work through the A register (accumulator).
MOVX instructions operate on RAM.
With 8051 the external memory can be addressed using indirect addressing only.
The DPTR register is used to hold the address of the external data (since DPTR is a 16-bit
register it can address 64KByte locations: 216= 64K).
The 8 bit registers R0 or R1 can also be used for indirect addressing of external memory but the
address range is limited to the lower 256 bytes of memory (28= 256 bytes).
Examples
MOVX @DPTR, A ; Copy data from A to the address specified in DPTR
MOVX A, @DPTR ; Copy data from address specified in DPTR to A
MOVC
The MOVC instruction is used to read data from the external code memory (ROM).

The DPTR register is used as the indirect address register.

The external code memory can be addressed using indirect addressing and indexed
addressing mode where register A is used to provide an offset in the address specification.
All external moves must work through the A register (accumulator).
For the MOVC the program counter, PC, can also be used to form the address.

Examples
MOV DPTR, # 2000h ; Copy the data value 2000h to the DPTR register
MOV A, #80h ; Copy the datavalue 80h to register A
MOVC A, @A+DPTR ; Copy the contents of the address 2080h (2000h + 80h) to register A
PUSH and POP
PUSH and POP instructions are used with the stack only.
The SP (stack pointer) register contains the current stack address.
Direct addressing is used .
Examples
PUSH 4Ch ; Contents of RAM location 4Ch is saved to the stack. SP is incremented.
PUSH 00h ; The content of R0 (which is at 00h in RAM) is saved to the stack and SP is
incremented.
POP 80h ; The data from current SP address is copied to 80h and SP is decremented.

XCH
The XCH instruction swaps the data between source and destination.
Immediate addressing may not be used with XCH.
XCH instructions must use register A.
XCHD is a special case of the exchange instruction where just the lower nibbles are
exchanged.
Examples
XCH A, R3 ; Exchange bytes between A and R3
XCH A, @R0 ; Exchange bytes between A and RAM location whose address is in R0
XCH A, A0h ; Exchange bytes between A and RAM location A0h (SFR port 2)

Arithmetic
Type of arithmetic instructions
1. Addition
2. Subtraction
3. Increment/decrement
4. Multiply/divide
5. Decimal adjust
Register A (the accumulator) is used to hold the result of any addition operation.
Addition
ADD
Simple addition is done within the 8051 based on 8 bit numbers
Examples
ADD A, #25h ; Adds the number 25h to A, sum is stored in A
ADD A, R3 ; Adds the register R3 value to A, sum is stored in A
ADDC
The instruction is used to include the carry bit in the addition process.
Examples
ADDC A, #55h ; Add contents of A, the number 55h, the carry bit; sum is stored in A
ADDC A, R4 ; Add the contents of A, the register R4, the carry bit; sum is stored in A
Subtraction
SUBB
The accumulator, register A, will contain the result (difference) of the subtraction operation.

The C (carry) flag is treated as a borrow flag, which is always subtracted from the minuend
during a subtraction operation.
Examples
SUBB A, #55d ; Subtract the number 55 (decimal) and the C flag from A; store the result in A.
SUBB A, R6 ; Subtract R6 and the C flag from A; and store the result in A.
SUBB A, 58h ; Subtract the number in RAM location 58h and the C flag from A; store the result
in A.
Increment/Decrement
INC
The increment instruction adds 1 to a number
DEC
The decrement instruction subtracts 1 from a number.
The increment and decrement instructions uses the direct, indirect and register addressing
Modes.
The DPTR register cannot be decremented using a DEC instruction .
Examples
INC R7 ; Increment register R7
INC A ; Increment A
INC @R1 ; Increment the number which isthe content of the address in R1
DEC A ; Decrement register A
DEC 43h ; Decrement the number in RAM address 43h
INC DPTR ; Increment the DPTR register
Multiply / Divide
For the MUL or DIV instructions the A and B registers must be used and only unsigned numbers
are supported.
Multiplication
MUL
The instruction is used with operands in the A and B registers.
The resulting product resides in registers A and B, the low-order byte of the product is stored in
A and the high order byte of the product is stored in B.
Example
MUL AB ; Multiply A by B.
Division
DIV
The instruction is used with operands in the A and B registers.
The remainder is put in register B and the integer part of the quotient is put in register A.

Example
DIV AB ; A is divided by B.
Logical (Boolean) operations
The 8051 provides Boolean instruction which can operate on byte and bit level data.
Byte level or bit level data logical operations
ANL Logical AND
ORL Logical OR
CPL Complement (logical NOT)
XRL Logical XOR (exclusive OR)
Byte level only data logical operations
The destination address of the operation can be the accumulator (register A), a general register,
or a direct address.

Examples
ANL A, #55h ; AND each bit in A with corresponding bit in number 55h, result in A.
ANL 42h, R4 ; AND each bit in RAM location 42h with corresponding bit in R4, result in RAM
location 42h.
ORL A,@R1 ; OR each bit in A with corresponding bit in the number whose address is
contained in R1, result in A.
XRL R4, 80h ; XOR each bit in R4 with corresponding bit in RAM location 80h (port 0), result
in A.
CPL R0 ; Complement each bit in R0
Logical operations at the BIT level
The C (carry) flag is the destination of most bit level logical operations.
The carry flag can be tested using a branch (jump) instruction following a bit level logical
operation.
Addressable SFR registers in bit level operations:
1. PSW
2. IE
3. IP
4. TCON
5. SCON
Examples
SETB 2Fh ; Bit 7 of Internal RAM location 25h is set
CLR C ; Clear the carry flag (flag =0)
CPL 20h ; Complement bit 0 of Internal RAM location 24h
MOV C, 87h ; Move to carry flag the bit 7of Port 0 (SFR at 80h)
ANL C,90h ; AND C with the bit 0 of Port 1 (SFR at 90)

ORL C, 91h ; OR C with the bit 1 of Port 1 (SFR at 90)

Rotate Instructions
Shift the content of accumulator one bit ,useful to allow examination of individual bits.
Examples
RL A ; Rotate A one bit to the left. Bit 7 rotates to the bit 0 position
Accumulatorb7b6b5b4b3b2b1b0

RLC A ; The Carry flag is used as a 9th bit in the rotation loop.
Carry flagAccumulatorCb7b6b5b4b3b2b1b0

RR A ; Rotates A one bit to the right. Bit 0 rotates to the bit 7 position
Accumulatorb7b6b5b4b3b2b1b0

RRC A ; Rotates to the right and includes the carry bit as the 9th bit.
AccumulatorCarry flagb7b6b5b4b3b2b1b0C

SWAP A; This instruction interchanges the accumulators high order nibble with the low-order
nibble .
Accumulatorb7b6b5b4b3b2b1b0High
nibbleLow nibble

Program Control Instructions

These instructions alter the sequence of program execution conditionally or unconditionally,
consist of Jump, call, restart, return, instructions.
The instructions can be:
1. Unconditional- instructions that alters the program sequence unconditionally
2. Conditional- instructions test for certain condition (zero, carry flag) and alter the program
sequence where the condition is met

Unconditional jump instructions

Types of jump instructions:
1. LJMP
2. SJMP
3. AJMP
LJMP (long jump)
It causes the program to branch to a destination address defined by the 16-bit operand in the
jump instruction to any location within the 64KByte program space (216=64K) .
Examples
LJMP LABEL_X ; Jump to the specified label
LJMP 0F200h ; Jump to address 0F200h
LJMP @A+DPTR ; Jump to address which is the sum of DPTR and Reg. A

SJMP (short jump)

The branch address is a signed 8-bit number which allows the program to branch to a distance
-128 bytes back or +127 bytes forward from the current PC address.
The relative addressing mode is used in this form of branching.
AJMP
This jump instruction allows a jump with a 2KByte address boundary (a 2K page)
JMP
Branch instruction supported by some 8051 assemblers. The assembler will choose the most
efficient instruction to use - LJMP/ SJMP /AJMP .
Subroutines and program flow control
A subroutine is called using the LCALL or the ACALL instruction.
LCALL
This instruction is used to call a subroutine at a specified address which is 16 bits long so the call
can be made to any location within the 64KByte memory space.
RET
Instruction to return from subroutine.
When a LCALL instruction is executed the current PC content is automatically pushed onto the
stack of the PC.
When the program returns from the subroutine the PC contents is returned from the stack so that
the program can resume operation from the point where the LCALL was made

ACALL
This instruction is used to call a subroutine with a 2KByte address boundary (a 2K page)
CALL
Call instruction supported by some 8051 assemblers. The assembler will choose the most
efficient type of call instruction, LCALL or ACALL.
Program control using conditional jumps
Format of conditional jump:
Jmp_condition branch_address;
Relative addressing is used for branch address, i.e. addressing within the range 128 to +127
bytes.
When using a conditional jump instruction the programmer can simply specify a program label
or a full 16-bit address for the conditional jump instructions destination. The assembler will
position the code and work out the correct 8-bit relative address for the instruction.
Examples
JZ LABEL_1 ; Jump to LABEL_1 if accumulator is equal to zero
JNZ LABEL_X ; Jump to LABEL_X if accumulator is not equal to zero
JNC LABEL_Y ; Jump to LABEL_Y if the carry flag is not set
DJNZ R2, LABEL ; Decrement R2 and jump to LABEL if the resulting value of R2 is not zero.
CJNE R1, #55h , LABEL_2 ; Compare the magnitude of R1 and the number 55h and jump to
LABEL_2 if the magnitudes are not equal.