Mindanao State University-Iligan Institute of Technology

College of Engineering
Department of Electrical and Electronics
Communications Engineering

Logic Gates: INVERTER

IN PARTIAL FULFILLMENT
OF THE COURSE REQUIREMENTS IN
EE 177.1

Submitted by:
Ceferino Kevin A. Tan

Submitted to:
Mr. Jefrey Pasco

December 04, 2014

Activity 1.
Logic Gates: INVERTER

I.

OBJECTIVES:
To study the basic logic gate: inverter, its representation by truth table, logic
diagram and Boolean algebra.
To familiarize with the Quartus II computer-aided design tool in the inverter
simulation.
To observe the pulse response of the inverter.

II.

BASIC CONCEPT
A NOT gate, often called an inverter, is used in digital circuits to produce the
desired logical function. The standard NOT gate is given a symbol whose shape is of
a triangle pointing to the right with a circle at its end. This circle is known as an
inversion bubble and is used in NOT, NAND and NOR symbols at their output to
represent the logical operation of the NOT function. This bubble denotes a signal
inversion (complementation) of the signal and can be present on either or both the
output and/or the input terminals. A NOT gate performs logical negation on its
output.

Figure 1. The NOT gate (inverter) Symbol

Input

Output

false

true

true

false

Figure 2. Truth table for a NOT gate

INPUT

OUTPUT

NOT A

Figure 3. Boolean algebra

III.

MATERIALS:
Computer
Quartus II Web Edition (www.altera.com)

IV.

PROCEDURE:
1. Download and install Quartus II; a design software for a programmable logic
devices.Run the program and use the Quartus II to create the project.
2. Click FileNew Project wizard Next, A 5-page preliminary project setting will
appear. See figure 4.a for Project name and directory

Figure 4. Project name and directory

3. Nextpage 2 of 5(add files)next, page 3 of 5 (family and device settings)
next page 4 of 5, (EDA tool settings)next, page 5 of 5 (Summary)Finish
4. Click File Newblock diagram/ schematic fileok
5. Click the Symbol tool ( ) and choose the NOT gate
6. Click the Pin tool(
below)

) for the input and output (follow the logic diagram

Figure 5. Logic Diagram

7. Click Compile , a window for the Flow summary will appear as the project
compiles. After compilation, open the Modelsim to start simulating the project
created in the Quartus II.
8. Click File NewProject, fill in the necessary requirements to proceed Add
Existing FileBrowse , open the folder where the project was saved
simulationmodelsim VHO file (usually the first file in the list) OK
9. Click the selected projectcompilecompile selected, a check mark in the
status column will appear as the compilation finishes simulate start
simulation Work the project to be simulatedOK
10. Send the input and output to the wave output window to run test the designed diagram
by selecting the input and output then right clickadd towave selected signals

Figure 6. Importing input and output to wave output window

11. Right click Input clock and choose:
o Rising ( if you want your input be 1)
o Falling ( if you want your input be 0)
12. Press F9 to run
13. Observe wave output

V.

OUTPUT

Figure 7. Wave Output

VI.

CONCLUSION:
As observed in the output, a NOT gate or inverter performs logical
negation on the input. It is a single input device which has an output level that is
normally at logic level 1 and goes LOW to a logic level 0 when its single
input is at logic level 1, in other words it inverts (complements) its input
signal. The output from a NOT gate only returns HIGH again when its input is at
logic level 0. In other words, If the input is true, then the output will be false
(the falling part of the square wave), similarly, a false input results in a true
output (the rising part of the square wave).

References:

1.

Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice
Hall, 2004. p. 73.

2.

Joshua Tynjala (2008). NOT gate (Inverter). http://logic.ly/lessons/not-gate

3.

Wayne Storr (1999). Basic Electronics tutorials. http://www.electronics-tutorials.ws/logic/logic_4.html