VLSI DESIGN MINI PROJECT

SERIAL ADDER
DASIKA PUSHKAR, U11EC132
CONTENTS
1. Problem Statement
2. Design
3. Program
4. Results

1. Problem Statement
Design a serial Adder/subtarcter with accumulator for 8-bit binary numbers and implement it
using VHDL. Use 2s Complement to represent negative numbers. Draw state diagram of
control unit and implement it using VHDL. Report numbers of LUTs and CLBs used and
maximum frequency of operation after synthesis it for SPARTAN-3E device.
Submission Constraints:

Draw RTL for data-path and state diagram for control path

Use behavioral model to describe control unit and structural model for data-path design

Submit fully commented VHDL code.

Submit simulation and post synthesis obtained for at least four cased
i. Both positive numbers
ii. Both negative numbers
iii. One positive and other negative number (Larger than positive no.)
iv. One positive and other negative number (Smaller than positive no.)

Project must be design for the Spartan 3E, family XC3S100E kit with speed -5.

Report numbers of LUTs and CLBs used and maximum frequency of operation after
synthesis.

CODE must be synthesizable.

2. Design
The design that has been implemented is described here.

Two shift registers with parallel input capability have been chosen, which take parallel
input when the 'rst' is made high, otherwise, they shift the input serially for each clock.

The accumulator has been implemented as a shift register with parallel output capability.
Whenever 'stop' is made high, the contents of the shift register are latched on the output.

Whenever the control unit receives the 'start' signal or after the completion of one
addition, it clears the flip flop, and accepts the inputs. On completion of addition, it
provides appropriate signals to latch the output.

The carry of present addition has been stored in a D flip-flop for its use as carry in of
next addition.

CLK
START

CONTROL

IN1

STOP

SUM

FULL ADDER

R
S
T

OUT1

R
S
T

B
Cout
Cin

IN2
Q

D
CLK

RST
SYSTEM BLOCK DIAGRAM

S0

S1

1/0

0/0

S2

S8

0/0

0/1
START='1'

RST/STOP
S3

S7

0/0

0/0
S6

S5

S4

0/0

0/0

0/0

CONTROL BLOCK

3. PROGRAM
--MAIN PROGRAM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity serial_adder is
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
in2 : in STD_LOGIC_VECTOR (7 downto 0);
out1 : out STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
start : in STD_LOGIC);
end serial_adder;
architecture Behavioral of serial_adder is
signal s0,s1,s2,s3,s4,s5,s6:STD_LOGIC;
component shift
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
rst: in std_logic;
out1 : out STD_LOGIC);
end component;
component control_fsm
Port ( clk : in STD_LOGIC;
start : in STD_LOGIC;
rst : out STD_LOGIC;
stop : out STD_LOGIC);
end component;
component d_ff
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q : out STD_LOGIC);
end component;
component full_adder
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
component accumulator
Port ( in1 : in STD_LOGIC;

clk : in STD_LOGIC;
stop:in STD_LOGIC;
out1 : out STD_LOGIC_VECTOR (7 downto 0));
end component;
begin
U1: control_fsm port map(clk,start,s0,s1);
U2: shift port map(in1,clk,s0,s2);
U3: shift port map(in2,clk,s0,s3);
U4: full_adder port map(s2,s3,s4,s5,s6);
U5: d_ff port map(s6,clk,s0,s4);
U6:accumulator port map(s5,clk,s1,out1);
end Behavioral;
--CONTROL FSM CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity control_fsm is
Port ( clk : in STD_LOGIC;
start : in STD_LOGIC;
rst : out STD_LOGIC;
stop : out STD_LOGIC);
end control_fsm;
architecture Behavioral of control_fsm is
type fsm_state is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal current_state: fsm_state;
begin
process(clk,start)
begin
if(start='1') then
current_state<=s0;
elsif (clk'event and clk='1') then
case current_state is
when s0 =>
rst<='1';
stop<='0';
current_state<=s1;
when s1 =>
rst<='0';
stop<='0';
current_state<=s2;
when s2 =>
rst<='0';
stop<='0';
current_state<=s3;
when s3 =>
rst<='0';

stop<='0';
current_state<=s4;
when s4 =>
rst<='0';
stop<='0';
current_state<=s5;
when s5 =>
rst<='0';
stop<='0';
current_state<=s6;
when s6 =>
rst<='0';
stop<='0';
current_state<=s7;
when s7 =>
rst<='0';
stop<='0';
current_state<=s8;
when s8 =>
rst<='0';
stop<='1';
current_state<=s0;
end case;
end if;
end process;
end Behavioral;

--FULL ADDER CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is
Port ( in1 : in STD_LOGIC;
in2 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
begin
sum<=in1 xor in2 xor cin;
cout<=(in1 and in2) or (in1 and cin) or (in2 and cin);
end Behavioral;

--D FLIP FLOP CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity d_ff is
Port ( d :
clk
rst
q :
end d_ff;

in STD_LOGIC;
: in STD_LOGIC;
: in STD_LOGIC;
out STD_LOGIC);

architecture Behavioral of d_ff is

begin
process(rst,clk)
begin
if(rst='1') then
q<='0';
elsif(clk'event and clk='1') then
q<=d;
end if;
end process;

end Behavioral;

--SHIFT REGISTER CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift is
Port ( in1 : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
rst: in std_logic;
out1 : out STD_LOGIC);
end shift;
architecture Behavioral of shift is
begin
process(rst,clk)
variable shifter: STD_LOGIC_VECTOR (7 downto 0):="00000000";
begin
if(rst='1') then
shifter:=in1;
elsif(clk='1' and clk'event) then
out1<=shifter(0);
shifter:=shifter(0) & shifter(7 downto 1);
end if;
end process;
end Behavioral;

--ACCUMULATOR CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity accumulator is
Port ( in1 : in STD_LOGIC;
clk : in STD_LOGIC;
stop:in STD_LOGIC;
out1 : out STD_LOGIC_VECTOR (7 downto 0));
end accumulator;
architecture Behavioral of accumulator is
begin
process(clk,stop)
variable acc:STD_LOGIC_VECTOR (7 downto 0):="00000000";
begin
if(clk'event and clk='1') then
if (stop='1') then
out1<=acc;
end if;
acc:=in1 & acc(7 downto 1);
end if;
end process;

4. RESULTS
Various test cases have been provided for verification.
1. 44 (2Ch) +45(2Dh) = 89(59h)
2.-19(EDh) + -7(F9h) = -26(E6h)
3. -75(B5h) + 59(3Bh)= -16(F0h)
4. -39(D9h) + 92(5Ch)= 53 (35h)

SYNTHESIS REPORT
Slices

24

Slice Flip Flops

42

4 input LUTs

41

Maximum Frequency

426.26 MHz

Device

Sparta 3E