FreeHDL Compiler Control Data Flow

Graph and its application in waveform

compression

Dr.-Ing. Edwin Naroska

Said Mchaalia
7th August 2002

1 Intention of this document

In this document, we try to present an idea of using Control Data
Flow Graph (CDFG) to improve waveform compression.
A waveform file is a VCD (Value Change Dump) file, which is divided
in two parts: header that contains general information, which are
version, date,.. and kernel, which contains signal values belong to
each simulation step and simulation time.
Figure 1 describes a VCD file. Notice that each parameter is coded
with an ASCII code composed of 1 to 4 characters depending on
the number of parameters inside considered VHDL model. For each
VHDL model, the simulation time is written before the parameter values. For example: #0 and #100 represent the simulation times 10
and 100 us. The character b preceded parameter value describes
that this parameter value is a binary format. Thereby all parameter
values will be transformed to a binary format before that they will be
written in the VCD file.
To compress a VCD file, many techniques are developed. The basic
idea of these techniques is inspired from the Lempel-Ziv and the others algorithms for data compression [4]. Mainly, five algorithms that
are Time-Value Separation, Time Compression Technique, Value
Compression Technique, Strength Reduction and Cross Signal Strength
Reduction (see [1] and [2]) are developed to allow a suitable VCD file
compression.
The object of this work is to get out an idea of using CDFG for developing a new waveform compression algorithm. In following sections,
we will describe this idea and present its features.

$date
Sep 26 2000 16:28:52
$end
$version
FREEHDL 0.1
$end
$times ale
1 us
$end
$s ope module stru t $end
$var reg 8 ! qsig2[8:1 $end
$var reg 8 " qsig[8:1 $end
$var trireg 1 ? lk $end
$ups ope $end
$enddefinitions $end
#0
$dumpvars
b110100 !
b110100 "
b0 ?
#100
b110100 !
b1 ?
$end
Figure 1: VCD File

2 An overview of waveform compression technique

The basic idea of waveform compression is finding a method that
reduces waveform file sizes in order to get more storage space for
further use.
The actual waveform compression techniques are described in [1]
and [2].

3 Control Data Flow description

The Control Data Flow Graph is a graphical representation, which
identifies each statement in a given program with a graph. A CDFG is
composed of edges, which represent data and/or control and nodes
that identify arithmetic and/or logic operations[3]. Figure 3 represents a CFDG of VHDL model.

4 CDFG and its application in waveform compression

The object of using CDFG is to develop a compression algorithm
based on interpreted graphical information. In this section we detail
the different waveform compression cases in which the CDFG will be
used.

4.1 Dependency Schedules

In this section, we will deal with the dependency between signals
and/or variables and dependency between processes. This section
is divided in two main subsection: however the first section treats
the case of the dependencies between signals and/or variables, the
second one interests the dependency between processes.
4.1.1 Signal dependency schedules
We know that CDFG gives a knowledge a priori of relationships between signals and variables inside a given VHDL model. Due to this
information, we can minimize the data storage. For example let consider the VHDL model described in figure 2. We see, that the signal
c is depended on whether the signals a and/or b change values or
not. So, we can use such an information to reduce the stored information belong to considered waveform. Thereby, we do not need to
store the c signal value and we should just store the a and b signal
values. In the other hand, notice that the signal d is depended on
3

pro ess(a,b)
begin
<= a xor b;
d <= and a;
end pro ess;
Figure 2: VHDL model 1

Figure 3: CDFG of VHDL model 1

whether the signal a an/or the signal c change values or not. Due
to this relationship between signals and the principles of the VHDL
language, we do not need to store the d signal value.
So, a dependency knowledge a priori checks whether to store a signal value or not.
Indeed, in figure 2 we can predicate the output signal value throughout the knowledge of the operand signal values. The CDFG of the
VHDL model described in figure 2 is presented in figure 3. We see
that the CDFG shows the dependencies between all considered signals in this process.
So, we do not need to store the d and c signal values due to the dependencies between those signals and the signals a and b. The idea
is to search a manner in which we must store information describing the dependencies between those signals. This can be solved by
storing these operations:

= a XOR b

(1)

= AND a

(2)

and

pro ess
begin
if lk'event and lk = '1' then
<= a xor b;
d <= and a;
end if;
end pro ess;
Figure 4: VHDL model 1
that attach each set of signals to the other. The first operation (equation (1)) describes the relationship between the signals a, b and c
and the second one (equation (2)) describes the relationship between the signals a, c and d. Notice that the storage of these equations should be done just once a time for each waveform compression process.
Let see, what will happen when we consider a VHDL model, which
depends on clock signal. Figure 4 shows the previous example in
the case where the process P depends on a clock signal clk.
We see that in the VHDL model of figure 4, the considered process
depends whether the clock signal clk changes value or not to assign
signal values to c and d. Although, signals c and d will change value
with a cycle delay of clock signal compared to signals a and b. Figure 5 describes the signal assignment structures for VHDL language
in the case of ideal electrical circuits without any component delays.
We notice that there is a clock cycle delay between the two assignments and the a and b signal values. I.e. that the signal assignment
will be achieved just after a delay of clock signal cycle.
In order to make synthesizable models and due to the VHDL language structure in the signal assignment, we notice that the previous
relationship between c, a and b, and d, c and a will not be valid in
the case of this VHDL model that depends on clock signal. Therefore, we must define new relationships between these signals, which
depend on the clock signal clk.
Figure 6 represents the CDFG of the VHDL model shown in figure 4.
Notice that this graphical representation describes the relationships
between all signals in this VHDL model. Thereby, the incoming data
edges a and b of the XOR node come from the Read Signal node,
which represents the source of out-coming data edges, however the
out-coming data edge c is an incoming edge of the Write Signal
node, which represents the source of incoming data edges. Between
Read Signal node and Write Signal node there is just one clock
signal cycle delay. After a clock signal cycle, the value of signal c
will be transfered to Read Signal node. On the other hand, the
5

Figure 5: VHDL signal assignment procedure

incoming data edges a and c of the AND node are coming from
Read Signal node. This means that there is a clock signal cycle
delay between these signals and the out-coming data edge d of this
node. Notice that the dependency of these nodes on the clock signal
is characterized with control edges true and false coming from the
Select node that is activated by the clock event node.
Let us consider the new relation as follows:

(n)

= f (a n ; b n )
(

1)

1)

(3)

where f (x; y ) a logical function, which is defined as follows:

f (x; y) = x XOR y

(4)

as the first relation between signals c, a and b.

d(n)

= f ( n ; a n )
(

1)

1)

(5)

where f (x; y ) a logical function, which is defined as follows:

f (x; y)

= x AND y

(6)

as the second relation between signal d, a and c.

Where n is the nth clock signal (clk) cycle.
4.1.2 Process dependency schedules
In this section, we will try to give an idea how the CDFG can solve
the dependencies between processes inside the same VHDL model
6

Figure 6: CDFG of VHDL Model 2

and how which information will be used in the waveform compression
techniques.
Let us look at the example of figure 7, we see that the three processes P1 , P2 , and P3 are depended each of the other. Based on
the CDFG of each process and on the knowledge that all processes
inside the same VHDL model have the same Read Signal and
Write Signal nodes, we can involve some relationships between
signals inside different processes to make a suitable optimization of
the waveform compression.
Figure 8 describes the CDFG of the VHDL model represented in
figure 7. We see that, the CDFGs allow us to get information about
the dependencies between signals inside theses processes and so
to achieve the needed optimization, which is the storage of signal a
and all relationships between considered signals such as:

= f (a; 1)

(7)

where f (x; y ) a logical function, which is defined as follows:

f (x; y) = x XOR y

= f (b; 1)

(8)
(9)

P1: pro ess(a)

begin
b <= a xor '1';
end pro ess;
P2: pro ess(b)
begin
<= b nor '1';
end pro ess;
P3: pro ess( )
begin

d <= xor '1';

end pro ess;
Figure 7: VHDL model 3

where f (x; y ) a logical function, which is defined as follows:

f (x; y) = x NOR y
d

(10)

= f ( ; 1)

(11)

Where f (x; y ) a logical function, which is defined as follows:

f (x; y) = x XOR

(12)

Above, we presented the case when the processes depend on signals. Let us look, what will happen when there are processes, which
depend on clock signal inside a considered model.

The simple case of processes that depend on clock signal is

the case when all processes have the same clock signal and
are activated on the same clock signal cycle. This case represents a composition of the process dependencies and dependency on clock signal. So, the relationship will described as
followed:

S (n+1)
Where
tion.

= f (Si n ; Sj n ))
( )

( )

(13)

f (:; :; :) represents a mathematical multi-variable func8

Figure 8: CDFG of VHDL Model 3

The more complex case is the case where each process has
its own clock signal. In this case, we must define a relationship between all clock signals, and try to write the other clock
signals function of the first one for example. If we suppose
for example that the clock signal lkk is slower k times than
the clock signal lk0 , and the clock signal lkp is p times faster
than signal clock lk0 , we can write the following relationships
between the distinguished clock signals:

= k  lk

lkk
lkp

(14)

= 1=p  lk

(15)

The relationships between signals inside theses processes will

be defined as follows:

Sl 0 (n)

= f (Si
0

(n

1)

; Sj k (E ((n

1)=k ))

; Shp (p(n

1))

(16)

Where E (x) is a function, which is defined as follows:

E (x)

: IR > IN : x j > n su h as : n 1 < x <= n (17)

where IR is the real sets and IN is the natural number sets.

Slk (n)
Slp (n)

= fk (Si

= fp(Si

(k (n

(E ((n

1))

1)=p))

; Sj k (n

1)

; Sj k (E ((n

; Shp(kp(n
1)=(pk )))

1))

; Shp (n

(18)
1)

(19)
9

P1: pro ess

begin
if lk0'rising_edge then
b <= a xor '1';
end if;
end pro ess;
P2 : pro ess
begin
if lk1'rising_edge then
<= b nor '1';
end if;
end pro ess;
P3 : pro ess
begin
if lk2'rising_edge then
d <= xor '1';
end if;
end pro ess;
Figure 9: VHDL model 4
Figure 9 represents a VHDL model, where considered processes
inside this model are depended on different clock signals.
The CDFG of the VHDL model described in figure 9 is shown in figure 10. Notice that in the VHDL model of figure 9, the three clock
signals lk0 , lk1 and lk2 are distinct. So, to get a relationship between signals a, b, c and d, we must define relations between the
clock signals.
Suppose for example that:

lk1

= 3  lk

(20)

and

lk2

= 0:5  lk

(21)

To involve the relations between signals that are defined previously,

we can consider these equations:
10

Figure 10: CDFG of VHDL Model 4

b(n+1)

= a n XOR 1
( )

(22)

Where n is the nth clock signal lk0 cycle.

(k+1)

= b k NOR 1
( )

(23)

Where k is the kth clock signal lk1 cycle.

d(m+1)

= m XOR 1
(

(24)

Where m is the mth clock signal lk2 cycle.

Indeed, we can use these equations to minimize data storage. Thereby,
we can just store the signal value a and these relations between different clock signals lk0 , lk1 and lk2 , and signals a, b, c and d.
Notice that these relations will be stored just only once a time duration the VHDL model simulation.

4.2 CDFG and Waveform Decompression

In this section, we will describe how the CDFG will be used in the
complex cases to improve the waveform compression techniques.
4.2.1 Compromise between decompression and signal dependencies
In the previous section, we treated the case of signal dependencies
and the involved solution based on the CDFG research. In section
11

4.1.1, we developed an algorithm that searches whether a signal will

be stored or not. Indeed, the storage of signal values needs a knowledge a priori of the signal dependencies. Thereby, a signal value will
be stored only when this signal is independent from all other signals defined inside a given VHDL model. On the other hand, section
4.1.1 involves that only the relationship in their mathematical forms
between signals will be stored, because this will be done just once
a time during a simulation process of waveform compression. Although, it is hard to achieve this task during the decompression process. Thereby, we do not know exactly the complexity of considered
mathematical functions, which link the signals to each other. In the
most case of complex VHDL models, we have mostly very complex
mathematical functions that belong a set of signals to a defined signal. This will make the process of decompression very complex and
it will take a great schedule time.
To solve this problem, we try to find an optimized solution for the
waveform compression techniques based on the signal dependencies.
This solution is described as follows:

in the case of a signal that depends of a set of signals: find an

algorithm that searches to store all needed signals based on
operation numbers that identify the signal values. Thereby, let
consider the signal Sk that depends on a set of signals. This
signal will be written as follows:

Sk

= fk (Sp0 ; :::; Spi ; Sj ; :::; Sn)

(25)

where Sp0 ; :::; Spi are independent or primery signals and Sj ; ::; Sn
are signals that depend of each other and the other signals.
For example, let consider the following signal dependencies:

Sj

= fj (S ; ::; Sl )

(26)

Sm

= fm(S ; S )

(27)

= fl (S )

(28)

= fn(S ; Sh; Sm )

(29)

Sl
Sn

In section 4.1.1, we will just store the signals that do not depend of any other signal. For example Sp0 ; :::; Spi . Therefore, the decompression process complexity will depend on the
complexity of the functions f0 (); :::; fn (). Notice that these functions can be as complex as possible and so the decompression
task will be so complex. To solve this problem, we can precede
as follows:
12

Figure 11: Complexity of dependency functions function of signal

numbers
first, store all independent signals.
secondly, in the case of dependent signals: see whether
the dependency function fi () : i = 1:::n and i <> k
is complex or not. If it is simple then do not store the
corresponding dependent signal Si . Figure 11 represents
the graph of the complexity of dependency functions.
In figure 11, we see that the complexity Cij of dependency
function fi () depends on the number of signals j that are contained in this function. If this number is higher than the complexity is lower and vice versa. This means that, in this case
of dependent signals, we must search the signal number to be
stored in order to reduce the complexity of the decompression
process. In the figure 11, we see that for a given dependency
functions that depend on m signal, we can find the suitable
signal number k such as k < m with which we can get an
optimized complexity of all considered dependency functions.
So, our object is to develop an algorithm that returns the signal
number k , which their values will be stored to allow a simple
restoration of the other signals and to identify the signals that

13

must be stored.

Thirdly, optimize the compromise between the storage space of

signal values and the complexity of schedule time needed for
the decompression process. As, we describe above, we must
find the signal number k that allows a suitable complexity of all
considered dependency functions inside a given VHDL model.
Although the research of this number is so complex and in the
most time we cannot find just a number but an interval. In this
case we must resolve the solution of finding this signal number
k based on other information, which is the reduction of needed
storage space of signal values. Throughout these information,
we must find a signal number k inside the considered interval
and which gives a less need of storage space of signal values.
Finally, store all needed signal and required dependency functions.

Problem formulation: The problem we are going to consider may

be formulated as follows:

For a given signal Sk , which is written in the form:

Sk = Fk (S0 ; :::; Si )i = 0


n
minimize the dependency function complexity:
be written in the following form:

Ck =

X
i

Cki =

X
i;j

(30)

Cki , which should

i wi Cij

(31)

where k; i = 0:::n, n is the number maximal of signals, f (:; :) a

function to define, and:

 j is defined as follows:
(
Sj value not stored in DDB
j = 10 :: otherwise

(32)

 wi is the weight of operation i contained inside the dependency

function fi (). It is defined as follows:
8
>
0 : S independent
>
< 1 : fii() = NOT
wi = > 2 : f () = XOR
i
>
:

(33)

: so on

14

Let consider the signal sets S = fS0 ;


; Sn g as information model,

which will be identified. It looks like that our VHDL model is a source
of signals, which will be produced each simulation time ti with distinguished probabilities pi . These signals are dependent one of each
other and they are correlated between them. Where each signal Si
represents an information to be stored or not. Thereby, our problem
will be considered as a Lossless Data Compression Problem that
searches to encode each signal Si with a number of bits and then
optimizes the number of the signal values, which must be stored for
further use and that allows a suitable restoration of the all signals
during the decompression process.
On the other hand, for a given signal sets S = fS0 ;


; Sn g, we consider the probability of a signal Si ; i = 0


n, pi to be appear in the
VCD file during a simulation process and the probability pi=j k i <>
j &i; j = 0


n as the probability of the dependency between signals
Si and Sj . The probability pi of signal Si . is defined as follows:

i
SSi
pi = P
n
j
SSj

(34)

j =0

where i is the occurrence frequency of the signal Si and SSi is

the storage space needed for storing the signal Si . It means, when
a signal Si appears just once a time during simulation process, i
will have the value one and so on. Although, the probability pi=j
of dependency between the signals Si and Sj (or the conditional
probability) is defined as follows:

pi=j =

j
SSj
i
SSi

j
= j SS
n
P
pi
l

(35)

l=0

where j is the number of times in which the Sj belongs to signal Si .

I.e. the number of times that the signal Sj is defined as a parameter
of function fi ().
The problem we are dealing with can be defined as an optimization
problem. So, mathematically, this problem will be written as follows:

8
>
( 1 PC )
< min
m m i;j ki
Pp )
OP : >
1
(
i
: min
m
m
i

(36)

From this optimization problem, we can say that the needed storage
space and the dependency function complexity are inversely (conversely) proportional. So, we can define a new space composed of
15

the complexity and the probability as shown in figure 12. This allows
us to consider the function to minimize as follows:

1 Xd )
min
(
im
k k
2

(37)

where dim is the distance between the points

Xi (pi ; Cki ):

dim = d(Xi ; Xm ) =

Xmin (pm ; Ckm )

and

( pi Apm ) + ( Cki BCkm )

2

(38)

where A and B are constants for scaling, and the distance dm is

defined as follows:

dm = min
(di ) k di =
i

( pAi ) + ( CBki )
2

(39)

The Xmin (pm ; Ckm ) is chosen with the manner that Sm = fm (Sj )j 2
f0


ng is composed of independent signals only. This means that
all Sj are independent.
So, the problem we are dealing with can be written as follows:

1 X (p p ) + (C C ) )
min
(
i
m
ki
km
l l
2

(40)

This problem can be transformed to a quadratic optimization problem

in the following form:

0 p 1
i
B
.
.. C
B
C
B
C
B
C
p
B
k C k min( 1 (X T M X + V X + K )) (41)
8k 2 fi


hg k Xk = B
k k
k
k k k
B
C
Cik C
k k
B
C
B
 ... C
A
Ckk

where :

0
B
B
B
B
B
B
B
 Mk = B
B
B
B
B
B
B


1
1
0 1
0


0 C
2
A
C
B
0 A12 0


0 C
C
B
C
C
B
.. C 0


0
..
..
B
C
C
 .


. . A
C
1
C
0


0 A2 0
C
1
1
C
0






0
2
C
B
C
C
B
1
0






0
0
C
C
B
B2
C
B
0


0
.. C C
..
..
B
A
 .


. . A C

B2

16

the matrix of quadratic optimization. This matrix is (2k; 2k ) dimension. I.e Mk 2 R2k2k . We can demonstrate that the
matrix Mk is symmetric and positive definite, which means
MkT = Mk and 8x 2 R2k1 : xT Mk x > 0.

0
B
B
B
B
 Vk = 2 B
B
B
B
B


0 pm 1
A
B
 ... C
A
pm
0 CAmk 1
B C
B
.
B
A
 .. C
Ckk
B

1
C
C
C
C
C
,
C
C
C
C
A

the vector of quadratic optimization.

The length of this vector is 2k .

0
B
B
B
B
B
 Kk = B
B
B
B
B
B

is 2k .

p2i
A2

..
.

p2k
A22
Ckm
B2

..
.

2
Ckk
B2

1
C
C
C
C
C
C
is a constant vector. The length of this vector
C
C
C
C
C
A

The solution of considered problem consists to find a set of signals

Xm = fSi gi2fj


mg where j < m < n, which satisfy the condition
below. Our object is to define the convenient signal sets with which
we have an optimal storage space that associates an optimal complexity.
So, our new problem will be formulate as follows:

8m 2 0


kfind Xm = Sii2fj


mg k j < m < n

(42)

that succeeds:

8 min ( 1 P C ) = ( 1 P C )
<
ki
ki opt
m
m
8m k Xm = fSigi2f0


mg k : ki=0=0





nn1 P
P
min
(
p(Si)) = ( m1 pi)opt
m m

(43)

To resolve this problem, we try to consider the optimal signal set

as Xopt , which has a length (number of signals inside) nopt such as
nopt < n where n is the total signal number inside the considered
VCD file.
To search Xnopt , we need to consider a discrete probability problem,
which is defined as follows:

for each 8m 2 f0


k g we have a chance probability to get

a solution of our OP problem. This solution can be written
17

Figure 12: Considered Space

18

Figure 13: Variation of the chance of getting optimal solution

1
Cik ; m1 pi ). Let associate to this solution a
as follows: ( m
chance probability qm that satisfies 0 < qm < 1.

we know that for our no pt we have the best chance to get the
P
P
optimal solution ( no1pt Cik ; no1pt pi )of our OP solution. So,
8m 2 f0


kg we have the following condition to be verified :
1 > qnopt  qm > 0. The Figure 13 shows the variation of the
chance to get an optimal solution function of the considered
signal sets.

We can assume that the variation of the chance of getting an optimal

solution is a distribution. So, we can define this distribution, which
will identify the relationship between the chance probability to get an
optimal solution an the signal sets. This distribution can be written
as follows:

19

q(Xi ) = exp(

(Xi Xnopt )T (Xi Xnopt ) ) +

!

(44)

where , ! and are constants.

We note that the peak of the chance is found at the point Xnopt .
Although, we cannot demonstrate that the considered distribution or
density is not symmetric around Xnopt .
If we assume that this density is symmetric around
demonstrate that it will be written as follows:

q(Xi ) = fXnopt ;Mk (Xi ) =

Xnopt ,

we can

(Xi Xnopt )T Mk (Xi Xnopt ) ) (45)

exp(
2
(2) det(Mk )
p1
k

Proof: to prove the equation above, just consider the case of the
p-variate normal distribution for multivariate with p = 2k [5].
So, we can use this equation as a constraint for the optimization
problem defined in equation (41). Always, we can fix the chance to
obtain an optimal solution of considered optimization problem, and
than search the corresponding signal sets which succeeds considered chance probability.
For example is we would like that the chance of getting an optimal solution must be greater than 0:7, we can consider the following
quadratic optimization problem:

8
>
( 1 (X T Mk Xk + Vk Xk + Kk ))
< min
k k k
1
T
>
: (2)k p1det(Mk ) exp( (Xk Xnopt ) M2k (Xk

Xnopt )

)  0:7

(46)

0S 1
i
B C
where k represents the length of the vector Xk =  ... A that must
be identified.

Sk

4.2.2 One signal restoration

In this section we try to treat the case of restoration of one signal from
a signal lists that have been compressed. We know that considered
signal is combination of a signal sets. So, to restore this signal we
need to calculate the function link this signal to all other signals. Indeed the complexity of the restoration depends on the calculation of
20

these signals. This can be so complex so possible. To reduce this

complexity, we need to reduce the complexities of the calculation of
all signal that are dependent of each other. This means that the
restoration depends on the operation number needed to calculate all
required signals.

Sn = Fn (S0 ;


; Sn

(47)

where

Si = Fi (S0 ;


; Sk ) k i; k = 0


n

(48)

So, to calculate Fn () we need first to calculate Fi (). So, the complexity of the function Fn (), will be calculated based on the function
complexities Fi ():

Cn =

n
X
i=0

wi Ci

(49)

where wi represents the weight of the operation belong to signal Si

This problem can be transformed to an optimization problem, which
is
n
X

min
( wiCi )
n

(50)

i=0

4.2.3 Data base optimization

In this section we try to give an overview about the case where the
same signal depends on itself for each clock cycle and/or on signal,
which depends on clock cycle. Although the simplicity of the simulation of the relationship between considered signal and the other
associated signal, we have to solve the problem of storage space
optimization.
Let look at the example of figure 14. We see that the signal a depends on the clock signal. It changes value for each clock signal
cycle.
In the example of figure 14, we see that the signal a will change
value each cock signal cycle. So, if we like to store the signal a,
we will need more storage space. Mathematically, we can write the
following relation between the clock signal clk and the signal a

a(n)

= an
(

1)

XOR 1

(51)

where n is the nth clock signal cycle.

21

P: pro ess
begin
if lk'rising_edge then
a <= a xor '1';
end if;
end pro ess;
Figure 14: VHD model 5
Notice that this equation allows us to restore the signal a at the clock
signal cycle n base on the value of this signal at the clock signal
cycle (n 1). So, we can just store the value of this signal at the first
clock signal cycle and then we can calculate the value of considered
signal recursively. Although the problem is that this calculation of the
value of signal a at the clock signal cycle n is so complex and need
a great schedule time.
To solve this compromise between these problems, we need to find a
solution that reduces the schedule time needed for the restore of the
signal a at the clock signal cycle n, when n is so great so possible
and the storage space needed for the storage of signal a each clock
signal cycle.
Problem formulation: The problem we are going to consider may
be formulated as follows:

8n 2 IN : S n = fn(S n )
( )

find

nopt =

1)

( min((n 1)  SS (a))
n

min
((n 1)  C )
n

(52)

(53)

where SS () is the storage space needed to store a signal value.

This can be transformed as follows:

p 2 IN : n = ip where 1  i  p

(54)

8n; p 2 IN : S n = fnp(S p )

(55)

such as
( )

( )

For each clock signal cycle n, we will try to find an integer p, that
allows to store the signal value S (ip) that minimize the time schedule
22

needed for the restoration of signal value

choose p as follows:

p 2 IN : p

S (n) .

Arbitrary, we can

n
1  10
 p k i = 1


9

(56)

Schedule time analyses: In this paragraph, we prove our choice

of the value of p. Let consider the case, when all values of the signal
a will be stored. So, we need (n 1)  size(a) storage space to
store all values of signal a. However, if we store just the value of a
at the clock signal cycle 0, we will need (n 1)  C0 schedule time
to restore the value of signal a at the clock signal cycle n. Indeed,
n C
if we apply the developed algorithm, we need just p  C0  10
0
schedule time to restore the a signal value at the clock signal cycle
n and just 9  size(a) storage space. So, we have to reduce the
number of schedule time of 10 and the number of storage space of
10 too.

4.3 Waveform Compression Software Design

In this section an overview of the developed software design is presented. Figure 15 represents the general aspect of this software.







FreeHDL Simulator: its task is to simulate a given VHDL design

in order to create the VCD and DDB files for further use.
CDFG Simulator: the CDFG simulator allows to create the
Control Data Flow Graph of considered VHDL model and write
it in a specific file.
Waveform Compressor: its task is the compression of the VCD
file based on the CDFG of considered model. The obtained file
will be stored for further use.
Waveform Decompressor: realizes the decompression of compressed VCD file to view it.
Waveform viewer: allows the viewing of the decompressed
VCD file in order to get out the verification results of considered VDHL design.

Figure 16 represents the software module designs in detail.

Waveform Compressor: the waveform Compressor is composed of two basic modules:

Waveform Compression module: this module interests the
compression techniques. Three compression modules
are employed:
23

Figure 15: Software Design

24




Header file compression module: as it is described

above, the compression of the VCD header file is
done independently of the Control Data Flow Graph.
Simulation Time Compression module: this module
interests the compression of the signal ids throughout the knowledge of considered clock cycle and signal events. It returns the signal ids, which must be
compressed and stored.
Parameter value compression module: this module
realizes the compression of considered parameter values inside the given VCD file based on the information returned from Dependency Scheduler and VCD
file. It returns the signal values, which must be compressed and stored.

Dependency Scheduler module: this module treats the

dependency of signals and processes based on the developed CDFG of the VHDL design. This module has to
control whether a given signal Id and value will be compressed and stored or not. So, it controls the Parameter
Value Compression and the Simulation Time Compression modules. Thereby, it gives the needed information to
the Simulation Time module about which signal Ids that
must be compressed and these to the Parameter Value
Compression about which signal and variable values must
be compressed and stored. On the other hand, it returns
the dependency between signals and variables in mathematic forms to the Waveform Compression module to
be stored. Its input comes from the CDFG Scanner and
Parser.




CDFG Scanner and Parser module: this module translates the

CDFG, which is written in a given file to a data base inside the
memory for further need. Its inputs are coming from the DDB
and CDFG files.
Viewer: the viewer has to get out the verification results of considered VHDL model. Basically it consists of two modules :
Waveform Decompressor: it is composed of four modules, which are needed for the decompression of compressed VCD file.




Header File Decompression module: this module is

used to decompress the VCD header file.
Simulation Time Decompression module: this module allows the decompression of the Simulation Time
25

based on the information returned from the compressed

VCD file and the Dependency Simulator.




Parameter Value Decompression module: this module decompresses all parameter values based on the
information stored in the compressed VCD file and
those returned from the Dependency simulator.
Dependency Simulator module: this module allows to
simulate the stored dependencies between parameters and returns either the parameter value or the the
Simulation Time.

waveform viewer: simulates decompressed VCD file to

get out the Verification results of VHDL model.

5 Time Schedule
In this section we presents the needed time to achieve each module
of this software.












VCD header file compression: already done.

Simulation time compression: one month.
Parameter value compression: one month.
Dependency scheduler: two months.
CDFG scanner and parser: already done.
VCD header file decompression: one month.
Simulation time decompression: two months.
Dependency simulator: three months.
Parameter value decompression: two months.
Waveform viewer: using Dinotrace. Already done.

6 Conclusion
In this document, we presented an idea of using CDFG to improve
the developed waveform compression technique. Two cases for using CDFG in the waveform compression are developed: simple case,
which interests the signal and process dependencies, and complex
case that interests the other VHDL statements. We can conclude
that the CDFG advantages are to allow a rapid interpretation of the

26

Figure 16: Software Module Designs

27

information inside a VHDL model throughout a graphical representation.

7 Reference
[1] E. Naroska, A Novel Approach for Digital Waveform Compression.
[2] E. Naroska, Waveform Compression Technique.
[3] E. Naroska and S. Mchaalia, Control Data Flow Graph for FreeHDL compiler.
[4] J. Ziv and A. Lempel,A Universal Algorithm for Sequential Data
Compression, IEEE Transaction on Information Theory, Vol. IT-23,
No.03, May 1997. [5] The multivariate Normal Distribution, basic
course.
List of Figures














Figure 1 : VCD File.

Figure 2 : VHDL Model 1.
Figure 3 : CDFG of VHDL Model 1.
Figure 4 : VHDL Model 2.
Figure 5: VHDL Signal Assignment procedure.
Figure 6 : CDFG of VHDL Model 2.
Figure 7 : VHDL Model 3.
Figure 8 : CDFG of VHDL Model3.
Figure 9 : VHDL Model 4.
Figure 10 : CDFG of VHDL Model 4.
Figure 15 : Software Design.
Figure 16 : Software Module Designs.

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