Report on

A New Hardware-Efficient Architecture for

Programmable FIR Filters

Submitted By:
Chandrani Saha(14VL07F)
Amrita Kumari(14VL02F)
VLSI Design

Under the guidance of:

Mr. Pathipati Srihari

Department of Electronics and Communication Engineering

Acknowledgement

We would like to convey our heartfelt thanks to Mr. Pathipati Srihari for who
has helped us as our guide by giving his useful suggestions and extending his
knowledge in this field. He has taken the pain to go through the project and
make necessary corrections as and when needed, with his help, the project on
"A New Hardware-Efficient Architecture for Programmable FIR Filters"
has been carried out.

Amrita Kumari
Chandrani Saha

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA

SURATHKAL (KARNATAKA)

Abstract
The basic operation performed by a FIR filter is convolution, i.e. in simple words, number of
additions and multiplications. Instead of having inherent stability, linear phase characteristics
and simple hardware implementations, the problem faced by the FIR filter is the large
number of multiplications and additions required which is directly related to the order of the
filter.
Since multiplication needs more computation time and is more complex to implement than
addition. We need an optimization technique to reduce the number of multiplications
required.
We will exploit the use of generalized modified Booth Algorithm to recode the coefficient of
the filter in radix 4 and then use the booth multiplier will be implemented in the filter.
The main advantage of the proposed technique is the possibility of using it to build
programmable FIR filter.

Introduction
High-speed high-order programmable filters are difficult to be implemented
efficiently
Multiplier-and accumulator (MAC) based architectures are frequently adopted for
programmable filters
Coding of input signals to reduce the multiplication complexity is attractive for
programmable applications
Implementing the MAC of each tap by a Modified Booth multiplier

Algorithm
level

Architecture
level

coding input signals

reformulate the entire

filtering operation

reduction in no. of
additions

Reduction in the internal

wordlength

programmable, low-cost,
accumulation-free tap
structure

flexibly pipelined

Take the associative property

of the addition

pipeline scheme2

Sign extension treatments

The Modifed Booth Algorithm

digit-serial algorithm for performing 2's complement multiplications
c multiplicand; x multiplier at bit level

l = 0, 1,...., (wx/2 )- 1

Fig. 1: Modified Booth Multiplier

B(xl, c) Modified Booth coding function

Application of the Algorithm Reformulation to

FIR Filters

Fig. 2: Direct implementation of digit-serial multiplication and accumulation of N-tap FIR filters

Filter Architecture free of accumulation in each tap

Overview of Project
Studying about booth multiplier based on modified booth algorithm
Writing the code for booth multiplier and D flip-flop to be used as basic building

blocks of an FIR filter in Xilinx Project Navigator in verilog (HDL).

Writing a suitable testbench for the FIR filter (with booth mutiplier) and using it as

stimulus.
Simulation of the HDL code in Modelsim simulator.
Verification of the output with theoretical results.

Verilog Code for Project

MODULE BOOTH MULTIPLIER
module booth_multiplier(product,a,b,clock);
output [15:0] product;
input [7:0] a,b;
input clock;
reg[15:0] product,c;
integer i;
integer d;
initial
begin
product=16'b0;
c=16'b0; // initialising the product to zero
end
always @(posedge clock)
begin
product=16'b0;
for(i=1;i<=7;i=i+2)
// loop for multiplication
begin
if(i==1)
d=b[0]-b[1]-b[1];
// d = b[i-1] + b[i-2] 2b[i]; assume: b[-1]=0
else
d=b[i-1]+b[i-2]-b[i]-b[i];
case(d)
1:
// multiplication by 1
begin
c=a;
c=c<<(i-1);

product=product+c;
end
2:
// multiplication by 2
begin
c=a<<1;
c=c<<(i-1);
product=product+c;
end
-1:
// multiplication by -1
begin
c=~a+1;
c=c<<(i-1);
product=product+c;
end
-2:
// multiplication by -2
begin
c=a<<1;
c=~c+1;
c=c<<(i-1);
product=product+c;
end
endcase
end
end
endmodule

MODULE D FLIP-FLOP
module dff(clk,rst,d,q);// sub module d flipflop
input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;
always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end
endmodule
TOP MODULE FIR FILTER
module newfilter(clk,rst,x,dataout,c1,c2,c3,c4,c5,c6);

input [7:0]x;
input [7:0]c1,c2,c3,c4,c5,c6;
input clk,rst;
output [17:0]dataout;
wire [15:0]d1,d2,d3,d4;
wire[15:0] b1,b2,b3,b4,b5,b6;
wire [7:0]d11,d12,d13,d14,d15;
booth_multiplier booth1(.product(b1),.a(x),.b(c1),.clock(clk));
dff u2(clk,rst,x,d11);
booth_multiplier booth2(.product(b2),.a(d11),.b(c2),.clock(clk));
assign d1=b1+b2;
dff u4(clk,rst,d11,d12);
booth_multiplier booth3(.product(b3),.a(d12),.b(c3),.clock(clk));
assign d2=b3+d1;
dff u6(clk,rst,d12,d13);
booth_multiplier booth4(.product(b4),.a(d13),.b(c4),.clock(clk));
assign d3=b4+d2;
dff u8(clk,rst,d13,d14);
booth_multiplier booth5(.product(b5),.a(d14),.b(c5),.clock(clk));
assign d4=b5+d3;
dff u10(clk,rst,d14,d15);
booth_multiplier booth6(.product(b6),.a(d15),.b(c6),.clock(clk));
assign dataout=b6+d4;//dataout
endmodule

TEST BENCH FOR SIMULATION

module newfilter_fir_booth_tb_v_tf();

// Inputs
reg clk;
reg rst;
reg [7:0] x;
reg [7:0] c1;
reg [7:0] c2;
reg [7:0] c3;
reg [7:0] c4;
reg [7:0] c5;
reg [7:0] c6;

// Outputs
wire [17:0] dataout;

// Bidirs

// Instantiate the UUT

newfilter uut (
.clk(clk),
.rst(rst),
.x(x),
.dataout(dataout),
.c1(c1),
.c2(c2),
.c3(c3),
.c4(c4),
.c5(c5),
.c6(c6)
);

// Initialize Inputs
initial begin
clk = 0;
rst = 0;
x = 0;
c1 = 0;
c2 = 0;
c3 = 0;
c4 = 0;
c5 = 0;
c6 = 0;
#100;
rst=1;
#100;
rst=0;
x=8'b00001000;
c1=8'b00000001;
c2=8'b00000010;
c3=8'b00000011;
c4=8'b00000001;
c5=8'b00000010;
c6=8'b00000011;
#600;
rst=1;
#100;
rst=0;
x=8'b00000101;
#600;

rst=1;
#100;
rst=0;
x=8'b00000100;
#600;
rst=1;
#100;
rst=0;
x=8'b00000010;

end
always
begin
#50 clk=~clk;
end
endmodule

RTL Schematic

Simulation result in Modelsim

References
Hwan Rei Lee, Chein Wei Jen, Member, IEEE, and Chi-Min Liu A New

Hardware-Efficient Architecture for Programmable FIR Filters IEEE

transactions on circuits and systems-11: analog and digital signal
processing, vol. 43, no. 9,pp 637-644 september 1996
Young-Ho Seo , Member, IEEE, and Dong Wook Kim , Member, IEEE A

New VLSI Architecture of Parallel MultiplierAccumulator Based on

Radix-2Modified Booth Algorithm IEEE transactions on very large scale
integration (vlsi) systems, vol. 18, no. 2, pp 201-208 February 2010
Elisardo Antelo, Member, IEEE, and Paolo Montuschi, Reducing the

Computation Time in Twos Complement Multipliers IEEE

transactions on computers, vol. 60, no. 2, pp 148-156 February 2011