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UNIVERSITY OF NEBRASKA AT OMAHA

COURSE SYLLABUS/DESCRIPTION
Department and Course Number
Course Title
Course Coordinator
Total Credits
Date of Last Revision
1.0

2.0

Course Description
1.1

Overview of content and purpose of the course (catalog description)


This course is built on the principal of digital logic covered in CSCI 2710. Topics
covered include: Register Transfer Languages, Non-pipelined CPU detailed design both
hardwired and micro-programmed, instruction format formats for three architectures
Stack, AC-based and general purpose based, assembly programming, memory
organization and cache, floating-point arithmetic, and input-output organization.

1.2

For whom course is intended


The course is intended for undergraduate computer science majors.

1.3

Prerequisites of the course (courses)


CSCI 2710 and CSCI 3320 (could be taken concurrently)

1.4

Prerequisites of the course (topics)


1.4.1 Knowledge of the principals of digital logic design for both combinational and
sequential circuits
1.4.2 Knowledge of programming

1.5

Unusual circumstances of the course


None

Objectives
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8

3.0

CSCI 3710
Introduction to Computer Organization and
Architecture
Hassan Farhat
3
June 19, 2003

Study Register Transfer Language (RTL).


Study the details of a simple AC-based CPU (hardwired).
Study the details of a simple AC-based CPU (microprogrammed).
Study assembly instruction formats for different architectures (CISC, RISC etc.).
Convert high-level constructs to assembly constructs.
Study computer arithmetic including floating-point arithmetic.
Study memory hierarchy with an emphasis on cache organization.
Study input-output organization and the different forms of interrupts.

Content and Organization


3.1

Register Transfer and Microoperations


3.1.1 Register Transfer Language
3.1.2 Register Transfer
3.1.3 Bus and Memory Transfers
3.1.3.1 Three-State Bus Buffers

Contact hours
X.X

3.2

3.3

3.1.3.2 Memory Transfer


3.1.4 Arithmetic Microoperations
3.1.4.1 Binary Adder
3.1.4.2 Binary Adder-Subtractor
3.1.4.3 Binary Incrementer
3.1.4.4 Arithmetic Circuit
3.1.5 Logic Microoperations
3.1.5.1 List of Logic Microoperations
3.1.5.2 Hardware Implementation
3.1.6 Shift Microoperations
3.1.6.1 Hardware Implementation
3.1.7 Arithmetic Logic Shift Unit
AC-Based Computer Organization and Design
3.2.1 Instruction Codes
3.2.1.1 Stored Program Organization
3.2.1.2 Indirect Address
3.2.2 Computer Registers
3.2.2.1 Common Bus System
3.2.3 Computer Instructions
3.2.3.1 Instruction Set Completeness
3.2.4 Timing and Control
3.2.5 Instruction Cycle
3.2.5.1 Fetch and Decode
3.2.6 Register-Reference Instructions
3.2.7 Memory-Reference Instructions
3.2.8 Input-Output and Interrupts
3.2.8.1 Input-Output Configuration
3.2.8.2 Input-Output Instructions
3.2.8.3 Program Interrupt
3.2.8.4 Interrupt Cycle
3.2.9 Complete Computer Description
3.2.10 Design of Basic Computer
3.2.10.1 Control of Logic Gates
3.2.10.2 Control of Registers and Memory
3.2.10.3 Control of Single Flip-Flops
3.2.10.4 Control of Common Bus
3.2.11 Design of Accumulator Logic
3.2.11.1Control of AC Register
3.2.11.2Adder and Logic Circuit
Assembly Programming
3.3.1 Machine Language
3.3.2 Assembly Language
3.3.2.1 Rules of the Language
3.3.2.2 Translation to Binary
3.3.3 The Assembler
3.3.3.1 Representation of Symbolic Program in Memory

X.X

X.X

3.4

3.5

3.3.3.2 First Pass


3.3.3.3 Second Pass
3.3.4 Program Loops
3.3.5 Programming Arithmetic and Logic Operations
3.3.5.1 Multiplication Program
3.3.5.2 Double-Precision Addition
3.3.5.3 Logic Operations
3.3.5.4 Shift Operations
3.3.6 Subroutines
3.3.6.1 Subroutines Parameters and Data Linkage
3.3.7 Input-Output Programming
3.3.7.1 Character Manipulation
3.3.7.2 Program Interrupt
Microprogrammed Control design
3.4.1 Control Memory
3.4.2 Address Sequencing
3.4.2.1 Conditional Branching
3.4.2.2 Mapping of Instruction
3.4.2.3 Subroutines
3.4.3 Microprogram Example
3.4.3.1 Computer Configuration
3.4.3.2 Microinstruction Format
3.4.3.3 Symbolic Microinstructions
3.4.3.4 The Fetch Routine
3.4.3.5 Symbolic Microprogram
3.4.3.6 Binary Microprogram
3.4.4 Design of Control Unit
3.4.4.1 Microprogram Sequencer
Alternative Processor Architectures and Instruction types
3.5.1 General Register Organization
3.5.1.1 Control Word
3.5.1.2 Examples of Microoperations
3.5.2 Stack Organization
3.5.2.1 Register Stack
3.5.2.2 Memory Stack
3.5.3 Instruction Formats
3.5.3.1 Three-Address Instructions
3.5.3.2 Two-Address Instructions
3.5.3.3 One-Address Instructions
3.5.3.4 Zero-Address Instructions
3.5.3.5 RISC Instructions
3.5.4 Addressing Modes
3.5.5 Data Transfer and Manipulation
3.5.5.1 Data Transfer Instructions
3.5.5.2 Data Manipulation Instructions
3.5.5.3 Arithmetic Instructions

X.X

X.X

3.6

3.7

3.8

3.5.5.4 Logical and Bit Manipulation Instructions


3.5.5.5 Shift Instructions
3.5.6 Program Control
3.5.6.1 Status Bit Conditions
3.5.6.2 Conditional Branch Instructions
3.5.6.3 Subroutine Call and Return
3.5.6.4 Program Interrupt
3.5.6.5 Types of Interrupts
3.5.7 Reduced Instruction Set Computer (RISC)
3.5.7.1 CISC Characteristics
3.5.7.2 RISC Characteristics
3.5.7.3 Overlapped Register Windows
Pipeline Processing
3.6.1 Pipelining
3.6.1.1 General Considerations
3.6.2 Arithmetic Pipeline
3.6.3 Instruction Pipeline
3.6.3.1 Example: Four-Segment Instruction Pipeline
3.6.3.2 Data Dependency
3.6.3.3 Handling of Branch Instructio
3.6.3.4 RISC Pipeline
3.6.3.5 Example: Three-Segment Instruction Pipeline
3.6.3.6 Delayed Load
3.6.3.7 Delayed Branch
3.6.4 Vector Processing
3.6.4.1 Vector Operations
3.6.4.2 Matrix Multiplication
3.6.4.3 Memory Interleaving
Computer Arithmetic
3.7.1 Multiplication Algorithms
3.7.1.1 Hardware Implementation for Signed-Magnitude Data
3.7.1.2 Hardware Algorithm
3.7.1.3 Booth Multiplication Algorithm
3.7.1.4 Array Multiplier
3.7.2 Division Algorithms
3.7.2.1 Hardware Implementation for Signed-Magnitude Data
3.7.2.2 Divide Overflow
3.7.2.3 Hardware Algorithm
3.7.2.4 Other Algorithms
3.7.3 Floating-Point Arithmetic Operations
3.7.3.1 Basic Considerations
3.7.3.2 Register Configuration
3.7.3.3 Addition and Subtraction
3.7.3.4 Multiplication
3.7.3.5 Division
Input-Output Organization

X.X

X.X

X.X

3.8.1

3.9

Input-Output Interface
3.8.1.1 I/O Bus and Interface Modules
3.8.1.2 I/O versus Memory Bus
3.8.1.3 Isolated versus Memory-Mapped I/O
3.8.1.4 Example of I/O Interface
3.8.2 Asynchronous Data Transfer
3.8.2.1 Strobe Control
3.8.2.2 Handshaking
3.8.2.3 Asynchronous Serial Transfer
3.8.2.4 Asynchronous Communication Interface
3.8.2.5 First-In, First-Out Buffer
3.8.3 Modes of Transfer
3.8.3.1 Example of Programmed I/O
3.8.3.2 Interrupt-Initiated I/O
3.8.3.3 Software Considerations
3.8.4 Priority Interrupt
3.8.4.1 Daisy-Chaining Priority
3.8.4.2 Parallel Priority Interrupt
3.8.4.3 Priority Encoder
3.8.4.4 Interrupt Cycle
3.8.4.5 Software Routines
3.8.4.6 Initial and Final Operations
3.8.5 Direct Memory Access (DMA)
3.8.5.1 DMA Controller
3.8.5.2 DMA Transfer
3.8.6 Input-Output Processor (IOP)
3.8.6.1 CPU-IOP Communication
3.8.6.2 IBM 370 I/O Channel
3.8.6.3 Intel 8089 IOP
3.8.7 Serial Communication
3.8.7.1 Character-Oriented Protocol
3.8.7.2 Transmission Example
3.8.7.3 Data Transparency
3.8.7.4 Bit-Oriented Protocol
Memory Organization
3.9.1 Memory Hierarchy
3.9.2 Main Memory
3.9.2.1 RAM and ROM Chips
3.9.2.2 Memory Address Map
3.9.2.3 Memory Connection to CPU
3.9.3 Auxiliary Memory
3.9.3.1 Magnetic Disks
3.9.3.2 Magnetic Tape
3.9.4 Associative Memory
3.9.4.1 Hardware Organization
3.9.4.2 Match Logic

X.X

3.9.5

4.0

3.9.4.3 Read Operation


3.9.4.4 Write Operation
Cache Memory
3.9.5.1 Associative Mapping
3.9.5.2 Direct Mapping
3.9.5.3 Set-Associative Mapping
3.9.5.4 Writing into Cache
3.9.5.5 Cache Initialization

Teaching Methodology
4.1

Methods to be used
The primary teaching methods will be lecture, in-class demonstrations, and lab
assignments.

4.2

Student role in the course


The student will attend lectures and demonstration, participate in discussion on assigned
readings, complete assigned homework, and complete required examinations

4.3

Contact hours
Three hours per week

5.0

Evaluation
5.1

Type of student projects that will be the basis for evaluating student performance,
specifying distinction between undergraduate and graduate, if applicable. For Laboratory
projects, specify the number of weeks spent on each project).
Students will complete a sequence of four assembly language assignments. Students will
participate in the design simulation of a simple AC- based CPU. This is in addition to
three examinations.

5.2

Basis for determining the final grade (Course requirements and grading standards)
specifying distinction between undergraduate and graduate, if applicable.
Component
Exams
Homework/ Lab Assignments
Participation

Grading
80%
15%
5%

5.3

Grading scale and criteria.


Points
97-100%
93-96%
90-92%
87-89%
83-86%
80-82%
77-79%
73-76%
70-72%
67-69%
63-66%
60-62%
0-59%

6.0

Grade
A+
A
A
B+
B
B
C+
C
C
D+
D
D
F

Resource Material
6.1

Textbooks and/or other required readings used in course


M. Mano, Computer System Architecture, 3rd Edition, Prentice Hall, 1993.

6.2

Other suggested reading materials, if any


None

6.3

Other sources of information


None

6.4

Current bibliography of resource for students information


6.4.1

William Stallings, Computer Organization and Architecture: Designing for


Performance, 6th edition, Prentice Hall, 2003.
6.4.2 Randal E. Bryant, David R. O'Hallaron, Computer Systems: A Programmer's
Perspective, Prentice Hall, 2003
6.4.3 G. Karam and J. Bryant, Principles of Computer Systems, Prentice Hall, 1992.
6.4.4 J. Carpinelli, Computer Systems Organization and Architecture, Addison-Wesley,
2001.
6.4.5 V. Hamacher, Z. Vranesic and S. Zaky, Computer Organization, 4th edition,
McGraw-Hill, 1996.
6.4.6 V. Heuring and H. Jordan, Computer System Design and Architecture, AddisonWesley, 1997.
6.4.7 P. Abel, IBM PC Assembly Language and Programming, Prentice Hall, 1995.
6.4.8 J. Hayes, Computer Architecture and Organization 3rd edition, McGraw-Hill,
1998.
6.4.9 M. Murdocca and V. Heuring, Principles of Computer Architecture, Prentice Hall,
2000.
6.4.10 J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach,
2nd edition, Morgan Kaufmann, 1996.

6.4.11 J. Hennessy and D. Patterson, Computer Organization and Design: The


Hardware/Software Interface, 2nd edition, Morgan Kaufmann, 1998.
6.4.12 M. Mano, Computer System Architecture, 3rd Edition, Prentice Hall, 1993.
6.4.13 W. Stallings, Computer Organization and Architecture, 5th Edition, Prentice Hall,
2000
6.4.14 Andrew S. Tanenbaum, Structured Computer Organization, 4th edition, Prentice
Hall, 1999.
6.4.15 James Evans, Itanium Architecture for Programmers: Understanding 64-Bit
Processors and EPIC Principles, Prentice Hall 2003.
7.0

Computing Science Accreditation Board Category Content (class time in hours)


CSAB Category
Data Structures
Computer Organization and Architecture
Algorithm and Software Design
Concepts of Programming Languages

8.0

Core

Advanced

35
3
3

Oral and Written Communications


Every student is required to submit at least __0___ written reports (not including exams, tests,
quizzes, or commented programs) to typically _____ pages and to make ___0__ oral
presentations of typically _____ minutes duration. Include only material that is graded for
grammar, spelling, style, and so forth, as well as for technical content, completeness, and
accuracy.

9.0

Social and Ethical Issues


No coverage

10.0

Theoretical content
The course is considers theoretical aspects of Boolean algebra, and finite state machine design
and minimization.

11.0

Problem analysis
The course is an introduction to computer architecture. As a result, design problems from
Register Transfer Languages are analyzed. The designed solutions are considered in the analysis
aspect of the design.

12.0

Solution design
The solution design includes translating the word problem into a formal description in the
context of state machines, ASM charts, and microoperations realization.

CHANGE HISTORY
Date
Change
06/19/2003 Initial ABET version
06/19/2003 Cleanup

By whom
Farhat
Wileman

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