University of Waterloo

CS 251 Midterm Exam

Fall 2009
CS 251: Computer Organization & Design
Instructor: Richard Mann and Stephen Mann
October 29, 2009
Start time: 4:30 PM. End Time: 6:30 PM.
Duration: 120 minutes
Number of exam pages (including this cover sheet): 9
CLOSED BOOK
Name:
Student Number:
Signature:

# Points Possible Score Comments

1
10
2
10
3
10
4
10

Directions
Write your name and Student ID Number on every page. The points for each
problem appear in the table above and in the question. The instructor reserves
the right to adjust the value of individual problems if they are deemed too hard
or too easy.
If you need extra paper for a question, use the back of that questions page.
If you need more paper beyond this, ask the proctors for blank pages. IT IS
YOUR RESPONSIBILITY TO ENSURE THAT ANY EXTRA PAGES ARE
STAPLED TO THIS EXAM.

Name:
1. (10 Points)

Student Number:
Short Answer

(a) (2 pts) Give the unreduced, minterm expression for F based on the following truth
table.
A B C F
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
(b) (2 pts) Circle the gate(s)/circuit(s) that are NOT equivalent to a NAND gate.

A
B

A
B

A
B

A
B

(c) (1 pt) Circle the symbol below that represents a MUX.

3

(d) (2 pts) What decimal number does the following single precision, IEEE floating
point number represent? For single precision IEEE floating point numbers, the
exponent has a bias of 127.
Sign
1

Exponent
128

Significand
0

Decimal value:

(e) (1 pt) Here is a clock pulse:

In this figure, circle the falling edge of the clock.

using only NAND gates.
(f) (2 pts) Draw a circuit for F = AB + B C + AC

CS 251

Name:
2. (10 Points)

Student Number:

(a) (1 pt) Find the 16-bit 2s complement representations of the following 8-bit 2s
complement signed numbers:
1010 0101
0101 1110
(b) (1 pt) If you wanted to build hardware to do the sign extension described in
part (a), how many gates are required?

(c) (1 pt) Negate the following number, expressed in 8-bit 2s complement representation.
0101 0110
(d) (3 pts) Using 8-bit 2s complement addition, perform the following computations,
noting overflow if it occurs. You should take the 2s complement of any of the
operands as needed. Show your work.
1101 0111
+1011 1101

1010 0111
0101 0110

(e) (2 pt) Compute the following bitwise logical operations.

0101 1110
XOR 0000 1111

0101 1110
OR 0000 1111

(f) (2 pt) Compute the arithmetic shift left by 1 bit and the arithmetic shift right by
1 bit of the following 8 bit binary number:
1110 0010
Shift left:
Shift right:

CS 251

Name:
3. (10 Points)

Student Number:
Consider the following next-state table and corresponding output table:
S1
0
0
0
0
1
1
1

S0
0
0
1
1
0
1
1

A S10
0 0
1 0
0 1
1 1
X X
0 0
1 1

S00
1
0
1
1
X
0
1

S1
0
0
1
1

S0
0
1
0
1

B
0
1
X
1

(a) (6 points) Draw the finite state machine for this next state table.

(b) (4 pts) Complete the table below tracing the above finite state machine on a
particular sequence of input bits. Note that the Next State of one column is the
Current State for the next column.

Current State
A
B
Next State

CS 251

00
0

Name:
4. (10 Points)

Student Number:
For the assembly language instruction

1000: lw $1,500($3)
(a) (6 pts) In the figure on the next page, there are 6 dark lines. On each line,
write in the value that travels along the corresponding wire(s) when executing
this assembly language instruction.
Assume that each register $i (with i > 0) contains the decimal value 20010 +i.

(b) (4 pts) In the table below, write the values of the control lines coming out of the
Control unit to execute this instruction.
You will find MIPS instruction formats and tables of the effects of some of the
control signals on the last page of this exam. You should be able to determine
the effects of the remaining signals from the datapath diagram.
Type Reg ALU
Dst Src
lw

CS 251

Mem
ToReg

Reg
Write

Mem Mem
Read Write

Branch ALU
op1

ALU
op0

CS 251

PC

Instruction
memory

Read
address

Instruction
[310]

Add

Instruction [15 0]

Instruction [15 11]

Instruction [20 16]

Instruction [25 21]

Instruction [31 26]

0
M
u
x
1

Control

16

Instruction [5 0]

Write
data

Sign
extend

Read
data 1
Read
register 2
Registers Read
Write
data 2
register

Read
register 1

RegWrite

ALUSrc

MemWrite

ALUOp

MemRead
MemtoReg

RegDst
Branch

32
ALU
control

0
M
u
x
1

Shift
left 2

Zero
ALU ALU
result

Add ALU
result

Write
data

Address

Data
memory

Read
data

M
u
x

1
M
u
x
0

PCSrc

Name:
Student Number:
(Question 4, continued)

Name:
5. (10 Points)

Student Number:

(a) (6 pts)
We wish to add a new instruction dbnz (decrement, branch non-zero) to the singlecycle datapath. The dbnz instruction is an I-format instruction that decrements
a register, and branches if the result of the decrement is non-zero.
The format of this I-format instruction is
6 bits
dbnz

5 bits
rs

5 bits
rt

16 bits
offset

The effect of this instruction is as follows:

rt <- rs-1
if rt != 0
PC <- PC+4 + 4*offset
else
PC <- PC+4
Modify the datapath of the single cycle computer appearing on the next page
of this exam to enable it to perform this operation. In your solution, add any
necessary data paths and control signals.
(b) (4 pts)
In the table below, give the settings of the control bits to implement the lpcreg
MIPS instruction. Use Dont Cares where appropriate. If you need an extra
control line to implement this instruction or if you need to increase the number of
bits in a control line, add additional columns to the table for the new control line,
split a column to increase the number of bits in a control line, and in either case
include a note below explaining the effect of the new/increased control line(s) on
the datapath.
You will find MIPS instruction formats and tables of the effects of some of the
control signals on the last page of this exam. You should be able to determine
the effects of the remaining signals from the datapath diagram.
Type Reg ALU
Dst Src
dbnz

CS 251

Mem
ToReg

Reg
Write

Mem Mem
Read Write

Branch ALU
op1

ALU
op0

dbnz

Sign
extend

#

!*
 ')
 (  
 
 

%

Registers

M
u
x

ALU
control
M
u
x

/#M 

 

M 
  8

7

  &(0

  8

7
#/
  &(0

 
 
  &(0

N
 




!*
 ' "
   
 

!*' "
   
 

&!%$ # "
   
 
! $
# '# "
   
 

&!%8
#  "
   
 

!  
  
 

>

 



Instruction
memory

?


 M 
N

 

  8

&7(0
 

,
= 43
2 1
  8

.
7 (-,+
6,
5 43
2 1
0/ .
 (-,+
.
 (-,+
: 

9
<
 &;(0
 

PC

Control

ALU

M 
  8

7
[
  1

EK QJ
D I HC GF
SFG R

Shift
left 2

Data
memory

M 
 

K JI HGF
4E
D C

Add

Add

M
u
x

M
u
x

?


XF WV
U T
?
L

CS 251

Student Number:
(Question 5 continued)
Name:

Name:

Student Number:

MIPS and architecture details

(You may remove this page from your exam.)
Instruction formats
R-format: add $t1, $t2, $t3 add rd,rs,rt
31

26 25

0
6 bits

21 20

16 15

11 10

rs

rt

rd

5 bits

5 bits

5 bits

6 5

shamt
5 bits

funct
6 bits

Load/store: lw $t1, 100($t2) lw rt,100(rs)

31

26 25

35/43
6 bits

21 20

16 15

rs

rt

5 bits

5 bits

offset
16 bits

Jump: j 3000
31

26 25

address

6 bits

26 bits

Single Cycle Computer Tables

Signal
RegWrite
MemRead
MemWrite

CS 251

Signal=0
no effect
no effect
no effect

Signal=1
register written
memory read
memory written

ALUOp
00
01
10
11

Operation
Add
Subtract
Funct Bits