Design of a Under Voltage Lock Out Circuit with

Bandgap Structure
Li Fuhua, Wang Wei, Hang Qiuping, Xie Weiguo, Lu Zhenghao
Department of Microelectronics,
School of Electronics and Information, Soochow University.
Suzhou, Jiangsu, CHN, 215021
block will protect the chip when any other situations lead the
voltage source to fluctuate below Voff. If it occurs, the chip will
be reset, the reference voltage will not be produced, and all the
logic operation will be prohibited.

AbstractAccording to the necessary function of Under

Voltage Lock Out (UVLO) in DC-DC power management
systems, an improved UVLO circuit is proposed. The circuit
realizes stabilization of parameters such as threshold point
voltage, hysteretic range of the comparator etc. without utilizing
an extra bandgap reference voltage source for comparison. The
UVLO circuit is implemented in CSMC 0.5m BCD process.
Hspice simulation results show that the UVLO circuit presents
advantages such as simple topology, sensitive response, low
temperature draft, low power consumption.
Index TermsUnder Voltage Lock Out; Power management;
Low Power; Hysteretic range, BCD process

I.

INTRODUCTION

With the development of the integrated circuit technology,

the requirements for the power management chips, such as
switching frequency, transmission delay, stability, power
consumption etc., are more and more important to make sure
the chips could work in any situation.

Figure 1. A DC-DC power supply management system

Generally, when the DC-DC power management system

starts up, the power supply charges the chip via the input
equivalent capacitor and resistor. The chip voltage rises
gradually to its start-up level. However, the system is likely
turned off over again just after opening if the load currents of
the system are too large. So IC designers often use the UVLO
(Under Voltage Lock-Out) circuit to make sure that the system
starts up normally and works steadily. Moreover, the UVLO
circuit has the function of supervising the power supply voltage
momentarily to avoid its fluctuation jeopardizes the total
circuits and the system.

Figure 2. Traditional UVLO circuit topology

Figure 1 illustrates a DC-DC power management system.

The Vstr pin connects directly to the rectified AC line 220V
voltage source and is capable of tolerating a maximum 650V.
The UVLO circuit monitors the power supply of the system
momentarily as long as the DC-DC converter connects to the
power supply. At startup, the internal high voltage current
source supplies internal bias and charges the external VCC
capacitor via the Vstr pin. It is not until VCC reaches the UVLO
threshold voltage Von that the UVLO output level turns over;
the IC internal start-up switch opens; the Vstr pin is shorted to
ground; the chip is supplied from the auxiliary transformer
winding. As noted above, the UVLO circuit also sets a stop
voltage Voff (Voff < Von) to avoid the situation that the system is
shut off just after its starting up. Simultaneously, the UVLO

It can be seen that the UVLO circuit is a hysteretic voltage

comparator essentially. It must have the characteristics of rapid
reaction speed, steady threshold voltage, reasonable hysteretic
range and low temperature drift.
But the UVLO circuits of many power management ICs are
comprised of voltage comparators, a bandgap voltage
reference, and some logic components as shown in Figure 2.
These circuits have high power consumption are too complex
to lower cost. Moreover, the bandgap voltage source only
produces an exact reference voltage within limits. If the
reference voltage is not stable, it could hurt the system no
matter it is higher or lower than the normal value.

224

ISIC 2009

currents of Q1 and Q2 respectively. Accordingly, the bandgap

reference comparator works by the principle of the difference
of their collector currents varying rate. It compares IC2 with IC1
by setting the latter as the reference value.

This paper proposes a novel UVLO circuit based on 0.5m

BCD process technology. It could reach the UVLO
performances without utilizing complex digital logic, an extra
bandgap voltage reference, and comparators. The primary
characteristics of the design circuit are simple circuit topology,
rapid reaction speed, low temperature drift, accurate threshold
voltage and low power consumption.
II.

There are three situations when the power supply VCC rises
from the low value to the high gradually.
Case1 because the equivalent transconductance of Q1 is
lower than that of Q2 as noted above, IC2 is smaller than IC1
when VCC does not reach to normal supply voltage. If M1, M2,
M3, M4, M5, M6 all work in saturation region, ID6, which equals
with IC1 through two current mirrors of M1, M2 and M5, M6, is
larger than ID4, which equals with IC2 through another current
mirror M3, M4. Where ID4 and ID6 are drain currents of M4 and
M6 respectively. It is impossible in the same direct current
gateway. It is noted that both of ID4 and ID6 are absolute values.
Hence, M6 has to operate in linear region to make sure its drain
current equals with ID4. Node X, the output of the band gap
reference comparator, is low. Through the inverter, UVLO
output is high level, which will shut off the bias and reference
voltage source, lock out the whole system. We should note that
M9 works in saturation region at this time.

CIRCUIT DESIGN

The designed UVLO circuit is shown in Fig.3. The

comparator utilizing bandgap reference principle consists of
Q1, Q2, R1, and R2. Some references define this structure as
bandgap reference comparator [1]. M2 and M3 are the active
loads of the comparator. There are current mirrors, M1, M2, M3,
M4, M5 and M6, used as active loads in this topology. The
resistive divider consists of R3, R4, R5, R6 and M9. The function
of M9 will be discussed elaborately later. R7, M7, R8 and M8 are
two inverters. Vaa is obtained by connecting VCC to zener diode.

Case 2 when VCC continuously rises to be close to Von, the

collector currents of Q1 and Q2 are appropriately equal. That is,
IC1IC2. Thus, all of the MOSFETs wok in saturation region
and have equal drain currents. If we choose Vaa=5V, the
potential at X node is higher than threshold voltage of M7,
because the pullup of the PMOS is as 2 or 3 times as the
pulldown of the NMOS. We choose the W/L ratios of M7 and
M8 are equal, R7 = R8. Thus,
Figure 3. Schematic of the designed UVLO with bandgap reference

VUVLO = VGS 9 = Vaa I D 7 ,8 R7 ,8

We assume the emitter area of Q1 is as 6 times as that of Q2.

So the transconductance relationship of the two bipolars is as
follows [2][3]:

g m1 = 6 g m 2

The output of UVLO is still high if we choose the proper

W/L ratios of M7 and M8, the proper values of R7 and R8.
Consequently, it also reaches to the purpose of shutting off the
reference voltage source and locking out the whole system. It is
noted that M9 still works in saturation region in this situation.

(1)

Because of the feedback of their emitter resistors R1 and R2, the

equivalent transconductances of the two bipolars are
g m1
1 + g m1 ( R1 + R2 )

Gm1 =

1
+ g m 2 ( R1 + R2 )
6
gm2
1 + g m 2 R2 + g m 2 R1 +

Gm 2 =

gm2
1 + g m 2 R2

Case 3 IC2 exceeds IC1 rapidly once VCC is a little higher

than the system startup voltage Von. It is impossible that ID6 is
smaller than ID4 in the same one direct current gateway, which
is similar with case 1. So M4 is impelled to work in linear
region to make sure ID4 = ID6. Thus, it is high level at node X,
and it is low level through inverter. M9 is shut off. Sequentially,
the voltage at node A is pulled up higher to ensure the output of
UVLO is low. The chip works normally in this case. We can
see that the UVLO circuit has a very rapid reaction speedy
because the mirrored pairs are quite sensitive to the difference
of their currents.

(2)

gm2

1
1
6

(6)

(3)

(4)

There are also three situations when VCC becomes lower

from the high value.
When VCC < Voff, it is similar with case 3 above, IC1 < IC2.
M4 is in saturation region and M9 is cut-off. Thus the output of
UVLO is low.

(5)

When VCC continuously drops to be close to Voff, as

discussed in case 2 above, IC1IC2. All of the MOSFETs in the
bandgap reference comparator are in saturation region and M9
is still cut-off. The output of UVLO is low, too.

Generally, gm2R1>>1. So Gm1<Gm2. That is to say, the

varying rate of IC1 is much rapider than that of IC2 as VCC
fluctuates. Where IC1 and IC2 are assumed to be the collector

225

When VCC drops below Voff, IC1 > IC2, M6 is in linear

region. The voltage at node X is low, and M9 is on.
Consequently, the effect of UVLO is reinforced. Note that Von
Voff.

Voff =

R + R4 + (R5 R6 ) R3 + R4 + R5
Von Voff = 3

VREF 17
R4 + R5
R4 + (R5 R6 )
III.

We use Hspice tool to simulate the UVLO circuit based on

CSMC 0.5m BCD process technology. As known above,
UVLO output is correlated closely with the slops of the
collector current curves of Q1 and Q2. So we simulate the
currents of the two bipolars varying with VCC as shown in
Fig.4. Obviously, before 2ms, IC1 > IC2, UVLO is high. At 2ms,
both of the currents of the two bipoars increase sharply.
However, since the transconductance of Q2 is smaller than that
of Q1. Quickly, IC1 < IC2. The output of UVLO is low. It is the
same after 2ms.

We know the voltage between base and emitter of bipolar is

VBE = VT ln

IC
IS

and, IS SE. Where SE is the emitter area of the bipolar.

Because the emitter area of Q1 is as six times as that of Q2,
I C1 = I C 2 =

VT ln 6
R1

VREF = VBE 2 + 2 I C 2 R2
= VBE 2 + 2

R2
VT ln 6
R1

It should be considerate in practice that the DC-DC chips are

often applied in a wide range of temperature and both
resistances and bipolars of the process vary largely with
temperatures. Thus the designed circuit is also simulated with
different temperature. We do the best to reduce the errors of the
hysteretic range and the threshold voltage to satisfy the
requirement used in a wide range of temperature. The outputs
of UVLO circuit varying with VCC, in -40, 25, 80 and
140 respectively, are shown in Table 1 and Fig. 5. We can
see that the maximum error voltage is no larger than 0.2V.
Thus the prominent advantage of the designed circuit is that it
can work in a wide range of temperature.

9
10
11

We know the base-emitter voltage VBE exhibits a negative

temperature coefficient, while VT exhibits a positive one [4].
We can generate a voltage that remains constant with
temperature if we choose a proper ratio of R1 and R2. Von and
Voff will be calculated respectively as follows.

14

When VCC rises but does not reach to Von, UVLO is high
and M9 is on (The turn-on resistance is ignored). As discussed
above, the voltage at node A is
R4 + ( R5 R6 )
R3 + R 4 +( R5 R6 )

VCC

12

The output of UVLO only reverses when VA > VREF. Thus

the turn-on voltage Von can be gained:
R4 + ( R5 R6 )
R3 + R 4 +( R5 R6 )
Von =

Von = VREF

R3 + R4 + ( R5 R6 )
R4 + ( R5 R6 )

13

R4 + R5
Von
R3 + R4 + R5

IC2

30.0

10

25.0

20.0

15.0

10.0

5.0

0.0

2.0m

4.0m

6.0m

0.0

8.0m

t(s)

VREF

14

Figure 4. Curves of

I C1 , I C 2 and the output of UVLO circuit versus VCC

Moreover, the power consumption is very litter when the

system UVLO occurs. This is because the other blocks of the
chip except UVLO circuit do not work, and do not consume the
power. The main power consumption consists is from the
currents following through bipolars, R3, R4, R5, R6. Thus we
can lower the power consumption by increasing the values of
the resistors. But taking into the account of layout area, the
power consumption could be decreased to 150W by
simulating in fact.

Once VCC > Von. M9 is turn-off. At this time, the voltage at

node A is
VA =

IC1

UVLO
VCC

12

V(V)

VA =

SIMULATION RESULTS

I(A)

VBE 2 VBE1
R1

16

Thus the hysteretic range of the UVLO circuit is

From discussing above, we know that all of the mirror pairs

operate in saturation region when the collector current of Q1
equals with that of Q2. The voltage value of A is very pivotal at
this time. We assume VREF is the voltage of node A. The
collector currents of Q1 and Q2 are
I C1 = I C 2 =

R3 + R4 + R5
VREF
R4 + R5

15

It is even higher than VREF that make sure UVLO is stably

low. Similarly, we can get the turn-off voltage Voff as follows:

226

TABLE I.

THE VALUES OF

Von

AND

Voff

IV.

IN DIFFERENT TEMPERATURES

-40

25

80

140

Von (V)

8.83

9.12

9.16

Voff (V)

6.87

7.03

7.08

According to the necessary function of Under Voltage Lock

Out (UVLO) in the DC-DC power management systems, an
improved UVLO circuit is proposed elaborately. The
prominent advantages are having a small area and a simple
topology without an extra bandgap and the complex digital
logic. The results of Hspice simulation have shown it can
operate from -40 to 140 with a maximum error no more
than 2%. The designed circuit satisfies varied power
management chips because it can work in a wide range of
temperature without especial demands to the process.

TEMP=-40 C/UVLO
o
TEMP=25 C/UVLO
o
TEMP=80 C/UVLO
o
TEMP=140 C/UVLO
VCC

14
12

Voltage (V)

10

REFERENCES

[1]

6
4

[2]

[3]

0
0.0

2.0m

4.0m

6.0m

CONCLUSIONS

8.0m

Time (t)

[4]

Figure 5. The curves of the UVLO circuit output in typical temperatures

227

Lai Xinquan, Hu Juncai, Jia Ligang, Wang Hongyi, Design of

hysteretic comparator with bandgap structure, Proc of 5th Int conf on
ASIC, pp. 615-618, 2003.
Gray P R, Meyer R G, Hurst P J, Analysis and design of analog
integrated circuits, New York: John Whiley & Sons, Inc, 2001.
Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design,
Second Edition. New York, Oxford University, pp. 493-600, 2002
Behzad Razavi, Design of analog CMOS integrated circuits, Fairfield:
Quebecor Printing Company, 2001.