Lab Manual 3440

Electronics Laboratory II
EECS 3440
Lab Manual
January 2002
rev. 2
editor
Roger King, prof. EECS
ii
Foreword
This lab is a continuation of the lab experience included with the course Electronics I.
As such, it would be repetitious to include the sections describing the equipment, documenting
procedures, or reviewing SPICE. For the same reason, a comprehensive set of data sheets is not
included in this lab manual. (The PN2222A data sheet is included because of its frequent use.)
It is assumed that the student has retained a copy of the lab manual from the Electronics I
(EECS 3400) course.
The main new topics covered by this lab are frequency response and feedback in analog
electronic systems. These are fundamental for any practical electronics, and in addition, each of
these has a counterpart in the digital signal processing world. An understanding of the behavior
of the analog system is the best preparation for an understanding of the corresponding
digital-domain behavior. As with Electronics I, this lab will also emphasize the use of SPICE
along with hands-on experimentation to gain an intuitive understanding of the electronics
involved. The student is encouraged in each experiment to simulate the lab using SPICE, to
hand work a simplified analysis, and to compare these with the observed experimental behavior.
This lab is continually being redeveloped. Please give the instructor your feedback
concerning the lab experiments and procedures so that the future manuals can be as error-free as
possible.
Prof. Roger King, EECS

July 1998
iii
iv
Table of Contents
Experiment 1 SPICE Modeling the 741

Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Experiment 2 741 Op-Amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Experiment 3 SPICE Simulation of a JFET
Common-Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Experiment 4 JFET Common-Source
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Experiment 5 Small-Signal CC and CB
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Experiment 6 Bypass and Coupling Capacitor
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Experiment 7 BJT High-Frequency
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Experiment 8 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Experiment 9 Complementary-Symmetry
Push-Pull Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Experiment 10 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Experiment 11 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Experiment 12 Wien Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Experiment 13 Analog/Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
vi
Experiment 1
SPICE Modeling the 741 Op-Amp
Introduction
The purpose of this experiment is to gain experience with ac and transient SPICE
simulation procedures, and to learn about the slew rate and bandwidth behaviors of a typical
general-purpose op-amp. A simple model of the internal structure of the 741 op-amp will be
used.
Equipment Needed
v PC running a current version of
PSpice
v SPICE model for a 741

general-purpose op-amp
Procedure
Use PSpice to run an analysis of the circuit of Fig. 1. A model for the 741 op-amp is
given in Fig. 2. (The model in Fig. 2 is also available from the instructor on disk.) The actual
circuit requires two 15-V power supplies for the op-amp; the model in Fig. 2 works without
having to explicity show these power supplies. Most general purpose op-amps have two internal
stages of gain: the first one is modeled in Fig. 2 as the voltage-controlled current source
Gstage1, and the second one is modeled as the voltage-controlled voltage source Estage2.
1. Make the input source Vin a pulse voltage source (VPULSE) in series with a transient
sine source (VSIN). Set the ac component of VPULSE to 1 V, and its pulse component
to transition from -1 V to +1 V as a square wave with a period of 400 s (200 s at -1 V,
and 200 s at +1 V). Set up VSIN for an offset voltage of 0, an amplitude of 50 mV, and
a frequency of 40 kHz. The input voltage to the inverting amplifier will then be a 1-V ac
signal during the ac analysis (a steady-state phasor analysis), and it will be a 50-mV
40-kHz sine wave added to a 1-V 2.5-kHz square wave during the transient simulation.
2. Run an ac sweep from 0.1 Hz to 10 MHz, and a transient simulation for 500 s.
Fig. 1 Inverting amplifier using a 741 op-amp.

1

3. Use PROBE to view the results of the ac sweep. The input ac voltage Vin will have a
constant magnitude of 1 V (0 dB); display the dB magnitude of the output voltage Vout.
Determine the high-frequency cutoff of the inverting amplifier by finding the frequency
at which the output is reduced to 3 dB less than its low-frequency value.
4. Determine why the gain of the inverting amplifier is not constant up to a very high
frequency. Use PROBE to plot the gain of the op-amp itself by adding the plot
DB(Vout/-Vid) to the previous plot. Note that -Vid is the input voltage to the op-amp,
not the input voltage to the circuit. Print this composite plot of the inverting circuit gain
together with the op-amp gain for a frequency range of 0.1 Hz to 10 MHz.
5. Use PROBE to view the results of the transient run. Plot the output voltage Vout
together with -10 times the input voltage Vin. Ideally, these two traces should coincide.
However, there will be some notable discrepancies. Print this composite plot.
6. The output voltage will show evidence of slew rate limiting at the times that the square
wave transitions. During this time, the Vout rises or falls with a well-defined slope, and
the small sinusoidal component of signal disappears. To find out why, add an additional
Y-axis to the plot and add a trace of the output current leaving the first stage, I(Gstage1).
The vertical scale of this new Y-axis should be -15 A to +15 A, and there should be
evidence that the current output of stage 1 is clipping. Print this composite plot.
Report
There is no formal report for this lab. Simply record your findings and comments and
submit them in a homework format. In the following, be careful to distinguish the op-amp by
itself from the complete amplifier circuit of Fig. 1. Please answer the following questions:
Vout
1. What is the voltage gain Vin (in dB) of the circuit of Fig. 1?
2. The high-frequency cutoff fH is defined as the frequency at which the gain is down to
3 dB less than its low-frequency value. What is the value of fH for this amplifier?
Vout
3. What is the voltage gain of the op-amp itself Vid (in dB) at very low frequencies?
Describe the variation of the op-amp gain with respect to frequency. What is the value of
fH for the op-amp by itself?
4. Describe the behavior of this inverting amplifier when it is producing a 10-V

square-wave output voltage, especially with regard to the regions where Vout is in
transition. Why does the sine waveform disappear from the output waveform during the
transition times?
Fig. 2 Inverting amplifier with 741 op-amp model.
Table 1
Device Parameters for the Inverting Amplifier SPICE Model
VPULSE
VSIN
Gstage1
Estage2
D1 & D2
Input source for ac

steady state +
transient square
wave
Input source for

transient sine wave
Transconductance
amplifier (VCCS)
with saturation
Voltage amplifier
(VCVS) with
saturation
Generic diodes
(use Dbreak model)
DC=0
AC=0
VOFF=0
VAMPL=50mV
FREQ=40kHz
TABLE=
(-75mV,-15uA)
(+75mV,+15uA)
DC=0
AC=1V
V1=-1V
V2=+1V
TD=200us
TR=0
TF=0
PW=200us
PER=400us
TABLE=
(-50mV,-13V)
(+50mV,+13V)
Dbreak D(
IS=1E-14
CJO=0.1pF
RS=0.1)
Experiment 2
741 Op-Amp Circuits
Introduction
The purpose of this experiment is to gain experience with the '741 op-amp in several
typical applications, and to discover some of the basic limitations of all op-amps. The observed
behavior of the inverting amplifier will be compared with the simulated behavior from
Experiment 1.
Pre-Lab
It is expected that Experiment 1, "SPICE Modeling the '741 Op-Amp," has already been
performed.
Equipment Needed
v LM741/MC741/SN741 op-amp
(prefix indicates manufacturer)
v Power supplies, function

generator, oscilloscope
Procedure
1. Connect the circuit of Fig. 1. Use a 100-mV peak 1-kHz sine wave input voltage to
vo
measure the system voltage gain Av = vi . (The expected result is -10.) To reduce the
high-frequency noise on the scope channel handling the 100-mV signal, turn on its
bandwidth limit, found on the channel input menu.
2. Measure the high-frequency cutoff (fH) of Fig. 1 using a 100-mV sine wave input and
monitoring the output voltage. Starting at 1 kHz, increase the frequency of v i until the
output v o has decreased to 70.7% of its 1-kHz value. Record this -3 dB frequency as fH .
(The expected value of fH is about 90 kHz.)
3. Collect two output voltage waveforms from Fig. 1 and display them simultaneously using
the memory capability of the DSO. Focus on the rising edge of the square wave
response. Display and record:
a) The response to a 50-mV peak 1-kHz square wave. Measure the slope of the rising
edge of the response using a horizontal scale of 0.5 s/div, and a vertical scale of
0.2 V/div.
b) The response to a 500-mV peak 1-kHz square wave. Measure the slope of the rising
edge of the response using a horizontal scale of 5 s/div, and a vertical scale of 2 V/div.
4. Measure the slew rate (SR) capability of the '741 op-amp from the recorded response of
(b) above. (The expected value of SR is about 0.5 V/s.) Try increasing the amplitude
5
741 Op-Amp Circuits

of the input square wave. Can the output voltage attain a rate-of-change any greater than
your measured slew rate?
5. Connect Fig. 2. Measure the voltage gain of Fig. 2 using a low amplitude 1-kHz sine
wave. (The expected result is +11.)
6. Connect Fig. 3 and display the input and output voltage waveforms together, using a
0.5-V peak 1-kHz square wave for v i . Does the output appear to satisfy the following
transfer function?
vo =
1
RiCf
0t vi(t) dt + vo(0)
7. Record this square wave input with its triangle wave response. Record the input/response
pair for a 1-kHz sine wave.
Report
1. Compare the 1-kHz voltage gains measured for Figs. 1 and 2 with those predicted by
ideal op-amp equations.
2. Compare the high-frequency cutoff measured for Fig. 1 with that predicted by the SPICE
simulation in Experiment 1. Use the SPICE model for the '741 op-amp to explain why
the circuit gain decreases at frequencies above fH .
3. Compare the slew rate measured for Fig. 1 with that predicted by the SPICE simulation
in Experiment 1. Does increasing the input voltage amplitude beyond 1 V increase the
slew rate observed at the output? Why?
4. Do the integrator responses observed in steps 6 and 7 agree with the equation given for
an ideal op-amp? Compare the shapes and amplitudes of the predicted and observed
responses to square wave and sine wave inputs.
741 Op-Amp Circuits
Fig. 1 Inverting amplifier, 8-pin dual-in-line plastic package (top view).
Fig. 2 Non-inverting amplifier.
Fig. 3 Integrator.
741 Op-Amp Circuits
Experiment 3
SPICE Simulation of a JFET Common-Source Amplifier
Introduction
The purpose of this experiment is to gain practical experience with the mechanics of the
SPICE simulations for bias point and ac analysis. The circuit used is a JFET common-source
amplifier.
Pre-Lab
There is no pre-lab for this experiment.
Equipment Needed
v Current version of PSpice
Procedure
Turn on the PC and open the current version of PSpice. Enter the circuit of Fig. 1 using
the library model for the 2N5457 JFET. The signal source Vin should be an ac source, set to an
amplitude of 1 V, and with its dc component set to 0 V.
1. Set up the simulation for a detailed bias point solution, a dc sweep, and an ac sweep. The
bias point solution will consist of a detailed listing of the operating-point solution in the
output file, along with calculated incremental model parameters for the JFET. Set the dc
sweep to step the dc value of source Vin from -5 V to +5 V in 0.1-V steps. Set the ac
sweep to step the frequency of the ac content of Vin from 1 Hz to 100 kHz in 101 steps
Fig. 1 JFET common-source amplifier.

9
SPICE Simulation of a JFET Common-Source Amplifier

per decade.
2. After running the simulation, examine the output file to find the bias point solution. The
JFET drain-source voltage (VDS) must be more than 2 V, and the drain current (ID) must
be more than 0.1 mA. If the bias point does not represent a reasonable operating point
for an amplifier, there is no point in proceeding further - something has gone wrong in
the entry of the schematic, or the design of the circuit. Note: Later versions of SPICE
allow you to enable direct display of the bias point solution on the schematic diagram.
Record ID and VDS .
3. Use probe to display the dc sweep results. Plot the output voltage Vo vs. the input
voltage Vin. Use the add trace menu to add a plot of the derivative of Vo [the syntax is
D(V(Vo))]. Record these traces.
4. Use probe to display the ac sweep results. Plot the dB equivalent of the output voltage
Vo vs. frequency. (Vin should be 0 dB at all frequencies.) Record this trace.
Report
No formal report is required for this experiment. Simply summarize the results you have
obtained in a homework format. Briefly answer the following questions:
1. Discuss the location of the optimum Q-point for this amplifier using the plot of Vo vs.
Vin obtained from the dc sweep. Use the plot of the derivative of Vo to estimate the gain
at this Q-point. At what values of Vo (upper and lower) will the amplifier saturate?
2. Discuss the voltage gain of the amplifier as measured at various frequencies. Why does
the voltage gain vary with frequency?
3. For what range of frequencies does the voltage gain read from the ac sweep agree with
the incremental voltage gain read from the dc sweep? Why?
Notes on SPICE
SPICE computes the bias point analysis by setting all ac and transient components of all
sources to zero, and considering only the dc components of these sources. The dc sweep is
computed by stepping the dc component of the source specified in the dc sweep setup statement.
During dc analyses, capacitors are open circuits; and inductors are short circuits.
When SPICE does an ac sweep, it first uses the dc source values to compute the dc bias
point solution. It then computes incremental models for all devices in the circuit based upon the
bias point. After this, SPICE applies an ac steady-state analysis to the incremental equivalent
circuit over the frequency range given in the setup. The ac amplitude of the source Vin can be
set to any convenient value without causing amplifier saturation because the incremental model
is always a linear model.
10
Experiment 4
JFET Common-Source Amplifier
Introduction
The purpose of this experiment is to investigate the performance of a JFET
common-source amplifier.
Equipment Needed
v Normal laboratory equipment
v 2N5457 n-channel JFET
v For alternate VP and IDSS , you

may substitute 2N5458/59
Pre-Lab
Estimated typical values of the JFET parameters are: VP = -2.5 V and IDSS = 3 mA.
Obtain a 2N5457 data sheet and find out what the allowable ranges of these parameters are.
Read the text file of the 2N5457 SPICE model currently used in this department and determine
what values the model assumes for these parameters.
Procedure
1. Obtain the FET drain characteristics using the curve tracer. Measure the pinchoff voltage
VP and the zero-bias drain current IDSS. Make sure these lie within the ranges promised
on the 2N5457 data sheet. Record the measured values of these two parameters, but you
do not need to record the drain characteristics.
2. Connect the circuit of Fig. 1 without C1 and measure its quiescent operating point (IDQ
and VGSQ).
3. Set the function generator for a 5-kHz sine wave with zero dc offset. Increase the FG
voltage level until the output voltage V o is on the verge of clipping-type distortion.
Record the output waveform, showing evidence of the voltage levels at which clipping
will occur.
4. Reduce the signal level to assure an undistorted output. Measure and record the voltage
gain Av
gain.
Vo
Vi at 5 kHz. Place C1 into the circuit and record its effect on the voltage
5. With C1 in the circuit, measure and record the amplitude and phase of the output voltage
(relative to the input voltage) at the following frequencies: 5 kHz, 500 Hz, 50 Hz.
11

Report
1. Use the measured values of VP and IDSS to predict the Q-point (IDQ and VGSQ). Compare
these values with the experimentally-measured values. Compare these values with the
prediction of a SPICE bias point solution using the 2N5457 model.
2. Use the measured values of VP and IDSS to estimate the transconductance (gm). Calculate
the midband voltage gain (the 5-kHz gain) with and without C1, and compare with the
experimentally-measured values. Also, compare the measured 5-kHz gain with the result
of a SPICE ac analysis.
3. Estimate the maximum possible output voltage before the onset of severe distortion.
Consider clipping due to the drain current going to zero, and distortion due to the JFET
entering its ohmic region of operation. Compare these estimates with your observed data.
4. Comment on the observed frequency response data. What happens to the signal as its
frequency is lowered below midband? Why? Compare these experimental results with
the results of a SPICE ac frequency sweep.
Background
Refer to your electronics text for background on modeling the JFET. For the purpose of
this experiment, it is OK to ignore channel-length modulation in modeling the JFET. Be aware
that various electronics books may present the following equations using different symbols.
v
iD = IDSS 1 VGSP
and
iD
gm = vGS
Q point
=
=
2IDSS
VP
2
VP
VGS
VP
IDSS $ ID
where
IDSS = zero-gate-voltage drain current, and
VP = pinchoff voltage.
The equations above are valid only in the constant-current (saturation, or pinch-off) region.
12
Fig. 1 JFET common-source amplifier.
Fig. 2 2N5457 case and pin-outs.
13
14
Experiment 5
Small-Signal CC and CB Amplifiers
Introduction
The purpose of this experiment is the measurement of the small-signal voltage gain, input
resistance, and output resistance of a common-collector (emitter follower) and a common-base
amplifier. These two circuits are then compared to each other.
Equipment Needed
v PN2222A npn transistor
Procedure
Connect the circuit of Fig. 1 and measure its quiescent operating point (ICQ and VCEQ).
Connect a 5-kHz sine wave signal source to the input terminals, and a 100- load resistor to the
output. Measure the following small-signal amplifier parameters using a signal level low enough
to avoid clipping, yet high enough to be measurable.
1. Measure the voltage gain Av =
Vo
Vi
2. Measure the input resistance Ri .
3. Measure the output resistance Ro .

Connect the circuit of Fig. 2 and measure its quiescent operating point (ICQ and VCEQ).
Connect a 5-kHz sine wave signal source to the input terminals, and a 10-k load resistor to the
output. Measure the same small-signal amplifier parameters as previously. Remember to keep
the signal level small enough to avoid any visible distortion of the sinusoidal waveforms.
1. Measure the voltage gain Av =
Vo
Vi
2. Measure the input resistance Ri .
3. Measure the output resistance Ro .

Use the curve tracer to measure the incremental current gain (ac = hfe) of your transistor
in the neighborhood of IC = 1 mA, VCE = 10 V.
15
Report
1. Using reasonable approximations, predict the Q-point of Figs. 1 and 2, assuming that
dc = 150. Compare this with the experimentally measured Q-point.
2. Using the values of ac (hfe) and Q-point which were measured experimentally, predict the
following: A v , Ri , Ri , R o , and Ro for Figs. 1 and 2.

3. Compare these calculated values with the experimentally-determined values. Compare
the relative values of A v , Ri , and R o for Figs. 1 and 2. Based on simplified formulas,
give the most important factor(s) which determine A v , Ri , and R o for Figs. 1 and 2.
16
Fig. 1 Common-collector (emitter follower) amplifier.
Fig. 2. Common-base amplifier.
Fig. 3 PN2222A package

and pin-out.
17

Appendix: The Experimental Determination of Voltage Gains and Incremental Resistances
1. Voltage gain is measured with a specified load resistor in place by monitoring Vi and V o
with a two-channel scope. The smallest measurable level is used; the measurement is
only valid if no appreciable distortion occurs in either Vi or V o .
2. Input resistance Ri can be measured by monitoring V o while driving the amplifier from a
source having a known source resistance (RS). Then, using a variable resistor in series
with the source, the source resistance is increased until V o drops to one-half its previous
value. We have:
3. Vo1 = Av Vs
Vo2 = Av Vs
Ri
(first measurement), and
Ri + Rs
(1)
Ri
Ri + Rs + Rpot
(second measurement)
(2)
4. Therefore:
Vo1
Vo2
1
2
Ri + Rs
(3)
Ri + Rs + Rpot
Ri = Rpot Rs
(4)
5. The input resistance Ri is calculated from the measured value of the variable resistor
(R pot ) and the value of the source resistance (R s ). For the FG in the electronics lab,
R s = 50 . This measurement is only valid for small (undistorted) signals. Ri is easily
calculated from Ri .
6. Output resistance Ro is measured by monitoring V o while driving the amplifier with a

signal source having the specified source resistance R s ; V o is first measured, and then a
variable resistor is paralleled with the output terminals and adjusted so that V o is one-half
its previous value. The resistance of the potentiometer is then equal to the output
resistance Ro . This measurement is only valid for small signals. R o is easily calculated
from Ro .
18
Experiment 6
Bypass and Coupling Capacitor Effects
Introduction
The purpose of this experiment is the measurement of the low-frequency response of an
ac-coupled amplifier.
Equipment Needed
v Switchable 0-dB/40-dB 50-

attenuator
Pre-Lab
Calculate the expected locations of the poles and zeros contributed by each capacitor in
Fig. 1 (they each act independently). Calculate the midband gain, and sketch a Bode plot of the
expected magnitude of the voltage gain from 1 Hz to 10 kHz.
Procedure
Gain will be measured over a wide range of values in this experiment: The amplitude of
the input signal may need to be changed in order to maintain a measurable output level, but at all
times keep the levels low enough to avoid appreciable distortion, yet high enough to be
measurable. You will need to use a switchable 0-dB/40-dB 50- attenuator at the FG output to
do this. Turn on the bandwidth limiters in both channels of the scope to reduce any
high-frequency noise present in low-level signals.
Fig. 1 Common-emitter amplifier with blocking and bypass capacitors.

19

1. Connect the circuit of Fig. 1 and measure its operating point (I C and VCE). Note that the
function generator (FG) must be connected to provide a dc path for the base current.
Make sure that the operating point is reasonable for operation as an amplifier.
2. Set the FG to produce a 7-mV rms 10-kHz sine wave at Vi and measure the midband
gain at 10 kHz. (Expected value is about +40 dB.) Make sure that both scope channels
are dc-coupled throughout this procedure. An ac-coupled scope channel is itself a
high-pass filter.
3. Measure the gain magnitude (in dB) over the frequency range of 10 Hz to 10 kHz. Mark
the data points on your predicted frequency response plot. If there is a deviation of more
than 6 dB, you should investigate the reason for the discrepancy. Use the 2-channel
scope to measure the peak-to-peak values of Vi and Vo for the purpose of measuring gain.
Details Lower the frequency by steps in a 10-4-2-1 sequence (e.g., 1 kHz - 400 Hz 200 Hz - 100 Hz), taking gain magnitude measurements at each step. You may need to
increase the input signal level at lower frequencies to maintain a measurable output
signal. Take data from 10 kHz down to 100 Hz. Continue going down in frequency
towards 10 Hz as far as meaningful data can be obtained. Use "averaging1" (found in the
scope Display menu) to reduce the amount of noise on small signals.
4. Divide the midband gain measured in part 1 by 1.414 (this is equivalent to subtracting
3 dB from its decibel value). Use the FG to experimentally measure the frequency at
which the amplifier's gain is 3 dB below its midband value. This is called the
"low-frequency cutoff."
Report
1. Bode plot the pre-lab calculated frequency response on 4-cycle semi-log paper. Use dB
notation, and use a frequency range of 1 Hz to 10 kHz.
2. Mark the experimental data points on this graph. Do they agree well with the predicted
values?
3. Identify the midband gain from the experimental data, and from the calculated response.
How do they compare?
4. Identify the low-frequency cutoff (fL) from the experimental data, and from the calculated
response. How do they compare?
1
"Averaging" is the process of storing repeated acquisitions of the waveform, each one based on the trigger
event, and point-by-point averaging these stored waveforms to produce the display. Averaging only works if there
is a stable trigger event.
20

Bode Plots
The actual gain vs. frequency plot of an ac-coupled amplifier is a smooth curve.
However, Bode pointed out that if semi-log paper is used, a series of straight-line asymptotic
approximations to the gain curve will be close enough for many engineering purposes. The gain
magnitude in dB is placed on the linear scale; the frequency is placed on the log scale. Fig. 2
below shows sample Bode plots of the contribution of the emitter bypass C1 acting alone (upper
figure), and the collector blocking capacitor C2 acting alone (lower figure).
Fig. 2 Bode plot of frequency response of C1 alone (upper figure); and C2 alone (lower figure)
21
22
Experiment 7
BJT High-Frequency Performance
Introduction
The purpose of this experiment is the investigation of the high-frequency performance of
a BJT common-emitter amplifier. The transistor junction capacitances C and C will be
estimated from typical data sheet information.
Equipment Needed
Pre-Lab
Study the appendix to this lab which shows how to estimate the transistor junction
capacitances on the basis of the limited information typically given on a data sheet.
Procedure
The circuit of Fig. 1 may not maintain a stable dc operating point; therefore, you should
verify at several stages during the experiment that the operating point is still 5 mA/5 V (IC/VCE).
The collector current is controlled by adjusting VBB , and the collector-emitter voltage is then set
by adjusting VCC . Be sure to remove the dc voltmeter or milliameter from the circuit when
making the actual gain measurements. Gain will be measured from midband (5 kHz) to beyond
the high-frequency cutoff fH (1 MHz).
Fig. 1 Common-emitter amplifier.

23
1. Connect Fig. 1 using a 1 K load resistor (RL). Set the dc operating point and remove all
Vo
dc meters from the circuit. Measure the midband gain factor V i at 5 kHz using a small
signal. Measure the transistor base-emitter resistance at 5 kHz by measuring the ac
signal at each end of R1.
2. Take gain measurements from 5 kHz to 1 MHz. The objective is to accurately determine
the high-frequency cutoff (fH). Take enough data points to be sure of the value of the
midband gain, and the frequency at which the gain is reduced to 70.7% of its midband
value. (Expected midband gain and hf cutoff are about -100 and 400 kHz.)
3. Change the load resistor (RL) to 560 . Readjust the dc operating point to maintain
5 mA/5 V. Measure the midband gain and the high-frequency cutoff again. (The
expected values are now 56% and 179% of the previous measurements, respectively.)
Report
1. Obtain a copy of the transistor data sheet for type 2N2222A or PN2222A, and put it in an
appendix to your report. Use the data sheet to estimate values for C and C .
2. Calculate the midband gain and high-frequency cutoff for each of the two values of load
resistance used. Compare these results with the experimental data.
3. Use SPICE to simulate the frequency response of the experimental circuit. Compare the
midband gain and high-frequency cutoff predicted by SPICE with your calculated and
observed data. After running your simulation successfully, open the *.OUT file and read
the values for C and C that were produced by SPICE. Compare these with your
estimated values.
24

Appendix A - Estimating C and C From a Data Sheet
The capacitance associated with a pn junction has two components: the transition
capacitance, which is a nonlinear function of the junction voltage; and the diffusion capacitance,
which is directly proportional to the junction forward current.
In the active mode, the collector-base junction is reverse-biased, and therefore it has only
transition capacitance, whose value is determined by the dc collector-base voltage. This
capacitance is denoted Cbc , C , Cob or "output capacitance" on most data sheets. A complete
data sheet will typically contain a graph of C vs. collector-base reverse voltage. An abbreviated
data sheet will at least give a single value for C . Note that the transition capacitance increases
with decreasing reverse-bias, reaching its maximum value at zero bias.
In the active mode, the emitter-base capacitance is composed of both transition and
diffusion components. The transition component is generally small and independent of operating
point (VBE is almost constant at 0.7 V); the diffusion component is generally large and directly
proportional to emitter current. The foregoing is true when the transistor is used at normal
current densities: In a large transistor used at low current, C will not be zero; it will approach a
lower limit equal to its transition capacitance. The transition component of C can be estimated
from the data sheet as the zero-voltage limiting value of the reverse-biased emitter-base
capacitance. The diffusion component of C is directly proportional to IE , and is never directly
given on the data sheet.
The short-circuit unity-current-gain frequency (denoted fT and frequently called the
current gain-bandwidth product, or GBW) is normally found on the data sheet. It can be shown
that this is related to the junction capacitances by:
2f T =
gm
C + C
If the proposed operating point current (IE ) is within one decade of the operating point used in
making the data sheet measurement, it may be assumed that fT does not change and the
computation of C is straightforward. If the proposed IE is small, model C by the following:
C = X0 + X1 $ IE
X0 is the zero-bias limiting value of the transition capacitance, and X1 is readily calculated from
the given GBW data together with the operating point used to measure it. This equation is then
used to estimate C at the proposed operating point.
As an example, capacitances are estimated from the data sheet for a National
Semiconductor PN2222A. A graph labeled "Emitter Transition and Output Capacitance vs.
Reverse Bias Voltages" directly states that C is typically 4.5 pF at VCB = 4.3 V. From the same
graph, X0 = 21 pF. Under the small-signal characteristics, it is stated that fT is at least 300 MHz
at IC = 20 mA. From this data, X1 = 20 pF/mA. Therefore, C is expected to be 121 pF at 5 mA.
25

An alternative calculation, which simply assumes that fT is the same at 5 mA as at 20 mA,
produces C = 102 pF. Either is justifiable given the precision of the available data.
Appendix B - SPICE Simulation of the CE Amplifier

The CE amplifier of Fig. 1 can be easily entered into SPICE and simulated using a
2N2222A transistor model. The problem that will immediately arise is that the dc operating
point in the simulation will not be the same as that in the lab. The gain and bandwidth results are
strongly operating-point dependent, and therefore will not match the lab results at all. The newer
versions of PSpice allow the direct display of the calculated operating point on the schematic:
Enable this option and verify that the correct operating point has been achieved before looking at
the frequency response data in probe.
With the direct display of the bias point solution, it is not difficult to iteratively adjust
VBB to obtain IC = 5 mA, and then adjust VCC to obtain VCE = 5 V. This process is speeded if all
other analyses except for bias point are disabled during this iterative procedure.
26
Experiment 8
Differential Amplifiers
Introduction
The purpose of this experiment is to investigate several key features of the balanced
differential pair and the wide band (asymmetrical) differential pair.
Equipment Needed
v two PN2222A npn transistors
v Scope probe having known input

capacitance
Pre-Lab
Assuming that the transistors will have a dc current gain ( or hFE) equal to 100, predict
the Q-points of Figs. 1 and 2. Estimate the differential gain (Ad) and the common-mode gain
(Acm) for Fig. 1. In each case, the output is taken at Q2's collector.
Procedure
1. Connect the circuit of Fig. 1 and verify that a reasonable Q-point is obtained. Remember
that the amplifier is not properly biased unless a dc current path is provided from each
transistor base to the ground. Substitute transistors until the collector currents of Q1 and
Q2 match to within 10 A of each other. Use the curve tracer to measure the ac current
gain (O or hfe) in the vicinity of the Q-point for each transistor.
2. Use the signal connections shown in solid lines in Fig. 1 to measure the differential-mode
Vo
gain ( Ad = Vs ) of the symmetric differential pair. Note that the output is taken
single-endedly (from one collector only). This is a midband, small-signal measurement;
use 400 Hz and a signal level low enough that there is no appreciable distortion in the
output sine wave. Use an attenuator as needed to reduce the output of the function
generator (FG). (The expected value is about 85.)
3. Measure the high-frequency cutoff fH of the symmetrical differential amplifier of Fig. 1.
Note that the input capacitance of the scope probe 1 is a part of the high-frequency model
of the circuit. (The expected value is about 27 kHz.)
4. Use the signal connections shown in broken lines in Fig. 1 to measure the common-mode
Vo
gain ( A cm = V cm ) of the symmetric differential pair. Use 400 Hz and a low signal level
so that there is no appreciable distortion in the input or output waveforms. (The expected
value is about -0.3.)
For the HP 10071A probe, the input capacitance is 16 pF.
27
5. Connect the asymmetric differential pair of Fig. 2 and verify that a reasonable Q-point is
obtained. (VCB for Q2 should be between 10 and 18 V.)
6. Measure the gain ( Ad = Vs ) and the high-frequency cutoff of the asymmetric
differential pair of Fig. 2. Note that the input capacitance of the scope probe is also an
important part of the high-frequency model of this circuit. (The expected values are
about 85 and 80 kHz, respectively.)
Vo
Report
1. From the transistor data sheet, estimate the values of collector-base and emitter-base
capacitance at the Q-point. Hint: at the current level used here, C will be dominated by
its transition component.
2. Calculate the theoretical values of Ad , Acm and fH for Figs. 1 and 2, and compare with the
experimental results. (For Fig. 1, use Miller's Theorem and model the symmetrical
differential amplifier as equivalent to a common-emitter stage.)
3. Use SPICE (with a 2N2222A model) to simulate this circuit, and compare these results
with the experimental and calculated results.
4. Compare the gains and cutoff frequencies of Figs. 1 and 2. Compute a gain-bandwidth
product for each.
28
Fig. 1 Symmetrical differential pair. The load capacitance is the scope probe capacitance.
Fig. 2 Asymmetrical differential pair. The load capacitance is the scope probe capacitance.
Fig. 3 PN2222A
package and pin-out.
29
30
Experiment 9
Complementary-Symmetry Push-Pull Amplifier
Introduction
The purpose of this experiment is to observe the operation of a class-B
complementary-symmetry amplifier and the use of negative feedback to improve its behavior.
Equipment Needed
v Complementary-symmetry
output stage circuit board
v Load resistor (about 12 , 5 W)
Procedure
Connect the circuit of Fig. 1 using a complementary-symmetry output stage circuit board.
Fig. 3 gives a top view (component side) of this circuit board to identify the correct connection
points. Note that both Figs. 1 and 2 show only a simplified equivalent of the circuit board
schematic: The details of the circuit board are shown in Fig. 3. In making connections, bring
all ground leads separately back to the "COM" binding post on the circuit board (including the
function generator and scope ground leads). This is known as a "star" grounding arrangement.
1. Use the function generator (FG) to apply a 10-V peak 100-Hz triangle wave as shown in
Fig. 1. Connect the two scope channels as indicated. Display and record the input
(Chan. 1) and output (Chan. 2) waveforms. Note carefully the defect in the output
waveform around its zero crossings. This is known as "crossover" distortion.
2. Display and record an X-Y plot of output vs. input on the scope. (Look on the horizontal
"Main/Delayed" menu.) Be sure that both channels are set for zero offset and 2 V/div
before switching to the X-Y mode. This is the transfer function of the basic
complementary-symmetry output stage.
3. Obtain a type '741 op-amp and connect Fig. 2, placing the op-amp on a proto-board. It is
best to run separate jumper wires from each op-amp terminal to the corresponding
terminals on the output stage circuit board. Make all power supply connections (+15 V,
-15 V and COM) to the circuit board, not to the proto-board. Set the FG for 10 V peak at
100 Hz as before.
4. Display and record the input from the FG (Chan. 1) and the output (Chan. 2) waveforms.
Note the suppression of the crossover distortion by the negative feedback.
5. Display and record an X-Y plot of output vs. input as before. Use identical vertical
settings of 2 V/div and zero offset on both channels.
31

6. Investigate how the negative feedback functions to suppress the crossover distortion.
Move the scope channel 1 to the two transistor bases (B1 and B2) on the circuit board.
Switch the scope back to voltage vs. time. Display and record the input and output of the
complementary-symmetry stage itself. Note the inverse crossover distortion at the input
to the complementary-symmetry stage.
7. Maintain these two waveforms on the scope while increasing the FG frequency to
10 kHz. Note the decreasing ability of the feedback to cancel the crossover distortion at
high frequency. Record these waveforms.
Report
1. Explain the cause of the crossover distortion observed in steps 1 and 2. (Most electronics
texts have a good discussion of this problem in a chapter on "power amplifiers" or
"output stages.")
2. Analyze the circuit in Fig. 2 based upon the assumption of an ideal op-amp. (Assume
that the voltages on pins 2 and 3 of the '741 must be exactly equal because of its infinite
gain.) How does this suppress the distortion? Use the waveforms gathered in steps 4 and
5 to support your discussion.
3. Why is the distortion reduction in step 7 (at 10 kHz) not so good as it was at 100 Hz?
Explain this in terms of a specific imperfection in all practical op-amps, as opposed to an
ideal op-amp.
32
Fig. 1 Simplified diagram of the complementary-symmetry output stage.
Fig. 2 Complementary-symmetry amplifier with negative feedback.
Fig. 3 Pictorial top view and detailed schematic of the complementary-symmetry output stage.
33
Fig. 4 '741 pinout, top view.
34
Experiment 10
Negative Feedback
Introduction
The purpose of this experiment is to investigate the effects of shunt-shunt negative
feedback on the gain, input resistance and output resistance of a transresistance amplifier.
Equipment Needed
Procedure
Connect the circuit of Fig. 1. Verify that the Q-point is approximately 1 mA. All ac
measurements will be at midband (5 kHz) and small signal (no appreciable distortion).
1. Measure the closed-loop voltage gain Av =
Vo
Vs
2. Measure the input resistance indicated on Fig. 1, Rif . This may be done by measuring
the ac voltages VS and VSJ using the scope. Verify that these two voltages are in-phase.
Compute the current in RS, and then find

60 .)
Rif =
VSJ
IRS . (The expected value is about
3. Measure the output resistance indicated on Fig. 1, Rof . Fig. 2 shows how to do this:
Remove the function generator (FG), but keep its source resistance R S in place as
indicated. Connect the FG at the output terminal with a 100-K series resistor (R5). Set
the FG for a 10-V peak 5-kHz sine wave output and measure voltages V1 and V2.
V1
Compute the current in R5, and then find Rof = IR5 . (The expected value is about
370 .)
4. Connect the circuit of Fig. 3. This is the amplifier with the feedback removed, but the
loading effects of the feedback resistor Rf retained. Verify that the Q-point is the same as
previously, approximately 1 mA.
5. Measure the voltage gain Av = Vs , input resistance Ri , and output resistance Ro using
the same techniques as previously. (The expected values are -150, 3.2 K and, 5 K
respectively.)
Vo
35
Negative Feedback
Report
1. Use feedback theory to calculate the gain Av =
Vo
Vs
, input resistance Rif , and output
resistance Rof for Fig. 1. Be sure to note that the gain factor A v is not the one directly
A
stabilized by the feedback or given by the equation 1+A .
2. Use SPICE simulation to predict the gain and input/output resistances of Fig. 1.
3. Compare the results predicted by SPICE and by calculation to your experimental data.
Background - Measuring Input/Output Resistances in a Feedback System

There are two general cautions to observe in analyzing a feedback system: The quantity
which you are computing may not be the same as the one actually stabilized by the feedback; and
everything (all gains and resistances) pertaining to the feedback amplifier is affected by the loop
gain. The first caution applies to this lab in that the voltage gain of Fig. 1 is not directly
stabilized by the feedback. Fig. 1 is a transresistance amplifier: Its current-to-voltage
conversion factor is stabilized by the feedback. The best way to calculate the voltage gain of
Fig. 1 is to compute the transresistance first, and then convert it into the voltage gain.
The second caution affects the resistance measuring procedure used in this lab. The
"ohmmeter" applied to the circuit must not alter the loop gain of the amplifier. (This caution
must also be remembered in devising a SPICE-based procedure for determining the input and
output resistances as well.) When measuring the input resistance Rif , the source resistance RS
provides a convenient way of measuring the input current; however, changing the value of R S
from that given will alter the measured value of Rif because it would alter the loop gain. The
function generator (FG) is connected in series with a 1-K resistor which is considered the
source resistance. It is reasonably accurate to neglect the internal 50 resistance of the FG.
Similarly, the measuring apparatus in Fig. 2 (the FG with R5) alters the loop gain, and
thus produces an erroneous value of Rof . In this case, R5 is chosen to be much greater than the
open loop value of the output resistance so that it will only change the open loop gain by a small
amount and produce a reasonably accurate measurement.
36
Negative Feedback
Fig. 1 Amplifier with shunt-shunt feedback.
Fig. 2 Measuring the output resistance.
Fig. 3 Amplifier with feedback removed, but loading effects retained.

37
Negative Feedback
38
Experiment 11
Voltage Regulators
Introduction
The purpose of this experiment is to investigate the performance characteristics of two
simple voltage regulators.
Equipment Needed
v MJE 371 pnp power transistor
v 1N754 6.8-V Zener diode

(alternates: 1N4736 or 1N5235)
v Resistor decade box
Pre-Lab
Complete the design of the Zener diode shunt regulator in Fig. 1 (determine the largest
5% standard value which can be used for R1). It must operate satisfactorily over a load current
range of 0 to 10 mA using a supply voltage of 12 V. The output voltage is expected to have a
nominal value of 6.8 V.
Procedure
The 12-V supply in the following procedure is a laboratory supply capable of 200 mA of
output current. Be sure to set its current limiter for at least this amount.
1. Set up the circuit of Fig. 1 using the standard value that you calculated for R1 in the
pre-lab. Use a resistor decade box as the "load resistor" RLOAD. Insert a milliammeter as
shown to monitor the load current. Measure the load voltage at light-load (ILOAD = 1 mA),
and at full-load (ILOAD = 10 mA).
2. Measure the output voltage/current pairs with various values of load resistance. Use
output currents ranging from zero to well beyond the point where the regulator "drops out
of regulation." Collect enough data to sketch a map of the regulator performance on the
VLOAD vs. ILOAD plane (put VLOAD on the vertical axis, and ILOAD on the horizontal). The
expected result is that the regulator will maintain the output voltage almost-constant with
regard to load current up to the "dropout current:" the output voltage will then fall
rapidly with further increase in load current.
3. Set up the circuit of Fig. 2 and adjust it for an output voltage of 5.0 V at no-load.
Measure the output voltage and current with load resistors of 500 and 50 .
4. Operate the voltage regulator for several minutes with a 50- load and feel Q2. (Is it
getting warm?)
39
Voltage Regulators
Report
1. Include and discuss your design calculations for the Zener diode voltage regulator of
Fig. 1.
2. Describe the range of output current over which Fig. 1 operates satisfactorily. Why does
it "drop out of regulation?"
3. Find the experimentally-measured dynamic output resistance of each regulator in the
following manner:
ROUT =
VLOAD
ILOAD
VLOAD,1 VLOAD,2
ILOAD,1 ILOAD,2
4. Use PSpice to estimate the output resistance of Figs. 1 and 2. Use ac simulation and
measure the resistance at midband (about 1 kHz). Include a 680- load resistor in Fig. 1,
and a 50 load resistor in Fig. 2. Model Z1 using a 1N750-series Zener diode, but edit
the breakdown voltage parameter to: (BV=6.8V). Model Q2 with a transistor having its
SPICE parameters set to: (IS=1E-14 BF=100 VAF=50V). Compare the SPICE results
with the experimentally-measured output resistances.
5. Use PSpice to determine the range of output current over which Fig. 2 operates
satisfactorily. Put a dc current source in place of the load resistor, and use a dc sweep to
plot the load voltage vs. the load current. (Truncate any data beyond the point at which
the load voltage is reduced to zero.) What is the maximum useful load current according
to this simulation? Calculate the power dissipation in Q2, and its junction temperature
for this amount of load current.
Background - Zener Shunt Regulator

The Zener diode shunt regulator is treated in detail by most electronics texts. For the
purposes of the pre lab design, it is sufficient to treat the diode as an ideal 6.8-V Zener. The
design problem is to pick R1 such that some amount of reverse current will flow in the Zener
diode under all normal load conditions. Here, worst case is at maximum load current. A
calculation at maximum load current produces the maximum feasible value for R1, which then
must be rounded downward to the nearest available standard value. The student version of
PSpice includes a 1N750-series Zener diode model - if it is not the one you need, modify the
library model to include "BV = 6.8." (This sets the reverse breakdown voltage of the diode.)
Background - Series-Pass Voltage Regulator
The voltage regulator in Fig. 2 is an application of series-shunt negative feedback.
Resistors R5 and R4, together with Z1, form an adjustable "input voltage" to a voltage amplifier
programmed for a gain of +1. The load is the external circuitry to which the voltage regulator is
40
Voltage Regulators
Fig. 1 Zener diode shunt regulator. Calculate the maximum

standard value which can be used for R1.
Fig. 2 Adjustable voltage regulator.
MJE 371
Fig. 3 Transistor package outlines.

41
Voltage Regulators
feeding power. (Nowadays, almost all electronic circuitry is fed from a voltage-regulated power
supply.) Note that the +12-V supply is the energy source which runs the whole system; it is not
usually a regulated source. One of the key specifications of a voltage regulator is its dynamic
output resistance, which indicates its ability to maintain a constant output voltage even as the
load current varies. This can be predicted theoretically by the same methods used to calculate
the output resistance of any shunt-sensing feedback amplifier.
Transistor Q2 is called a "series-pass transistor." This is because the main load current is
carried by Q2; the collector-emitter voltage drop on Q2 is equal to the difference between the
supply voltage (+12 V) and the load voltage. In general, Q2 dissipates a lot of heat, and thus
gets hot. The junction temperature of Q2 may be estimated by using a simplified heat-flow
model which makes the temperature drop between two locations directly proportional to the
amount of heat flowing from one to the other. (Note the analogy to Ohm's law.) For the
MJE 371, which is in a TO 225 package, mounted in free air, the "thermal resistance" between
the junction and the ambient air is approximately 83 C/W. The maximum safe junction
temperature for the long-term survival of this semiconductor is rated by the manufacturer at
150 C. The heat dissipated in the junction is calculated by P DISS = V CE $ I C (watts).
Therefore, assuming a laboratory ambient temperature of 25 C, the junction temperature is
estimated by: T J = P DISS $ (83 C/W ) + 25 C . The junction temperature of Q2 defines the
maximum load current that this regulator can safely deliver.
42
Experiment 12
Wien Bridge Oscillator
Introduction
The Wien bridge oscillator will be used to demonstrate the effects of positive feedback,
and the Barkhausen criterion for oscillation. Negative feedback is also used to stabilize the
transfer characteristics of the amplifier used by this oscillator.
Equipment Needed
y
Normal laboratory equipment
PN2222A npn transistor

(alternate: 2N4401)
PN2907A pnp transistor

(alternate: 2N4403)
Pre Lab
Read the appropriate section(s) of your electronics text dealing with the "Barkhausen
criterion" or "quasi-linear sinusoidal" oscillators.
Procedure
V out
1.
Construct the amplifier of Fig. 1. Measure its voltage gain V in at 1 kHz. Verify
that the amplifier is non-inverting, and that trim pot R4 adjusts its voltage gain from
something less than +3 to something more than +3. Use the 100-K series resistor
together with the function generator (FG) to measure the amplifier input resistance
Rin . (The expected value is about 180 K.)
2.
Add the frequency-selective feedback network to the amplifier as shown in Fig. 2.

Use the capacitor value given for C on Fig. 2, unless otherwise instructed. Initially,
wire the circuit as indicated by the "TEST" position of the switch. Set the FG for a
1
sine wave at the frequency f o = 2RC and monitor Vout and the FG signal using the
two-channel scope. Monitor the phase shift. (Hint: A phase measurement is
available on the DSO "Measure Time" menu.) Vary the FG frequency about f o until
you find the frequency at which the phase is zero.
3.
Remove the FG, and wire Fig. 2 as indicated by the "OSCILLATE" position of the
switch. Adjust trim pot R4 until the circuit breaks into oscillation. Adjust R4 to
produce the minimum amplifier gain which maintains oscillation. Study the effects
of a slight decrease or increase of the amplifier gain about the borderline value
which just barely sustains oscillation. Measure the frequency of oscillation.
4.
Do not change the setting on R4. Remove the frequency-selective feedback network,
V out
and measure the amplifier gain V in as done previously in Fig. 1.
43

Report
1.
Review the Barkhausen criterion for oscillation.
2.
Derive the transfer function V i (s ) of Fig. 3, the frequency-selective feedback

network. Calculate the magnitude and the phase of this function at the frequency
1
f o = 2RC
.
3.
Calculate the amplifier gain required for oscillation at f o . Compare this with your
laboratory observations.
4.
Run a series of several PSpice simulations of the complete oscillator circuit. Use a
transient simulation, and parametrically step the total resistance RE = R3+R4 from
1.2 K to 1.6 K in 100- steps. Set the simulation run time at 50 ms with a
maximum step size of 0.1 ms. Do not omit the initial transient solution. Observe the
start-up process for the oscillator, and comment on it in your report.
V o (s )
44
Fig.1 Voltage amplifier with series-shunt feedback.
Fig. 2 Completed oscillator circuit using amplifier from above.
Fig. 3 Frequency-selective feedback network.
45
46
Experiment 13
Analog/Digital Conversion
Introduction
Most digital signal processing systems are interfaced to the analog world through
analog-to-digital converters (A/D) and digital-to-analog converters (D/A). The purpose of this
experiment is to observe how the conversion process modifies the signal. A circuit board having
separate sample-and-hold (S/H), A/D and D/A sections is provided for this experiment. It allows
easy access to the signals at each stage of these conversion processes.
Equipment Needed
y
Digital Scope with event

averaging capability
Function generator
Analog/digital conversion
circuit board
Pre Lab
Read the appropriate section(s) of your electronics text dealing with A/D and D/A
conversion, as well as S/H circuits.
Procedure
1.
Connect the analog/digital conversion circuit board as shown in Fig. 1. Be sure to

observe correct polarity in connecting the +/- 15-V power supplies. The function
generator and oscilloscope ground leads should be connected to "analog ground."
The power supply common lead is connected to "digital ground." Set the FG for a dc
output1 voltage of 0 V. Connect the scope channel 1 to the analog input (to the A/D
converter), and channel 2 to the analog output (from the D/A converter).
2.
Vary the dc voltage at the analog input slowly from 0 V to 5 V. The eight LEDs
indicate the digital value of the converted analog input voltage. The 8-bit byte
should vary from 00h to FFh . Determine what happens when the analog input
voltage goes below zero, or above 5 V. Using an increment of 1 mV in the analog
voltage, carefully determine the voltage change (to the nearest 1 mV) required to
produce a 1-bit change in the digital output. This is the "quantization step size."
3.
Use a dc voltmeter connected between "analog ground" and "VREF" to measure the
internal reference voltage of the A/D and D/A converters. The result should be 5 V,
plus or minus 5%. Divide VREF by (28 -1) and compare with the quantization step
size measured in step 2. These two results should be equal.
To obtain dc output from the HP 33120A, press and hold the buttons for two waveforms, such
as sine and triangle, simultaneously for several seconds.
47
4.
Set the FG for a 100-mVpp 50-Hz triangle wave with a 100-mV dc offset2. Connect
channel 1 of the scope to show this analog input waveform, and connect channel 2 to
show the output voltage of the S/H stage, labeled "S/H OUT." Trigger from channel
1. You will need to use event averaging to obtain a low-noise display at 50 mV/div.
Record this display which documents the relationship between the low-frequency
input signal and a sampled version of it.
5.
Keep the same setup as the previous step, except move channel 2 to the "analog
output." This output shows the result of digitizing the sampled signal, and then
converting it back to analog form. Record this display which documents the
relationship between the low-frequency input signal and a sampled and quantized
version of it. Use this display to measure the quantization step size.
6.
Measure the frequency of the sampling-and-conversion clock signal labeled

"CONV. CLK." This is the sampling frequency.
7.
Set the FG for a 5-Vpp 500-Hz sine wave with a 2.5-V dc offset. View the input
signal on channel 1, and the sampled signal (S/H OUT) on channel 2. Be sure to
trigger the scope from channel 1. View the results both with and without event
averaging (8 averages is fine). The normally-acquired waveforms should clearly
show the effects of the sampling process on the signal. Record two sets off
waveforms, one event-averaged and the other without event averaging.
8.
With the event averaging turned off, slowly change the frequency of the sine wave
by +/- 10 Hz using 1-Hz increments. Your scope display should be showing signal
components at 500 Hz, and signal components at the sampling frequency ( 7 kHz).
These two frequencies could be commensurate (having an integer-ratio relationship),
or incommensurate. As you change the signal frequency slightly, observe what
happens when the two frequencies involved become commensurate. Record your
written comments.
9.
Set the scope time base for 1 ms/div, and change the triggering source to channel 2
with HF reject on. Channel 2 is still connected to the analog output. Increase the
frequency of the sine wave input from 0.5 kHz to 22 kHz, going in 0.1 kHz steps.
Observe what happens as you pass through the frequencies fS, 2 fS, and 3 fS. Record
your written comments.
1.
Discuss the meaning of "quantization step size." Give its numerical value for this
A/D converter as measured in steps 2 and 3. Label your waveforms recorded in step
Report
Remember that the actual output voltage amplitude will not agree with the programmed value
unless the output termination is set to "High Z."
48
Fig. 1 Top view of analog/digital conversion experiment circuit board. Observe polarity when
connecting the +/- 15-V power supplies.
5 to show where the quantization step size can be measured from these results.
2.
3.
49
50
Data Sheets
The following data sheets are included with this lab manual:
Part
Number
PN2222A
MJE371
LM741
Brief Description
(see data sheet)
npn BJT: small signal, 40 V, 1 A, 625 mW, TO-92 case,
complement to PN2907A
pnp BJT: power, 40 V, 4 A, 4 W, TO-225AA case,
complement to MJE521
Operational Amplifier: GBW=1 MHz, SR=0.5 V/s, Voff<7.5 mV
Additional data sheets are found in the Electronics Lab I lab manual.
51
52
MMBT2222A
PZT2222A
C
E
C
TO-92
SOT-23
SOT-223
Mark: 1P
NPN General Purpose Amplifier

This device is for use as a medium power amplifier and
switch requiring collector currents up to 500 mA. Sourced
from Process 19.
Absolute Maximum Ratings*

Symbol
TA = 25C unless otherwise noted
Parameter
Value
Units
VCEO
Collector-Emitter Voltage
40
VCBO
Collector-Base Voltage
75
VEBO
Emitter-Base Voltage
6.0
IC
Collector Current - Continuous
1.0
TJ, Tstg
Operating and Storage Junction Temperature Range
-55 to +150
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:
1) These ratings are based on a maximum junction temperature of 150 degrees C.
2) These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Thermal Characteristics
Symbol
PD
Characteristic
RJC
Total Device Dissipation

Derate above 25C
Thermal Resistance, Junction to Case
RJA
Thermal Resistance, Junction to Ambient
Max
PN2222A
625
5.0
83.3
*MMBT2222A
350
2.8
**PZT2222A
1,000
8.0
200
357
125
*Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06."

**Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm2.
1998 Fairchild Semiconductor Corporation
Units
mW
mW/C
C/W
C/W
PN2222A / MMBT2222A / PZT2222A
PN2222A
(continued)
Electrical Characteristics
Symbol
Parameter
Test Conditions
Min
Max
Units
OFF CHARACTERISTICS
V(BR)CEO
Collector-Emitter Breakdown Voltage*
IC = 10 mA, IB = 0
40
V(BR)CBO
Collector-Base Breakdown Voltage
IC = 10 A, IE = 0
75
V(BR)EBO
Emitter-Base Breakdown Voltage
IE = 10 A, IC = 0
6.0
ICEX
Collector Cutoff Current
VCE = 60 V, VEB(OFF) = 3.0 V
ICBO
Collector Cutoff Current
IEBO
Emitter Cutoff Current
VCB = 60 V, IE = 0
VCB = 60 V, IE = 0, TA = 150C
VEB = 3.0 V, IC = 0
IBL
Base Cutoff Current
VCE = 60 V, VEB(OFF) = 3.0 V
V
10
nA
0.01
10
10
A
A
nA
20
nA
ON CHARACTERISTICS
hFE
VCE(sat)
VBE(sat)
DC Current Gain
Collector-Emitter Saturation
Voltage*
Base-Emitter Saturation Voltage*
IC = 0.1 mA, VCE = 10 V

IC = 1.0 mA, VCE = 10 V
IC = 10 mA, VCE = 10 V
IC = 10 mA, VCE = 10 V, TA = -55C
IC = 150 mA, VCE = 10 V*
IC = 150 mA, VCE = 1.0 V*
IC = 500 mA, VCE = 10 V*
IC = 150 mA, IB = 15 mA
IC = 500 mA, IB = 50 mA
IC = 150 mA, IB = 15 mA
IC = 500 mA, IB = 50 mA
35
50
75
35
100
50
40
300
0.6
300
0.3
1.0
1.2
2.0
V
V
V
V
SMALL SIGNAL CHARACTERISTICS

fT
Current Gain - Bandwidth Product
IC= 20 mA, VCE= 20 V, f= 100 MHz
Cobo
Output Capacitance
VCB = 10 V, IE = 0, f = 100 kHz
8.0
MHz
Cibo
rbCC
Input Capacitance
VEB = 0.5 V, IC = 0, f = 100 kHz
25
pF
Collector Base Time Constant
IC= 20 mA, VCB= 20 V, f= 31.8 MHz
150
pS
NF
Noise Figure
4.0
dB
Re(hie)
Real Part of Common-Emitter

High Frequency Input Impedance
IC = 100 A, VCE = 10 V,
RS = 1.0 k, f = 1.0 kHz
IC = 20 mA, VCE = 20 V,
f = 300 MHz
60
10
ns
pF
SWITCHING CHARACTERISTICS
td
Delay Time
VCC = 30 V, VBE(OFF) = 0.5 V,
tr
Rise Time
IC = 150 mA, IB1 = 15 mA
25
ns
ts
Storage Time
VCC = 30 V, IC = 150 mA,
225
ns
tf
Fall Time
IB1 = IB2 = 15 mA
60
ns
*Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%
Spice Model
NPN (Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0
Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6
Vtf=1.7 Xtf=3 Rb=10)
(continued)
V CE = 5V
400
125 C
300
200
25 C
100
- 40 C
0
0.1
0.3
1
3
10
30
100
I C - COLLECTOR CURRENT (mA)
300
Base-Emitter Saturation
Voltage vs Collector Current
= 10
- 40 C
0.8
25 C
125 C
0.6
0.4
1
I
10
100
- COLLECTOR CURRENT (mA)
500
V CESAT - COLLECTOR-EMITTER VOLTAGE (V)
500
V BE(ON) - BASE-EMITTER ON VOLTAGE (V)
Typical Pulsed Current Gain

vs Collector Current
V BESAT - BASE-EMITTER VOLTAGE (V)
h FE - TYPICAL PULSED CURRENT GAIN
Typical Characteristics
0.4
= 10
0.3
125 C
0.2
25 C
0.1
- 40 C
10
100
500
Base-Emitter ON Voltage vs
Collector Current
1
VCE = 5V
0.8
- 40 C
25 C
0.6
125 C
0.4
0.2
0.1
1
10
25
Emitter Transition and Output

Capacitance vs Reverse Bias Voltage
Collector-Cutoff Current
vs Ambient Temperature
500
100
CB
20
= 40V
CAPACITANCE (pF)
I CBO - COLLECTOR CURRENT (nA)
Collector-Emitter Saturation
Voltage vs Collector Current
10
1
0.1
f = 1 MHz
16
12
C te
8
C ob
4
25
50
75
100
125
T A - AMBIENT TEMPERATURE ( C)
150
0.1
1
10
REVERSE BIAS VOLTAGE (V)
100
(continued)
Typical Characteristics
(continued)
Turn On and Turn Off Times

400
I B1 = I B2 =
Switching Times
400
Ic
320
TIME (nS)
V cc = 25 V
240
160
240
ts
160
tr
t off
80
tf
80
t on
td
100
0
10
1000
100
Power Dissipation vs
Ambient Temperature
1
PD - POWER DISSIPATION (W)
TIME (nS)
10
320
V cc = 25 V
0
10
Ic
I B1 = I B2 =
10
SOT-223
0.75
TO-92
0.5
SOT-23
0.25
25
50
75
100
o
TEMPERATURE ( C)
125
150
1000
(continued)
V CE = 10 V
T A = 25oC
6
hoe
4
h re
2
h fe
h ie
0
10
20
30
40
50
60
CHAR. RELATIVE TO VALUES AT TA = 25oC
Common Emitter Characteristics

8
CHAR. RELATIVE TO VALUES AT VCE = 10V
CHAR. RELATIVE TO VALUES AT I C= 10mA
Typical Common Emitter Characteristics
(f = 1.0kHz)

2.4
V CE = 10 V
I C = 10 mA
h re
h fe
1.6
hoe
1.2
0.8
0.4
0
20
40
60
80
T A - AMBIENT TEMPERATURE ( o C)

1.3
I C = 10 mA
T A = 25oC
1.25
h fe
1.2
1.15
h ie
1.1
1.05
1
h re
0.95
0.9
0.85
hoe
0.8
0.75
h ie
10
15
20
25
30
VCE - COLLECTOR VOLTAGE (V)
35
100
(continued)
Test Circuits
30 V
200
16 V
1.0 K
0
200ns
500
FIGURE 1: Saturated Turn-On Switching Time
6.0 V
- 1.5 V
NOTE: BVEBO = 5.0 V
1k
30 V
1.0 K
0
200ns
50
FIGURE 2: Saturated Turn-Off Switching Time
37
TO-92 Tape and Reel Data
TO-92 Packaging
Configuration: Figure 1.0
TAPE and REEL OPTION
FSCINT Label sample
See Fig 2.0 for various

Reeling Styles
FAIRCHILD SEMICONDUCTOR CORPORATION

LOT:
CBVK741B019
PN2222N
NSID:
D/C1:
HTB:B
QTY: 10000
SPEC:
D9842
SPEC REV:
FSCINT
Label
B2
QA REV:
5 Reels per
Intermediate Box
(FSCINT)
Customized
Label
F63TNR Label sample

LOT: CBVK741B019
FSID: PN222N
D/C1: D9842
D/C2:
F63TNR
Label
QTY: 2000
SPEC:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
Customized
Label
(F63TNR)3
375mm x 267mm x 375mm

Intermediate Box
TO-92 TNR/AMMO PACKING INFROMATION
Packing
Style
Quantity
EOL code
Reel
2,000
D26Z
2,000
D27Z
Ammo
2,000
D74Z
2,000
D75Z
AMMO PACK OPTION

See Fig 3.0 for 2 Ammo
Pack Options
FSCINT
Label
Unit weight
= 0.22 gm
Reel weight with components
= 1.04 kg
Ammo weight with components = 1.02 kg
Max quantity per intermediate box = 10,000 units
327mm x 158mm x 135mm

Immediate Box
Customized
Label
(TO-92) BULK PACKING INFORMATION

EOL
CODE
DESCRIPTION
QUANTITY
TO-18 OPTION STD
NO LEAD CLIP
2.0 K / BOX
J05Z
TO-5 OPTION STD
NO LEAD CLIP
1.5 K / BOX
NO LEADCLIP
2.0 K / BOX
NO LEADCLIP
2.0 K / BOX
TO-92 STANDARD
STRAIGHT FOR: PKG 92,
94 (NON PROELECTRON
SERIES), 96
L34Z
TO-92 STANDARD
STRAIGHT FOR: PKG 94
(PROELECTRON SERIES
BCXXX, BFXXX, BSRXXX),
97, 98
Customized
Label
F63TNR
Label
333mm x 231mm x 183mm
Intermediate Box
BULK OPTION
LEADCLIP
DIMENSION
J18Z
NO EOL
CODE
5 Ammo boxes per

Intermediate Box
See Bulk Packing

Information table
Anti-static
Bubble Sheets
FSCINT Label
2000 units per

EO70 box for
std option
114mm x 102mm x 51mm

Immediate Box
5 EO70 boxes per

intermediate Box
Intermediate box
Customized
Label
FSCINT Label
10,000 units maximum
per intermediate box
for std option
2001 Fairchild Semiconductor Corporation
March 2001, Rev. B1
TO-92 Tape and Reel Data, continued
TO-92 Reeling Style

Machine Option A (H)
Machine Option E (J)
Style A, D26Z, D70Z (s/h)
Style E, D27Z, D71Z (s/h)
TO-92 Radial Ammo Packaging

FIRST WIRE OFF IS COLLECTOR
ADHESIVE TAPE IS ON THE TOP SIDE
FLAT OF TRANSISTOR IS ON TOP
ORDER STYLE
D74Z (M)
FIRST WIRE OFF IS EMITTER (ON PKG. 92)

ADHESIVE TAPE IS ON BOTTOM SIDE
FLAT OF TRANSISTOR IS ON BOTTOM
FIRST WIRE OFF IS EMITTER

ADHESIVE TAPE IS ON THE TOP SIDE
FLAT OF TRANSISTOR IS ON BOTTOM
ORDER STYLE
D75Z (P)
FIRST WIRE OFF IS COLLECTOR (ON PKG. 92)

ADHESIVE TAPE IS ON BOTTOM SIDE
FLAT OF TRANSISTOR IS ON TOP
September 1999, Rev. B
TO-92 Tape and Reel Data, continued

TO-92 Tape and Reel Taping
Dimension Configuration: Figure 4.0
Hd
P
Pd
b
Ha
W1
d
L
H1 HO
L1
S
WO
W2
W
t1
P1 F1
DO
P2
PO
User Direction of Feed
TO-92 Reel
ITEM DESCRIPTION
SYMBOL
DIMENSION
Base of Package to Lead Bend
0.098 (max)
Component Height
Ha
0.928 (+/- 0.025)
Lead Clinch Height
HO
0.630 (+/- 0.020)
Component Base Height
H1
0.748 (+/- 0.020)
Component Alignment ( side/side )
Pd
0.040 (max)
Component Alignment ( front/back )
Hd
0.031 (max)
Component Pitch
0.500 (+/- 0.020)
Feed Hole Pitch
PO
0.500 (+/- 0.008)
Hole Center to First Lead
P1
0.150 (+0.009, -0.010)
Hole Center to Component Center
P2
0.247 (+/- 0.007)
Lead Spread
F1/F2
0.104 (+/- 0 .010)
Lead Thickness
0.018 (+0.002, -0.003)
Cut Lead Length
0.429 (max)
Taped Lead Length
L1
0.209 (+0.051, -0.052)
Taped Lead Thickness
0.032 (+/- 0.006)
Carrier Tape Thickness
t1
0.021 (+/- 0.006)
Carrier Tape Width
0.708 (+0.020, -0.019)
Hold - down Tape Width
WO
0.236 (+/- 0.012)
Hold - down Tape position
W1
0.035 (max)
Feed Hole Position
W2
0.360 (+/- 0.025)
Sprocket Hole Diameter
DO
0.157 (+0.008, -0.007)
Lead Spring Out
0.004 (max)
Note : All dimensions are in inches.

ELECT ROSTATIC
SEN SITIVE D EVICES
D4
D1
D2
F63TNR Label
ITEM DESCRIPTION
SYSMBOL
MINIMUM
MAXIMUM
Reel Diameter
D1
13.975
14.025
Arbor Hole Diameter (Standard)
D2
1.160
1.200
D2
0.650
0.700
Customized Label
(Small Hole)
W1
Core Diameter
D3
3.100
3.300
Hub Recess Inner Diameter
D4
2.700
3.100
Hub Recess Depth
W1
0.370
0.570
Flange to Flange Inner Width
W2
1.630
Hub to Hub Center Width
W3
1.690
2.090
W3
W2
Note: All dimensions are inches

D3
July 1999, Rev. A
TO-92 Package Dimensions
TO-92 (FS PKG Code 92, 94, 96)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.1977
2000 Fairchild Semiconductor International
January 2000, Rev. B
SOT-23 Tape and Reel Data

SOT-23 Packaging
Customized Label
Packaging Description:
SOT-23 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,000 units per 7" or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 10,000 units per 13"
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
Antistatic Cover Tape
Human Readable
Label
These full reels are individually labeled and placed inside

a standard intermediate made of recyclable corrugated
brown paper with a Fairchil d logo printing. One pizza box
contains eight reels maximum. And these intermediate
boxes are placed inside a labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Embossed
Carrier Tape
3P
3P
3P
3P
SOT-23 Packaging Information

Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Standard
(no flow code)
TNR
3,000
D87Z
7" Dia
13"
187x107x183
343x343x64
Max qty per Box
24,000
30,000
Weight per unit (gm)
0.0082
0.0082
Weight per Reel (kg)
0.1175
0.4006
Reel Size
Box Dimension (mm)
SOT-23 Unit Orientation
TNR
10,000

Intermediate box for L87Z Option
Human Readable Label
Note/Comments
Human Readable Label sample
H uman readable
Label
187mm x 107mm x 183mm

Intermediate Box for Standard Option
SOT-23 Tape Leader and Trailer

Carrier Tape
Cover Tape
Components
Trailer Tape
300mm minimum or
75 empt y poc kets
Leader Tape
500mm minimum or
125 empty pockets
September 1999, Rev. C
SOT-23 Tape and Reel Data, continued

SOT-23 Embossed Carrier Tape
P0
P2
D1
D0
T
E1
F
E2
Wc
B0
Tc
A0
P1
K0
Dimensions are in millimeter

Pkg type
A0
B0
SOT-23
(8mm)
3.15
+/-0.10
2.77
+/-0.10
W
8.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.125
+/-0.125
1.75
+/-0.10
6.25
min
3.50
+/-0.05
P1
P0
4.0
+/-0.1
4.0
+/-0.1
K0
1.30
+/-0.10
0.228
+/-0.013
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
Wc
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
5.2
+/-0.3
Tc
0.5mm
maximum
20 deg maximum component rotation

Typical
component
center line
Sketch A (Side or Front Sectional View)

A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SOT-23 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option

B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub

DETAIL AA
Dimensions are in inches and millimeters

Tape Size
Reel
Option
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
8mm
7" Dia
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
8mm
13" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 0.429
7.9 10.9
SOT-23 Package Dimensions
SOT-23 (FS PKG Code 49)
1:1
Dimensions shown below are in:
inches [millimeters]
September 1998, Rev. A1
SOT-223 Tape and Reel Data

SOT-223 Packaging
Customized Label
Packaging Description:
F63TNR Label
Antistatic Cover Tape
SOT-223 parts are shipped in tape. The carrier tape is

made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Static Dissipative
Embossed Carrier Tape
F852
014
F852
014
F852
014
F852
014
SOT-223 Packaging Information

Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Standard
(no flow code)
TNR
2,500
D84Z
SOT-223 Unit Orientation
TNR
500
13" Dia
7" Dia
343x64x343
184x187x47
Max qty per Box
5,000
1,000
Weight per unit (gm)
0.1246
0.1246
Weight per Reel (kg)
0.7250
0.1532

Intermediate box for Standard
F63TNR Label
Note/Comments
F63TNR Label
F63TNR Label sample

Pizza Box for D84Z Option
SOT-223 Tape Leader and Trailer

LOT: CBVK741B019
QTY: 3000
FSID: PN2222A
SPEC:
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
(F63TNR)3
Carrier Tape
Cover Tape
Components
Trailer Tape
300mm minimum or
38 empty pockets
Leader Tape
500mm minimum or
62 empty pockets
September 1999, Rev. B
SOT-223 Tape and Reel Data, continued

SOT-223 Embossed Carrier Tape
P0
D0
T
E1
F
K0
Wc
E2
B0
Tc
A0
D1
P1
Dimensions are in millimeter

Pkg type
SOT-223
(12mm)
A0
6.83
+/-0.10
B0
7.42
+/-0.10
W
12.0
+/-0.3
D0
D1
1.55
+/-0.05
1.50
+/-0.10
E1
E2
1.75
+/-0.10
10.25
min
P1
5.50
+/-0.05
P0
8.0
+/-0.1
4.0
+/-0.1
K0
1.88
+/-0.10
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
Wc
0.292
+/0.0130
9.5
+/-0.025
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
Tc
0.5mm
maximum
20 deg maximum component rotation

Typical
component
center line
Sketch A (Side or Front Sectional View)

A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SOT-223 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option

B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub

DETAIL AA
Dimensions are in inches and millimeters

Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
5.906
150
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 0.606
11.9 15.4
12mm
7" Dia
7.00
177.8
12mm
13" Dia
13.00
330
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
July 1999, Rev. B
SOT-223 Package Dimensions
SOT-223 (FS PKG Code 47)
1:1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx
Bottomless
CoolFET
CROSSVOLT
DOME
E2CMOSTM
EnSignaTM
FACT
FACT Quiet Series
FAST
FASTr
GlobalOptoisolator
GTO
HiSeC
ISOPLANAR
MICROWIRE
OPTOLOGIC
OPTOPLANAR
PACMAN
POP
PowerTrench
QFET
QS
QT Optoelectronics
Quiet Series
SILENT SWITCHER
SMART START
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
TinyLogic
UHC
VCX
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for

product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. G

Order this document

by MJE371/D
SEMICONDUCTOR TECHNICAL DATA

4 AMPERE
POWER TRANSISTOR
PNP SILICON
40 VOLTS
40 WATTS
. . . designed for use in generalpurpose amplifier and switching circuits. Recommended for use in 5 to 20 Watt audio amplifiers utilizing complementary symmetry
circuitry.
DC Current Gain hFE = 40 (Min) @ IC = 1.0 Adc
MJE371 is Complementary to NPN MJE521
v
v
CASE 7708
TO225AA TYPE
MAXIMUM RATINGS
Rating
CollectorEmitter Voltage
Symbol
Value
Unit
VCEO
40
Vdc
CollectorBase Voltage
VCB
40
Vdc
EmitterBase Voltage
VEB
4.0
Vdc
Collector Current Continuous

Peak
IC
4.0
8.0
Adc
Base Current Continuous
IB
2.0
Adc
Total Power Dissipation @ TC = 25_C

Derate above 25_C
PD
40
320
Watts
mW/_C
TJ, Tstg
65 to + 150
_C
Symbol
Max
Unit
JC
3.12
_C/W
Operating and Storage Junction Temperature Range
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)

Characteristic
Symbol
Min
Max
Unit
VCEO(sus)
40
Vdc
CollectorBase Cutoff Current

(VCB = 40 Vdc, IE = 0)
ICBO
100
Adc
EmitterBase Cutoff Current

(VEB = 4.0 Vdc, IC = 0)
IEBO
100
Adc
hFE
40
OFF CHARACTERISTICS
CollectorEmitter Sustaining Voltage (1)

(IC = 100 mAdc, IB = 0)
ON CHARACTERISTICS
DC Current Gain (1)

(IC = 1.0 Adc, VCE = 1.0 Vdc)
(1) Pulse Test: Pulse Width
300 s, Duty Cycle
2.0%.
REV 2
Motorola, Inc. 1995

Motorola Bipolar Power Transistor Device Data
MJE371
IC, COLLECTOR CURRENT (AMP)
10
100 s
1.0 ms
5.0
3.0
2.0
5.0 ms
dc
1.0
TJ = 150C
0.5
BONDING WIRE LIMIT

SECOND BREAKDOWN LIMIT
THERMAL LIMIT @ TC = 25C
0.3
0.2
0.1
2.0
There are two limitations on the power handling ability of a

transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 1 is based on T J(pk) = 150_C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T J(pk)
150_C.
At high case temperatures, thermal limitations will reduce the
power that can be handled to values less then the limitations
imposed by second breakdown.
40
4.0
6.0 8.0 10
20
VCE, COLLECTOREMITTER VOLTAGE (VOLTS)
60
2.0
10
7.0
5.0
TJ = 25C
150C
1.6
VCE = 1.0 Vdc
3.0
VOLTAGE (VOLTS)
hFE , DC CURRENT GAIN, NORMALIZED
Figure 1. ActiveRegion Safe Operating Area
2.0
55C
1.0
0.7
0.5
0.3
TJ = 25C
1.2
0.8
VBE(sat) @ IC/IB = 10
VBE(on) @ VCE = 1.0 V
0.4
0.2
0.1
0.01
0.02 0.03 0.05 0.1

0.2 0.3 0.5
1.0
2.0 3.0 4.0
VCE(sat) @ IC/IB = 10
0
0.005 0.01 0.02 0.03 0.05 0.1
0.2 0.3 0.5
1.0
r(t), EFFECTIVE TRANSIENT

THERMAL RESISTANCE (NORMALIZED)
Figure 2. DC Current Gain
1.0
0.7
0.5
0.3
Figure 3. On Voltage
D = 0.5
0.2
0.2
0.05
0.02
0.03
P(pk)
JC(t) = r(t) JC
JC = 3.12C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) JC(t)
0.1
0.1
0.07
0.05
2.0 3.0 4.0
0.01
t1
t2
DUTY CYCLE, D = t1/t2
0.02
SINGLE PULSE
0.01
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1.0
2.0 3.0 5.0
10
t, TIME OR PULSE WIDTH (ms)
20
50
100
200
500
Figure 4. Thermal Response
1000
MJE371
PACKAGE DIMENSIONS
B
U
Q
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
C
M
1 2 3
V
G
S
R
0.25 (0.010)
D 2 PL
0.25 (0.010)
DIM
A
B
C
D
F
G
H
J
K
M
Q
R
S
U
V
INCHES
MIN
MAX
0.425
0.435
0.295
0.305
0.095
0.105
0.020
0.026
0.115
0.130
0.094 BSC
0.050
0.095
0.015
0.025
0.575
0.655
5 _ TYP
0.148
0.158
0.045
0.055
0.025
0.035
0.145
0.155
0.040
MILLIMETERS
MIN
MAX
10.80
11.04
7.50
7.74
2.42
2.66
0.51
0.66
2.93
3.30
2.39 BSC
1.27
2.41
0.39
0.63
14.61
16.63
5 _ TYP
3.76
4.01
1.15
1.39
0.64
0.88
3.69
3.93
1.02
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. BASE
CASE 7708
TO225AA TYPE
ISSUE V
MJE371
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different
applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:

USA / EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 18004412447
JAPAN: Nippon Motorola Ltd.; TatsumiSPDJLDC, Toshikatsu Otsuki,

6F SeibuButsuryuCenter, 3142 Tatsumi KotoKu, Tokyo 135, Japan. 0335218315
MFAX: RMFAX0@email.sps.mot.com TOUCHTONE (602) 2446609

INTERNET: http://DesignNET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 85226629298
*MJE371/D*
MJE371/D
LM741 Operational Amplifier

General Description
The LM741 series are general purpose operational amplifiers which feature improved performance over industry standards like the LM709. They are direct, plug-in replacements
for the 709C, LM201, MC1439 and 748 in most applications.
The amplifiers offer many features which make their application nearly foolproof: overload protection on the input and
output, no latch-up when the common mode range is exceeded, as well as freedom from oscillations.
The LM741C/LM741E are identical to the LM741/LM741A
except that the LM741C/LM741E have their performance
guaranteed over a 0 C to a 70 C temperature range, instead of b55 C to a 125 C.
Schematic Diagram
TL/H/9341 1
Offset Nulling Circuit
TL/H/9341 7
C1995 National Semiconductor Corporation
TL/H/9341
RRD-B30M115/Printed in U. S. A.
November 1994
Absolute Maximum Ratings

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 5)
LM741A
LM741E
LM741
LM741C
g 22V
g 22V
g 22V
g 18V
Supply Voltage
Power Dissipation (Note 1)
500 mW
500 mW
500 mW
500 mW
g 30V
g 30V
g 30V
g 30V
Differential Input Voltage
g 15V
g 15V
g 15V
g 15V
Input Voltage (Note 2)
Output Short Circuit Duration
Continuous
Continuous
Continuous
Continuous
b 55 C to a 125 C
b 55 C to a 125 C
0 C to a 70 C
0 C to a 70 C
Operating Temperature Range
b 65 C to a 150 C
b 65 C to a 150 C
b 65 C to a 150 C
b 65 C to a 150 C
Storage Temperature Range
Junction Temperature
150 C
100 C
150 C
100 C
Soldering Information
N-Package (10 seconds)
260 C
260 C
260 C
260 C
J- or H-Package (10 seconds)
300 C
300 C
300 C
300 C
M-Package
Vapor Phase (60 seconds)
215 C
215 C
215 C
215 C
Infrared (15 seconds)
215 C
215 C
215 C
215 C
See AN-450 Surface Mounting Methods and Their Effect on Product Reliability for other methods of soldering
surface mount devices.
ESD Tolerance (Note 6)
400V
400V
400V
400V
Electrical Characteristics (Note 3)

Parameter
Conditions
LM741A/LM741E
Min
Input Offset Voltage
TA e 25 C
RS s 10 kX
RS s 50X
Typ
Max
0.8
3.0
TAMIN s TA s TAMAX
RS s 50X
RS s 10 kX
TA e 25 C, VS e g 20V
Input Offset Current
TA e 25 C
5.0
Units
Typ
Max
2.0
6.0
7.5
g 15
3.0
g 15
TA e 25 C
30
30
20
200
70
85
500
20
200
nA
300
nA
nA/ C
80
80
0.210
TA e 25 C, VS e g 20V
1.0
TAMIN s TA s TAMAX,
VS e g 20V
0.5
6.0
500
80
1.5
0.3
2.0
0.3
TA e 25 C
g 12
50
TAMIN s TA s TAMAX,
RL t 2 kX,
VS e g 20V, VO e g 15V
32
2.0
500
nA
0.8
mA
MX
MX
TAMIN s TA s TAMAX
TA e 25 C, RL t 2 kX
mV
mV
mV
0.5
TAMIN s TA s TAMAX
mV
mV
mV/ C
g 10
Average Input Offset

Current Drift
Large Signal Voltage Gain
1.0
Min
6.0
TAMIN s TA s TAMAX
Input Voltage Range
Max
15
Input Offset Voltage

Adjustment Range
Input Resistance
LM741C
Typ
4.0
Average Input Offset

Voltage Drift
Input Bias Current
LM741
Min
g 12
g 13
50
200
25
10
g 13
V
V
20
15
200
V/mV
V/mV
V/mV
V/mV
V/mV
Electrical Characteristics (Note 3) (Continued)

Parameter
Conditions
LM741A/LM741E
Min
Output Voltage Swing
VS e g 20V
RL t 10 kX
RL t 2 kX
Typ
Max
10
10
25
Common-Mode
Rejection Ratio
TAMIN s TA s TAMAX
RS s 10 kX, VCM e g 12V
RS s 50X, VCM e g 12V
80
95
86
96
TAMIN s TA s TAMAX,
VS e g 20V to VS e g 5V
RS s 50X
RS s 10 kX
Transient Response
Rise Time
Overshoot
TA e 25 C, Unity Gain
Bandwidth (Note 4)
TA e 25 C
Slew Rate
TA e 25 C, Unity Gain
Supply Current
TA e 25 C
LM741A
LM741E
LM741
Min
Typ
Units
Max
V
V
TA e 25 C
TAMIN s TA s TAMAX
0.25
6.0
TA
VS
VS
LM741C
Max
g 15
Output Short Circuit

Current
Power Consumption
Typ
g 16
VS e g 15V
RL t 10 kX
RL t 2 kX
Supply Voltage Rejection

Ratio
LM741
Min
0.437
1.5
0.3
0.7
e 25 C
e g 20V
e g 15V
80
g 12
g 14
g 12
g 14
g 10
g 13
g 10
g 13
35
40
0.8
20
25
V
V
25
mA
mA
dB
dB
70
90
70
90
77
96
77
96
dB
dB
0.3
5
0.3
5
ms
%
0.5
0.5
V/ms
MHz
1.7
2.8
1.7
2.8
mA
50
85
50
85
mW
mW
150
VS e g 20V
TA e TAMIN
TA e TAMAX
165
135
mW
mW
VS e g 20V
TA e TAMIN
TA e TAMAX
150
150
mW
mW
VS e g 15V
TA e TAMIN
TA e TAMAX
60
45
100
75
mW
mW
Note 1: For operation at elevated temperatures, these devices must be derated based on thermal resistance, and Tj max. (listed under Absolute Maximum
Ratings). Tj e TA a (ijA PD).
Thermal Resistance
Cerdip (J)
DIP (N)
HO8 (H)
SO-8 (M)
ijA (Junction to Ambient)
100 C/W
100 C/W
170 C/W
195 C/W
N/A
N/A
25 C/W
N/A
ijC (Junction to Case)
Note 2: For supply voltages less than g 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 3: Unless otherwise specified, these specifications apply for VS e g 15V, b 55 C s TA s a 125 C (LM741/LM741A). For the LM741C/LM741E, these
specifications are limited to 0 C s TA s a 70 C.
Note 4: Calculated value from: BW (MHz) e 0.35/Rise Time(ms).
Note 5: For military specifications see RETS741X for LM741 and RETS741AX for LM741A.
Note 6: Human body model, 1.5 kX in series with 100 pF.
Connection Diagrams
Ceramic Dual-In-Line Package
Metal Can Package
TL/H/93412
TL/H/9341 5
Order Number LM741H, LM741H/883*,

LM741AH/883 or LM741CH
See NS Package Number H08C
Order Number LM741J-14/883*, LM741AJ-14/883**

See NS Package Number J14A
*also available per JM38510/10101
**also available per JM38510/10102
Dual-In-Line or S.O. Package

Ceramic Flatpak
TL/H/9341 6
Order Number LM741W/883

See NS Package Number W10A
TL/H/93413
Order Number LM741J, LM741J/883,

LM741CM, LM741CN or LM741EN
See NS Package Number J08A, M08A or N08E
*LM741H is available per JM38510/10101
Physical Dimensions inches (millimeters)
Metal Can Package (H)

Order Number LM741H, LM741H/883, LM741AH/883, LM741CH or LM741EH
NS Package Number H08C
Physical Dimensions inches (millimeters) (Continued)
Ceramic Dual-In-Line Package (J)

Order Number LM741CJ or LM741J/883
NS Package Number J08A
Ceramic Dual-In-Line Package (J)

Order Number LM741J-14/883 or LM741AJ-14/883
NS Package Number J14A
Small Outline Package (M)

Order Number LM741CM
NS Package Number M08A
Dual-In-Line Package (N)

Order Number LM741CN or LM741EN
NS Package Number N08E
10-Lead Ceramic Flatpak (W)

Order Number LM741W/883
NS Package Number W10A
LIFE SUPPORT POLICY

NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life

support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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Electronics Laboratory II

Prof. Roger King, EECS

Experiment 1 SPICE Modeling the 741

v SPICE model for a 741

Fig. 1 Inverting amplifier using a 741 op-amp.

SPICE Modeling the 741 Op-Amp

4. Describe the behavior of this inverting amplifier when it is producing a 10-V

SPICE Modeling the 741 Op-Amp

Fig. 2 Inverting amplifier with 741 op-amp model.

Input source for ac

Input source for

SPICE Modeling the 741 Op-Amp

v Power supplies, function

741 Op-Amp Circuits

741 Op-Amp Circuits

Fig. 1 Inverting amplifier, 8-pin dual-in-line plastic package (top view).

Fig. 2 Non-inverting amplifier.

741 Op-Amp Circuits

Fig. 1 JFET common-source amplifier.

SPICE Simulation of a JFET Common-Source Amplifier

v 2N5457 n-channel JFET

v For alternate VP and IDSS , you

JFET Common-Source Amplifier

JFET Common-Source Amplifier

Fig. 1 JFET common-source amplifier.

Fig. 2 2N5457 case and pin-outs.

JFET Common-Source Amplifier

v PN2222A npn transistor

2. Measure the input resistance Ri .

3. Measure the output resistance Ro .

2. Measure the input resistance Ri .

3. Measure the output resistance Ro .

Small-Signal CC and CB Amplifiers

following: A v , Ri , Ri , R o , and Ro for Figs. 1 and 2.

Small-Signal CC and CB Amplifiers

Fig. 1 Common-collector (emitter follower) amplifier.

Fig. 2. Common-base amplifier.

Fig. 3 PN2222A package

Small-Signal CC and CB Amplifiers

(first measurement), and

6. Output resistance Ro is measured by monitoring V o while driving the amplifier with a

v PN2222A npn transistor

v Switchable 0-dB/40-dB 50-

Fig. 1 Common-emitter amplifier with blocking and bypass capacitors.

Bypass and Coupling Capacitor Effects

Bypass and Coupling Capacitor Effects

Bypass and Coupling Capacitor Effects

v PN2222A npn transistor

Fig. 1 Common-emitter amplifier.

BJT High-Frequency Performance

BJT High-Frequency Performance

BJT High-Frequency Performance

Appendix B - SPICE Simulation of the CE Amplifier

v two PN2222A npn transistors

v Scope probe having known input

For the HP 10071A probe, the input capacitance is 16 pF.

v Load resistor (about 12 , 5 W)

Complementary-Symmetry Push-Pull Amplifier

Complementary-Symmetry Push-Pull Amplifier

Fig. 1 Simplified diagram of the complementary-symmetry output stage.

Fig. 2 Complementary-symmetry amplifier with negative feedback.

Complementary-Symmetry Push-Pull Amplifier

Fig. 4 '741 pinout, top view.

v PN2222A npn transistor