EE 705: Experiment 1

Madhav Desai
January 9, 2015

Describing Combinational Circuits in VHDL

In a combinational circuit, the stable values of the outputs depend solely on the
stable values the current inputs. Thus the response of a combinational circuit to
an input event is always the same (irrespective of what happened in the past).
To describe a combinational circuit in VHDL, one has several options. We
illustrate this with an example. Suppose we want to describe a combinational
circuit which has one output bit w and inputs a,b,c,d,e (all bits), and implements
the formula
w = (a + b + c).(d + e)
Such a circuit can be described in several ways, of which the following are the
most common.
The first is to use concurrent assignments. For example
w <= (a or b or c) and (not (d or e));
or
w <= u and v;
u <= (a or b or c);
v <= not ( d or e);
etc. In this case, it is easy to verify that each driver is purely combinational
because the output of each driver depends only on the inputs (and the inputs do
not include the output!). Further, the network of drivers is acyclic, and hence
can have no state.
The second way is to use a process statement.
process(a,b,c,d,e)
variable u, v: bit;
begin
u := (a or b or c);
u := (u and not(d or e));
w <= u;
end process;

In this case, it is clear that every time the process statement is executed, the
value scheduled to be written onto w is a function entirely of a,b,c,d,e and does
not depend on the old value of w.

1.1

Examples of non-combinational descriptions

Take this case

w <= (clk and d) or w;
This is not a combinational driver because w depends on w.
In the following case:
q <= not ((not s) and qbar);
qbar <= not ((not r) and q);
The two drivers are part of a cycle, and as a result, the circuit can potentially
have state.
A process statement which is not combinational.
process(c,d)
begin
if(c = 1) then
q <= d;
end if;
end process;
This process does not describe a combinational circuit because the result left at
q depends potentially on the old value of q.

In Lab Assignment

Using VHDL, describe a combinational circuit which implements an 8-input

priority encoder with the following entity description
entity PriorityEncoder is
port (x7,x6,x5,x4,x3,x2,x1,x0: in bit;
s2,s1,s0,N: out bit);
end entity;
The priority encoder behaves as follows: If all the input bits to the encoder are
0, then N=1 and s2,s1,s0 are dont-cares. If at least one of the input bits to the
encoder is 1, then N=0, and the bits s2,s1,s0 indicate the binary code for the
lowest index I for which the corresponding input xI is 1.
Implement an architecture for the PriorityEncoder entity. Verify it using
a testbench which checks all 256 input conditions. The test-bench should be
self checking; ie, it should report success/failure without you having to check
waveforms.
2

Home Assignment

Read up on array types and implement the PriorityEncoder with the following
entity description
entity PriorityEncoder is
port (x: in bit_vector(7 downto 0);
s: out bit_vector(2 downto 0);
N: out bit);
end entity PriorityEncoder;
The behaviour of the encoder is the same as before.
Implement an architecture for the PriorityEncoder entity. Verify it using
a testbench which checks all 256 input conditions. The test-bench should be
self checking; ie, it should report success/failure without you having to check
waveforms.