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Operational Amplifier
Stability
Compensation
Miller Effect
Phase Margin
Unity Gain Frequency
Slew Rate Limiting
Reading:
Solomon, The Monolithic IC Op Amp: A
Tutorial Study
Two-stage op-amp
Analysis Strategy
Recognize sub-blocks
Represent as cascade of simple stages
DC operating point
MOSFET
M1
M2
M3
M4
M5
M6
M7
M8
ID[A]
25
25
25
25
50
50
50
50
Veff
0.235
0.235
0.247
0.247
0.350
0.332
0.332
0.332
av1 = 106
av2 = 73
Gate of M5
"
F
Cg = (900m)(10m) 4.17E ! 4 2 $
#
m %
Cg = 3.74 pF
1
2! (800k" 1.43M")(3.74pF )
f p1 = 82kHz
1
2! (400k" 715k" )(10 pF )
f p1 = 61kHz
][
Negative feedback:
Output connected to inverting input
! RL $
& vin
vout = #
" RL + RS %
vout = vin
No buffer:
With buffer:
Voltage divider
No current required
from source
Signal reduced due to
voltage drop across RS
Problem: Instability
Oscillation superimposed on desired output
Output for zero input
Why? Need...
R1
!=
R1 + R2
(1 + A")vout = Avin
vout
A
=
vin 1 + A"
vout 1
"
vin
!
Example: follower
!=1 "
vout
A
=
vin 1 + A
Use A(j),
solve for 1+A = 0
No thanks!
gm1( rds2 rds 4 )gm5( rds5 rds8 )
A( j!) =
1 + j!2" (rds 2 rds 4 )Cg5 1 + j!2" (rds 5 rds8 )CL
][
Trouble!
Miller Effect
Impedance across inverting gain stage G
Reduced by factor equal to (1+G)
Z
Zin =
(1+ G)
1
Z=
sC
1
! Zin =
)3
s(1
14
+2
G4
C
C eq
Miller Compensation
Need effect of large capacitance
Use Miller effect to multiply small on-chip
capacitance to higher effective value
Effect of large capacitance
without die area cost of large capacitance
New schematic
Add CC across 2nd stage
"Phase margin"
How stable is new
transfer function?
Phase margin =
Phase lag at |A| = 1
minus (-180)
gm1(rds2 rds 4 ) A2
A(j! ) "
!(rds2 rds4 )A2CC
A(j! ) = 1 at ! T
gm1
!T "
CC
Slew rate
I= C dV/dt
Only limited current IBIAS available to charge,
discharge CC
Slew rate
I= C dV/dt
dV
dt
IBIAS
CC
Summary Op-amp:
Stability
Compensation
Miller effect
Phase Margin
Unity gain frequency
Slew Rate Limiting