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A New Frontier in Ultralow Power Wireless Links:

Network-on-Chip and Chip-to-Chip Interconnects
Soumyasanta Laha, Student Member, IEEE, Savas Kaya, Senior Member, IEEE,
David W. Matolak, Senior Member, IEEE, William Rayess, Student Member, IEEE,
Dominic DiTomaso, Student Member, IEEE, and Avinash Kodi, Senior Member, IEEE

AbstractThis paper explores the general framework and

prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in
the context of micro power wireless design. HPC interconnects demand very high ( 10 Gb/s) transmission rates using
ultraefficient ( 1 pJ/bit) transceivers over extremely short
( 100 cm) ranges. In an attempt to design such wireless
interconnects, first a model for the wireless communication
channel properties is developed. The use of CMOS-based energyefficient onoff keying (OOK) transceiver architectures operating
in the 6090 GHz bands is considered as a practical solution.
In order to address strict performance requirements of wireless
HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative
circuits based on novel double-gate MOSFETs (DG-MOSFETs)
are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using
common source (CS) inductive degeneration with 32 nm DGMOSFETs is investigated by quantitative analysis and simulation.
The proposed inductor-less two-stage cascode cascade LNA is
optimized for 90 GHz operation and has the advantage of gain
switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power
efficient and faster. As further examples of efficient and compact
DG-MOSFET circuits for OOK transceiver design, a three-stage
CS 5 dB tunable power amplifier operating up to 90 GHz, and
a novel 90 GHz voltage controlled oscillator are also presented.
This is followed by the proposal of an array of four monopole
antennas studied using full-wave EM solver.
Index Terms90 GHz, antenna, channel modeling, CS
inductive degeneration low-noise amplifier (LNA), double gate
MOSFET (DG-MOSFET), gain switching, LC oscillator, power
amplifier (PA), wireless network on chip.

I. I NTRODUCTION

NE of the most distinguishing features of the twenty-first

century integrated electronics has been the proliferation

Manuscript received March 28, 2014; revised August 7, 2014; accepted

November 15, 2014. Date of publication December 11, 2014; date of current
version February 16, 2015. This work was supported by the NSF Award
under Grant ECCS-1129010. This paper was recommended by Associate
Editor J. Henkel.
S. Laha, D. DiTomaso, and A. Kodi are with the School of Electrical
Engineering and Computer Science, Ohio University, Athens, OH 45701 USA,
(e-mail: {sl922608,kaya,dd292006,kodi}@ohio.edu).
S. Kaya is with the School of Electrical Engineering and Computer Science,
Ohio University, Athens, OH 45701 USA (e-mail: kaya@ohio.edu).
D. W. Matolak and W. Rayess are with the Department of Electrical
Engineering, University of South Carolina, Columbia, SC 29208 USA,
(e-mail: matolak@cec.sc.edu, rayess@email.sc.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2014.2379640

Fig. 1. Ultrashort range high-fidelity micro-power wireless interconnects

can have dramatic impacts on a number of integrated applications and HPC
systems.

of wireless connectivity and explosive growth of multifunctional and portable systems utilizing sub-10 GHz
communications. Extrapolating this trend to next decades, it is
obvious that there is a compelling need for even higher bandwidths and data rates, ultralow power in yet more capable
systems connected in very short length scales (see Fig. 1).
This is especially true for rapidly evolving integration of
circuits and systems on flexible and organic substrates for
wearable and implantable electronics, many-layer sensor networks, many-core computers, data centers, and internet of
things just to point out few. Moreover, creative and judicious
use of high-speed ultrashort (< 100 cm) range wireless links
in these highly integrated platforms are expected to provide
not only significant reduction in complexity and size, but also
improvements in efficiency, reconfigurability, fault tolerance,
and overall performance [1].
In many of the existing and promising applications utilizing the inherent flexibility and advantages of wireless links, the
power is scarce or even absent all together so it must be scavenged from the ambient energy sources. Thus, the ubiquitous
use of wireless connectivity in embedded and distributed electronics systems invariably implies massive challenges in terms
of low-power design. Moreover, in most cases, notably in sensor networks, the link range is an equally important concern
that determine overall design targets. Yet, perhaps luckily, the

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LAHA et al.: NEW FRONTIER IN ULTRALOW POWER WIRELESS LINKS: NETWORK-ON-CHIP

data rate and bit-error-rate (BER) are fairy low (< 10 kbps and
< 103 , respectively) in many such scenarios. In other words,
the peak power usage and power efficiency for per unit of
transmission length (W/m) may be considered as most important performance metrics and often the quality of transmission
is not detrimental. Also true in such cases, as in bio-medical
implants or mobile sensors, is the fact that there is not a
competing alternative or established gold-standard to beat.
In this paper, we focus on a new and different frontier, and arguably a more challenging design task: ultralow
power (< 1 mW), extremely high-performance (> 10 Gb/s),
and high fidelity (BER < 1012 ) wireless links for on-chip
and off-chip data transfer at ultrashort (< 10 cm) ranges. As
also indicated in Fig. 1, these parameters pushes all design
targets to beyond what is possible today. Both the antenna
size and data throughput necessitate the use of extremely high
frequencies, reaching up to THz range. In this new frontier for
micro-power (power) transceiver design, not the power efficiency over link range but the energy efficiency per transmitted
bit and very low error rates become the essential delimiters.
This is because the existing solutions are based on wired links
that are extremely efficient and robust competitors that must
be outdone. In other words, it is not sufficient to build a good
link, but the designers are posed with a problem to actually
build a better-than-wired link.
Interconnects in multicore high-performance computing (HPC) architectures are the main drivers of such seemingly
incompatible design requirements even though intraroom multimedia and mobile data cloud applications are also potential
beneficiaries. In the case of HPC solutions, the need is many
fold: both on-chip (intercore) and off-chip (chip-to-chip and
board-to-board) use can be envisaged. Since HPC systems
of today are limited primarily by the interconnect performance, wireless interconnects are a potential solution that
can provide energy efficient communication, while providing
high bandwidth and low latency, especially between multiple
cores [2][7] and memory banks. The other unique and specific benefits of wireless interconnects for HPC systems may
include the following.
1) High
energy
efficiency
for
long,
one-hop
communication.
2) Reduced complexity compared waveguides or wires.
3) Compatibility with CMOS wireless technology designs.
This paper is intended to serve two orthogonal purposes.
On the system level, it is structured to define a general
framework and parameters that would be demanded from
power transceivers in this new frontier, including the context and requirements for HPC systems, media access channel (MAC) and infrastructure design for the communication
layer as well as the technological basis for the challenges
introduced. On the device and circuits level, it comprises a
number of hitherto unexplored and novel, ultracompact, and
tunable 90 GHz low-noise amplifier (LNA), power amplifier (PA), and voltage controlled oscillator (VCO) circuits
based on double-gate MOSFETs (DG-MOSFETs) as well as
antenna structures believed to be applicable to building systems in the introduced framework. Hence, this paper attempts
to explore the complex task of designing on-chip wireless

187

interconnects within realistic constraints at all levels including

the system/architecture, communication medium, and antennas as well as circuits and devices that are completely
novel (LNA/VCOs) or have been completely redesigned for
ultralow power operation at 90 GHz.
The structure of this paper is as follows. A general description of the wireless interconnects for HPC systems for on and
off-chip communication is introduced in Section II. This is
followed by a description of the general context for medium
access and channel modeling perspectives required for the
design of efficient, ultralow BER, and short-range power
OOK transceiver in Section III. The feasibility of reverberation chamber model for the dispersion loss of the wireless
channel of the on chip interconnect is also analyzed with the
computation of root mean square delay spread (RMS-DS) in
this section. Section IV deals with the DG-MOSFET device
and subsequently Section V deals with the design of proposed
novel 90 GHz DG-MOSFET LNA and VCO circuits along
with a wideband PA circuit operating at the same frequency, as
examples to how novel nano-scale CMOS devices can impact
mm-wave IC design. This paper concludes with a pilot study
in Section VI that introduces full-wave simulations of a fourmonopole antenna array that can be used for both on and
off-chip wireless interconnects.
II. W IRELESS I NTERCONNECTS FOR HPC
As transistors continue to scale down, the number of cores
that can be integrated on the same chip has continued to
increase. This increase in core count is driven by the high
demands of multithreaded and HPC workloads. Cores communicate through the interconnection network which connects
cores and other I/O devices both at the on-chip and off-chip
levels. Conventional electrical interconnects suffer from high
latency due to limited off-chip bandwidth and dissipate ten
times more energy to communicate than to compute a floating point operation [8]. Potential solution for interconnects
include emerging technologies such as wireless and photonic
interconnects.
The potential benefits of wireless link over wired have
already been discussed in Section I. To analyze, it can be
observed that as wire distance increases, both the resistance and capacitance of the electrical links also increases.
Additionally, electrical links require repeaters made up of several inverters in order to propagate the electrical signal. Both
wire distance and repeaters contribute to electrical link energy
per bit. Therefore, at long distances electrical wires have both
high latency and energy. The energy per bit for three interconnect technologies: electrical, wireless, and photonic can be
observed from Fig. 2. The energy per bit estimates for electrical and photonic interconnects were calculated using the
DSENT modeling tool in 45 nm technology [9]. The estimate
for the wireless energy was estimated using trends in wireless
interconnect technology available from [10]. As shown in the
figure, wireless interconnects are assumed to have a low energy
per bit of about 1 pJ/bit at up to 20 mm. Wireless interconnects
have an energy per bit advantage over electrical links past
a distance of approximately 10 mm. Photonic interconnects

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 2, FEBRUARY 2015

Fig. 2. Energy per bit for three interconnect technologies: electrical, wireless,
and photonics.

have a low energy per bit of approximately 0.17 pJ/bit, however, this does not include the laser energy as well as losses
due to components such as splitters. Incorporation of these
hidden costs would significantly erode the advantage of
photonics in Fig. 2, making wireless solutions especially favorable until low-power, compact, and low-cost lasers can be
built on Si substrates. Therefore, wireless interconnects have
both technology and energy advantages over other interconnect
technologies, especially beyond 10 mm of electrical length.
In addition to energy, both latency and bandwidth are
important factors for interconnect technologies. Since wireless
signals propagate near the speed of light, data can be sent chipto-chip in one clock cycle after the signal has been modulated
and sent to the transmitting antenna. Electrical links, on the
other hand, can take 34 cycles to transmit 20 mm across chip
and several hundred cycles to transmit off-chip. In terms of
bandwidth, wireless interconnects are limited by the frequency
spectrum [11] which in turn limits the available bandwidth
for communication. Electrical links can achieve an increase of
bandwidth by adding additional wires or increasing the clock
rate incurring either an area or energy penalty. Overall, wireless interconnects have a limited bandwidth but a better energy
efficiency and latency at long distances (> 10 mm) compared
to electrical links. Therefore, wireless interconnect technology
can be used as a supplement to electrical interconnects to provide long distance communication at low energy and latency.
Hybrid network-on-chip architectures, which use both wireless and wired links, have been studied on various topologies
and shown to improve performance and energy [7], [12], [13].
Fig. 3 shows a proposed wireless HPC interconnect that combines processing elements (PEs), memory controllers (MCs),
memory, and interboard traffic managers. Wireless channels
can directly connect to other cores on different system boards
or to MCs that can directly reach DRAM chips thereby
reducing both the bandwidth and energy consumption issues.
III. MAC L AYER D ESIGN FOR HPC
W IRELESS L INKS
A. Frequency Band Selection
To take advantage of wireless interconnects for HPC
systems, data rates must be highon the order of 10 Gb/s

Fig. 3.
Proposed wireless HPC interconnect that combines PEs, MCs,
memory, and interboard traffic managers.

per link. In addition, multiple links are required, spanning

a range up to 100 cm. These implies carrier frequencies
well above 10 GHz for multiple channels in a frequency
division arrangement. In the spirit of newly developed
IEEE standard 802.11ad for short range indoor communications, we consider in this paper 60100 GHz as the
target band for the short term, CMOS compatible solutions.
However, in the long-term power solutions in the 150500
GHz, and above 500 GHz may be needed, utilizing hybrid
SiGe BiCMOS and/or IIIV [14][16]. Clearly, the higher
one goes in frequency, the larger the available bandwidth and
smaller the antennas. Moreover, channel modeling can employ
simplified high-frequency methods with greater accuracy. Yet,
as the frequency increases, design of power circuits may
become even more challenging and complex since use of
pure CMOS technology for the transceivers becomes almost
impossible. In the 150500 GHz band, where THz CMOS is
headed [17] and the bandwidth is still sufficient, the channel
modeling becomes more complex, and small antennas less
efficient. However, inefficient near-field antennas may be
tolerable due to ultrashort ranges involved. Hence, until
Si-based CMOS mm-wave solutions are fully developed in
the next decade to reach 150500 GHz operation, the only
option is to utilize the current CMOS mm-wave circuitry
capable of reaching up to 100 GHz operation. Therefore,
100 GHz technology is the natural development platform for
wireless HPC interconnects despite the inefficient antennas
and complex channel modeling that requires full-wave electromagnetic solutions, until THz CMOS is mature and widely
available.
B. Channel Path Loss and Dispersion
In terms of the channel itself, attenuation, or path loss,
increases with frequency, which requires either higher transmission powers or directional antennas or shorter links as
one increases frequency. The other significant channel effect
delay dispersionwill depend strongly on the actual on-chip
and off-chip (chassis) landscape, and it is difficult to say anything quantitative as a function of frequency for this effect.
Moreover, antenna design is most challenging at the lowest frequencies, because the severe wireless network on chip

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189

physical size constraints may force antennas to be electrically

small at lower frequencies. Electrically small antennas generally implies inefficiency, and with the short link distances,
near-field effects can pertain, and this will create interference
and mutual coupling among antennas.
Two potential path loss models in [7] and [18] are applicable to the problem at hand. As is common in terrestrial settings,
these models take a log-distance form, where path loss L in
dB at distance d is given by
L(d) = A + 10nlog10(d/d0 ) + X

(1)

with A the path loss in dB at a reference distance d0 , d > d0

the link distance, n the dimensionless propagation path loss
exponent, and X a zero mean Gaussian random variable in dB
with standard deviation x . Reference distance d0 is chosen for
convenience and within the far field of antennas; n = 3 or 4 is
common in cellular settings when no line-of sight path exists,
and n = 2 in an obstacle-free vacuum. For HPCs, d0 could
be on the order of 1 mm or so. From plots in [7], we have
estimated n = 1.98, d0 = 1 cm, and for polyimide, A = 44.6
dB, and for silicon, A = 79.6 dB. The applicable distance
range is 1100 cm (so here, d0 can be less than d). Hence,
assuming a deterministic model (ignoring X) the path loss can
be estimated using the equation above.
The dispersion in HPC interconnects can be studied using
the reverberation chamber model as an approximation. This
assumes the wireless links are contained within a conducting box. The RMS-delay spread (DS), denoted , is then
computed given some material parameters for the reverberation chamber in terms of several quality (or Q) factors as
follows [19]:
1

= 
2 fSQ

(2)

where SQ is the sum of reciprocals of the various Q-factors,

taking into account the presence of any electromagnetically
absorptive material, chamber apertures, conductive wall properties, and antenna sizes. The aperture Q is the only pertinent
if there are large openings in the chamber walls; hence, for our
closed-box estimates, we need only use the wall and antenna
factors [20], given by Qwall = 3V/(2r S), and Qantenna =
16 2 V/(m3 ), where V is cavity volume (d d h), S is
surface area (2d2 + 4hd), r = w /0 is the relative wall
permeability, with w , the actual wall permeability and m0 ,
the permeability of free space, m is the antenna impedance
mismatch factor (= 1 for a perfect
impedance match), and
is the skin depth, given by 1/ f w w with w the wall
conductivity. For nonferric materials, we can assume w = 0 .
For an air-filled cavity, we show in Fig. 4 an example plot
of the delay spread in nanoseconds versus frequency from
300 GHz to 100 THz, for copper and aluminum conductors,
and for d = 20 mm and several values of h. As noted in [19],

the functional form of the plots are approximately 1/ f .

Clearly, the parameters in this figure are relevant only for onchip wireless links and similar plots can be generated for other
distances and frequency ranges of interest.
For cavities filled with dielectric (lossy), the delay spreads
will be smaller, since the propagating waves get attenuated

Fig. 4.
RMS-DS versus frequency for micro reverberation chambers
representing the case for on-chip wireless interconnects.

with each path from wall-to-wall within the chamber

(i.e., we add Q1
absorber > 0 to SQ ). Thus, the results in Fig. 4
can be viewed as upper bounds for this model. The largest
RMS-DS occurs at the lowest frequency, and for the largest
cavity size (h = d/5). This delay spread value is approximately 5 ns, but this chamber height is likely unrealistically
large. If we assume that the h = d/100 case is representative, the maximum RMS-DS is 0.6 ns at f = 300 GHz. A
convention in communication systems is to declare a channel
nondispersive if the RMS-DS is less than one-tenth of a symbol duration [21]; in general, the larger the RMS-DS, the lower
the distortion-free data rate. The 0.6 ns delay spread implies
a minimum symbol duration of Ts = 6 ns, and this would
then correspond to a maximum symbol rate Rs = 1/Ts
= 167
Msymbols/s (167 Mb/s if binary modulation).
This is an extremely low (i.e., uncompetitive) data rate for
HPC systems, but note that the reverberation chamber analysis
is a worst case one in terms of delay spread. As noted, the
delay spreads would be substantially smaller if a lossy dielectric were within the cavity instead of air, and as frequency
increases, delay spread also decreases; for example, if we used
f = 40 THz, the maximum RMS-DS would drop by an order
of magnitude, yielding a data rate of 1.67 Gsymbol/s by our
previous rules. Operation at such frequencies is not currently
practical, and this value is only provided as an example based
on the very rough estimates of Fig. 4. Note also that the very
low error probabilities required of HPC interconnects ( 1012
for wired links [7]) would likely require even smaller values
of dispersion unless some higher-layer error correction could
be applied. Sophisticated forward error correction coding and
decoding could dramatically reduce error probability, but this
would be at the expense of throughput and latency, plus circuit
area and power, and like equalization, error correction at rates
of multiple gigabits per second is not trivial with present-day
devices.
Although the reverberation chamber analysis is clearly quite
pessimistic, the degree of pessimism in the result is difficult to quantify precisely without more sophisticated analysis
and landscape specification. As another idealized example,
if we assume d = 20 mm and h = d/10, the two-ray
model [22] yields a maximum delay spread of approximately

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(a)

Fig. 5. Generic architecture of the OOK transceiver proposed for the HPC
wireless routers with four channels operating at 10 Gb/s centered around
85 GHz.

(b)
Fig. 7. (a) Generic DG-MOSFET device structure. (b) ID -Vfg characteristics
of an n-type independent and common mode DG (Vbg = Vfg ) transistors.
Inset: resulting shift in the front gate threshold.

Fig. 6. Wireless radio signal power required by different data rates (Tx/Rx)
and distances (Tx only) in OOK architecture for a BER = 1012 in free
space.

2 ps, corresponding to a maximum symbol rate on the order

of 50 Gsymbols/s, a very competitive for HPC systems. These
two examples illustrate the enormous range of possible WiNoC
delay spreads, which depend on the environment. Such results
are clearly initial ones, and more work is required to increase
the accuracy of delay spread estimates.
C. Modulation Scheme and Link Budget
The generic architecture of the wireless transceiver proposed for iWISE implementation [12] can be observed from
Fig. 5. The transceiver uses onoff keying (OOK) since the
simplicity of this noncoherent modulation technique leads to a
very low power consumption as well as ultracompact architecture. We target ultralow power operation (< 1 pJ/bit) as well
as ultrashort ( 2 cm) range, based on 100 GHz RF-CMOS
technology and on-chip antennas.
Another important consideration for the design of power
wireless channels for the HPC interconnects is the careful
analysis of the signal budget. In order to determine the appropriate signal levels and the required amplification levels, a
link-budget analysis is presented in Fig. 6. According to this
figure, which considers losses in air and a 10 dB error margin, typical signal levels for a 30 Gb/s link over 1 cm is below
13 dBm. It is clear that different power levels are required
for different link ranges (in order to attain the maximum
allowable BER). Thus, power levels and required technology
parameters to achieve them must be tuned for the specific conditions that pertain. According to Fig. 6, the signal power is
a stronger function of the distance than the data rate, therefore the gain tuning in the LNA/PA circuits may substantially

lower overall power dissipation. However, the transmission

losses and interference affects must be more precisely
evaluated, once antenna technology and full-3-D architecture is
determined.
IV. DG-MOSFET D EVICES
Novel devices that are the product of the final decade
of CMOS downscaling can endow CMOS mm-wave circuit
engineering with many exciting possibilities. For instance,
sub-22 nm MOSFETs built on silicon on insulator (SOI)
substrates with ultrathin channels and precisely engineered
source/drain contacts have been replaced by 3-D-engineered
multigate devices [23], [24]. Such multigate MOSFET architectures can efficiently control the channel from multiple
sides instead of the top-side in planar bulk MOSFETs. The
ability to alter channel potential by multiple (e.g., double,
triple, cylindrical) gates provides a relatively easier and robust
way to control the channel electrostatics, reducing the short
channel effects (SCEs) and leakage concerns considerably.
While multigate SOI structures are well recognized for digital performance [25], [26], they are also strong contenders for
mm-wave applications in rapidly expanding wireless communications market [27].
Being simpler for 3-D structural optimization and relatively easier to fabricate as compared to other MOSFET
structures (MIGFET, -MOSFET, tri-gate, and so on), the
DG-MOSFET architecture, Fig. 7(a) is chosen for the simulation study exploring the potential of multigate devices
for mm-wave analog applications. Such a structure can be
built using a modified (two gates separated and independently
accessed) FinFET device architecture and is also referred to
as independent-gate FinFET. Although it requires additional
routing for the second (back) gate connection, the functionality
gained by this second independent gate bias certainly makes

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191

this analysis. Also, gmf = gmb = gm , since the DG-MOSFET

is considered to operate in common mode configuration
(two gates are joined). Therefore, the current law can be
modeled as
VS
.
(4)
2(Vin VS )sCgs + 2gm (Vin VS ) =
Z
After arrangement, we have
VS
=
Vin
Fig. 8. Small signal equivalent of the DG-MOSFET for the CS inductive
generation topology.

this complexity worthwhile, for a tunable architecture such as

this that can trade-off between power and gain. The simulations are performed with Synopsys HSPICE RF using the ASU
PTM FinFET models [28]. The typical transfer characteristics
of an n-type DG-MOSFET for both common mode (two gates
are joined) and independent mode (two gates are disconnected)
operation are shown in Fig. 7(b).
The advantages of DG-MOSFET as a device over conventional CMOS can be summarized as follows.
1) Excellent control of SCEs due to presence of two gates
and ultrathin body.
2) Lower subthreshold leakage current due to reduced SCE.
3) Higher ON (drive) current due to two gates.
4) Reduced gate leakage, as afford to use thicker gate oxide
due to control from two gates.
The above advantages are primarily applicable to the
common (symmetric) gate operation. When applied to construct different circuits in this mode many other advantages
come into sight. One such is demonstrated here with the
LNA design. On the other hand, the advantages entitled to
the independent mode primarily materialize through circuit
applications and are as follows.
1) Implementation of tunable circuits.
2) Circuits with reduced transistor count.
The DG-MOSFET LNA designed in this paper, operate in
both common mode and independent mode operation. The
common mode advantage has been put forward by a quantitative analysis of area efficiency while the independent mode
operation has the advantage of gain switching by incorporating
back gate tuning. These are described in the next section.
V. DG-MOSFET MM -WAVE C IRCUITS
A. Quantitative Analysis: DG-MOSFET CS Source
Degeneration LNA
The small signal model of CS cascode source degeneration
with DG-MOSFET is depicted in Fig. 8. Solving Kirchoffs
current law at node S, we get
(Vin VS ) sCgfs + (Vin VS ) sCgbs
VS
.
(3)
Z
The DG-MOSFET considered here is a symmetric device,
and therefore, we can safely assume Cgfs = Cgbs = Cgs in
+ gmf (Vin VS ) + gmb (Vin VS ) =

2sCgs + 2gm
1
Z

+ 2sCgs + 2gm

(5)

The input current, Iin can be written as

Iin = sCgs (Vin VS ).

(6)

The input impedance (Zin = Vin /Iin ) is thus

Zin =

sCgs 1

VS
Vin

.

(7)

Inserting the value for VS /Vin from (5) in the above equation
and after a few steps of arithmetic, we obtain the following:
Zin =

1
2Zgm
+ 2Z +
.
sCgs
sCgs

(8)

Replacing Z by sLS , the input impedance is rewritten as

Zin =

1
2gm LS
+ 2sLS +
.
sCgs
Cgs

(9)

The last term of (9) is the resistive term and of our interest.
The other two reactance terms resonate and cancel each other.
The factor 2 in the term is absent in design with conventional
CMOS [29]. Now, the value of source degeneration inductor,
LS , in the last resistive term of (9) should be chosen in a
manner such that it equals or approaches 50  impedance to
match the impedance of the 50  antenna. As earlier informed,
the factor 2 present in (9) for DG-MOSFET, is absent in the
design with conventional CMOS. This implies, the value of LS
can be half in DG-MOSFET when compared to design with
CMOS to achieve the 50  impedance matching. At this stage,
we have ignored the role of the transit frequency.
Now it is known, the expression gm /Cgs in the resistive term,
is the transit frequency (T ) of the device, and therefore, a constant for a particular device. The T of DG-MOSFET is almost
equal to its single gate counterpart for channel lengths of 75
nm and above while it is higher for channel lengths shorter
than 75 nm owing to the good gate control on the channel and
reduced SCE [30]. As can be observed in [30], for channel
lengths lower than 50 nm, the T of DG-MOSFET is almost
three times to that of single gate CMOS. Therefore, the above
statements confirm the inductance, LS , in DG-MOSFET can be
a sixth to that of single gate CMOS in a CS inductive degeneration topology to achieve the same 50  input impedance
for antenna power matching for an LNA. We have [31]
LS N 2

(10)

and from a fair approximation

AN

(11)

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Fig. 9. Basic CS cascode source degeneration LNA in both the CMOS and
DG-MOSFET technologies for area analysis.

implies
A


LS .

(12)

Here, N is the number of turns of inductor and A is

the physical layout area of the inductor. From the above
proportionality

ACMOS
LS(CMOS)
=
.
(13)
ADGMOSFET
LS(DGMOSFET)
Considering the inductance value of CMOS to be six times
that of DG-MOSFET from aforesaid explanations coupled
with (13)
ACMOS
ADGMOSFET

2.5.

(14)

Therefore, the area occupied in the CS inductive degeneration topology by a CMOS is nearly 2.5 times more than that
of DG-MOSFET.
Now considering a basic cascode CS inductive degeneration
LNA that consists of three inductors [29], the total inductor
area of the LNA in CMOS is 7.5AL while in DG-MOSFET it is
6AL (Fig. 9). The area of inductors L1 and L2 in both the technologies are considered to be same and the area of inductor
LS in CMOS is taken to be 2.5AL versus AL in DG-MOSFET
following (14). Hence, the LNA area (based on inductor size)
in DG-MOSFET design can be decreased by almost 20% when
compared to single gate CMOS. It should be noted as the
inductor is the major occupier of area in mm-wave circuits,
with several orders larger in magnitude than that of the active
and other passive devices, the above figures can be accepted to
verify the DG-MOSFET to be a viable alternative to conventional CMOS for area efficient mm-wave LNA designs in this
CS inductive degeneration topology. The inductor geometry
considered for the analyses is spiral.
B. Microstrip TL Inductors
LNA designed at mm-wave frequencies such as at 90 GHz,
generally incorporates transmission lines to substitute on
chip inductors or on chip transformers. This is because,
although not impossible, it is quite difficult to build on
chip inductors for circuits operating at mm-wave frequencies.

Fig. 10. Inductance versus microstrip aspect ratio (w/h) at l = 50 m.

Inset: resulting characteristic impedance of the microstrips TL on alternative
substrates.

Also, at microwave frequencies, the conventional lumped components cannot work as their desired performance as an
inductor or capacitor is significantly dwarfed by the undesired
device parasitics, hence replaced by microstrip transmission
lines.
Considering the above reasons, we adopt microstrip transmission lines to substitute inductors in our 90 GHz mm-wave
LNA design. The microstrip transmission line is a transmission line geometry with a single conductor trace on one side
of a dielectric substrate and a single ground plane on the
opposite side (inset: Fig. 10). These structures achieve inductance with the flow of current in the conductor, whereas the
capacitance is associated with the conducting strip separated
from the ground plane by the dielectric substrate [32]. The
dielectric substrate considered in this paper is GaAs. In the
layered structures, microstrip transmission lines and coplanar
waveguides are commonly used as the transmission lines.
Although microstrip structures have lower Q-factor when
compared with the coplanar wave guides, they have less coupling between the adjacent lines and are easier to layout and
integrate [33].
The inductor in question can be formed by shorting the
microstrip center conductor to the lower level ground plane
at one end of the transmission line. This results in an inductance which, for a given geometry and in a specified frequency
range, is mostly independent of frequency [34]. Moreover,
the microstrip transmission line provides an inductance which
could be used on any type of substrate, with either low or high
resistivity. Beyond the III-V technology, it is worth mentioning that micro-strip inductors can have big impact in silicon
CMOS platforms since they could utilize two or all of the
metal wiring levels, allowing a wide range of inductance and
quality factor design tradeoffs. An important feature in this
trade-off is the ability to utilize lower (below the inductor)
metal wiring levels, as well as lower silicon and polysilicon
areas for other than inductor design purposes, without affecting
the operation of the inductor. Thus, silicon RF-CMOS circuits
and its evolution to DG-MOSFETs/FinFETs are also well positioned to take advantage of this technique as a way to save
area and reduce parasitics.

LAHA et al.: NEW FRONTIER IN ULTRALOW POWER WIRELESS LINKS: NETWORK-ON-CHIP

Fig. 11. DG MOSFET-based LNA in common source cascode configuration.

Transistors MN1 and MN2 operate in the symmetric mode while MN3 and
MN4 operate in the independent mode with the back gates used for dynamic
tuning.

The microstrip characteristic impedance, Z, and the inductance, L, are computed as follows:


 2

0
h
h
1

log F + 1 + 2
(15)
Z=
2
0
e
w
w


Z
2 l
L=
sin
(16)
2 f

where, F &
e are obtained from expressions in [35]. To illustrate the design process and serve as example, the impedance
of the microstrip transmission line is plotted for different
substrates along with GaAs in the inset of Fig. 10.
At 90 GHz, the free-space wavelength (0 ) is 3.3 mm.
The wavelength in GaAs substrate is given by GaAs =

(0 /
GaAs ). Considering
GaAs to be 10, GaAs is given
as 1 mm. As the length of the microstrip transmission line
considered for realizing the inductance is in the range of
30 m, which is nearly 3% of the wavelength, we can justify
l GaAs . Hence, (2) can be rewritten as
L=

Zl
.
f

(17)

Considering this equation the inductance L is plotted for

different aspect ratio (w/h) of the microstrip transmission line
as shown in Fig. 10.
C. LNA Design and Gain Switching
The LNA implemented with DG-MOSFET, is demonstrated
here with the design of the circuit as shown in Fig. 11, consisting of four DG-MOSFETs in a two stage cascade common
source inductive degeneration cascode topology. This is a modified design following the LNA implemented in 90 nm CMOS
technology [36]. The common source transistors MN1 and
MN2 operate in the symmetric mode while the two transistors
MN3 and MN4 are configured for independent mode operation.
The transistor MN3 in common source topology is connected
to MN4 in cascode configuration. The transistor MN4 acts in
common gate configuration. The width of MN1 is taken to be
1 m while the width for transistors MN3 and MN4 are kept

193

higher at 2.4 m for better input return loss and optimized

gain performance. The supply, VDD is kept constant at 1.2 V.
MN3 is biased at 1 V (Vb ). The back gate of the transistors
MN3 and MN4 are biased for gain switching.
The series peaking circuit consists of an inductive
load, T2 , implemented with transmission lines that allows
for low voltage operation and resonates with the interstage
capacitance, C1 , enabling a higher operating frequency [29].
The inductor T1 , implemented in transmission lines is set to
resonate with the gate source capacitance of MN1 . The source
degeneration circuit consisting of T4 yields (in real part) wide
band impedance matching to maximize the interstage power
transfer. The MTL T5 tunes out the middle pole of the cascode,
thus compensating for the lower fT [37] of DG-MOSFET
which is nearly 160 GHz at 32 nm.
The variable voltage bias introduced in the back gate of the
two cascode transistors MN3 and MN4 implements the gain
switching operation of the DG-MOSFET LNA. The two cascode transistors are considered for the gain switching primarily
because the cascode here is not a part of the input transistor
at the first stage as can be seen from Fig. 11. The variation
of the back gate voltage of a transistor alters the gm of that
transistor. The change in gm in turn affects the input matching
of the LNA, which should ideally be unaffected for maximum
power transfer and minimized reflection losses between the
antenna and the LNA. The cascode switching is also attractive because it reduces the current flowing through the load
by a well defined ratio that aids in the achievement of small
gain steps, which is yet another important issue that must be
taken into consideration. As observed in the next section, the
small step size considered in the biasing of the two transistors also assist in attaining the small gain steps. Therefore,
the back gate bias should not be applied at the input transistor
at the first stage (MN1 particularly) which plays the crucial
role of impedance matching in this CS inductive degeneration
LNA. Another valid reason of not applying the bias to the
input transistor is to avoid the thermal noise arising out of
the transistor which can degrade the LNA noise figure when
gm is high.
On the contrary, in LNA implemented with conventional
CMOS, the gain switching is usually achieved with the addition of extra transistor(s) that alters the total transconductance
of the transistor which in turn alters the gain. The added transistor that essentially acts as a switch can degrade the original
speed of the LNA operation. Therefore, the DG-MOSFET
based LNA gain switching is advantageous over its CMOS
counterpart since it does not require any additional hardware
and therefore results in no supplementary delay. Moreover, the
power consumption attributed to switching of transistors in the
conventional CMOS is significantly reduced in DG-MOSFET
based design. The LNA dissipates 12.1 mW of power for a
back gate bias of 0.7 V. The noise figure in the DG-MOSFET
circuit also improves with the absence of these extra switching
devices.
D. Simulation Results
The simulation shows the 3-dB bandwidth to be 20 GHz,
ranging from 80 to 100 GHz. The forward gain (S21 ) achieves

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 2, FEBRUARY 2015

Fig. 12. Gain (S21 ) of the LNA varies with Vbg . This is measured for
Vbg = 0.20.7 V.

Fig. 13.
Input and output return losses of the LNA (S11 and S22 ) for
different Vbg . S11 remains the same for all back-gate biases.

a peak value of 17 dB at 90 GHz for Vbg = 0.7 V (Fig. 12).

Beyond this maximum operating voltage, the gain gets saturated and is independent of Vbg . The peak gain reduces
gradually as Vbg is reduced and drops to 12.5 dB for
Vbg = 0.2 V. The power dissipated (Pdc ) by the LNA also
varies with Vbg , reaching 12.1 mW at Vbg = 0.7 V. The reflection losses (S11 and S22 ) obtained from the same simulations
are shown in Fig. 13. The additional gate maintains nearly
the same input matching while the gain is switched without
any additional hardware/physical resistance. The LNA noise
figure (NF) depends upon the back gate bias, dropping to a
minimum at peak gain as expected. At 90 GHz, it ranges from
6.8 dB at Vbg = 0.7 V to 7.5 dB at Vbg = 0.2 V (Fig. 14).
Clearly, the back gate tuning provides a convenient tool to
optimize specific device performance parameters, setting up
unique trade-offs such as that between power and gain.
The proposed LNA is unconditionally stable in the operating frequency range, as can be seen from the simulated
rollet stability factor, i.e., K > 1 (Fig. 15) (also,
< 1
from easy computation) [29]. The circuit is also simulated
for linearity performance using a two tone frequency analysis near 60 GHz and the observed maximum third-order input
intercept point (IIP3 ) is 5.0 dBm (for 0.2 V) as shown in
Fig. 16. The linearity does not vary considerably because

Fig. 14. Noise figure dependence on Vbg of the LNA is evident. The NF
changes marginally in the tuning range of Vbg at 90 GHz.

Fig. 15. Value of K > 1, as one of the necessary condition indicates the
unconditional stability of the circuit.

Fig. 16.

Computed IIP3 is 5 dBm at Vbg = 0.2 V.

of the source degeneration and the minimum is observed at

6.2 dBm (0.7 V). These parameters are compared against
some recent mm-wave LNA designs for different technologies (Table I) which include a recent work on a variable gain
LNA in 65 nm CMOS [42]. Table II lists the performance
trade-offs for different operating Vbg s among gain, NF, and
Pdc at 90 GHz for our design.

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195

TABLE I
P ERFORMANCE C OMPARISON OF D IFFERENT MM -WAVE LNA S

TABLE II
LNA P ERFORMANCE T RADE -O FFS FOR D IFFERENT Vbg S

Fig. 18.

Independent mode tunable DG-MOSFET LC oscillator.

150500 GHz range as the transistor-scaling reaches to 14 nm

level as foreseen by the ITRS roadmap (2011 edition). The
detailed analysis on this circuit can be observed at [43].
F. DG-MOSFET VCO

Fig. 17. Simulated response of three-stage PA circuit with tunable gain via
DG-MOSFET. Inset: circuit topology [43].

E. DG-MOSFET PA
Following similar principles of operation and design for
the LNA, DG-MOSFETs can also be used to build a class
A PA (inset: Fig. 17) [43]. The gain of this circuit can also
be tuned via the back-gate of the DG-MOSFETs used, which
can be used for adaptive wireless communication among the
multiple cores/chips in a typical HPC architecture. With the
signal levels determined from Fig. 6 for a particular data rate
and distance, one can alter the required gain for a given wireless link for power efficiency. Fig. 17 envisages the practicality
to carry out such a dynamic gain allocation within 5 dB using
32 nm DG-MOSFET devices up-to 100 GHz. As the current
DG-MOSFET transistor models are further improved, it should
be possible to extend the design of the PA operation into the

The LC VCO is another classic example of how

independent-mode DG-MOSFET can be utilized for compact
and more innovative circuits. The compact resonant LC VCO
implemented with a DG-MOSFET can be tuned via back gate
voltage bias to vary the oscillation frequency without any
requirement of a MOS varactor. This unique aspect has been
exploited for the design of the VCO of the 90 GHz transceiver,
as shown in Fig. 18.
Unlike the characteristics of the VCO implemented in single
gate CMOS with MOS varactors, the oscillation frequency in
the compact DG-MOSFET VCO decreases with increase in
voltage once the threshold (VT ) is reached (Fig. 19). This is
because the inversion charge density, Qi , varies proportionally
to Cox (Vbg VT ) in both the linear and saturation regions [44],
where Cox is the oxide capacitance. Therefore, as Vbg increases
beyond VT , Qi increases. The increase in Qi results in the
increase of the total gate capacitance of the back gate (Cbg ),
which in turn lowers the oscillation frequency, f . It should
be noted that beyond VT , Cbg only depends on Cox [44]. The
oscillation frequency beyond VT is given as
1

f =
.
(18)
2 L1 (C1 + Cbg )
A novel formulation can be devised for the characteristic of
the DG-MOSFET LC VCO which can be written as follows:
f = KDGVCO (Vbg VT ) + fc .

(19)

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 2, FEBRUARY 2015

Fig. 19. Frequency tuning with back gate bias for the independent mode
LC oscillator. Inset: output waveform of the DG-MOSFET LC oscillator
at 90 GHz.

The slope of the characteristic, KDGVCO , is termed the sensitivity of the VCO and is a negative quantity as can be observed
from the curve fitting of the oscillator characteristic in Fig. 19.
In the above equation, fc is the oscillation frequency in the subthreshold region of the back gate of the devices and is given as
fc =

1
.

2 L1 C1

(20)

The voltage response of the oscillator at 90 GHz can be

observed from the inset of Fig. 19.
The DG-MOSFET can actually be extended to incorporate
several other ultrapower ultra compact wireless components
that include OOK modulator, envelope detector, and RF mixer.
One can refer to [45] for the details on these novel designs.
More matured and definitive analysis can be attempted when
advanced commercial processes and more refined compact
models are available for DG-MOSFETs in the near future [46].
VI. C HANNEL C HARACTERIZATION
AND A NTENNA D ESIGN
The characteristics of the chip-to-chip channel will have a
profound effect upon wireless link performance [47]. Thus,
accurate models for these channels are required to specify channel bandwidths, modulation/demodulation schemes,
and any mitigations for channel distortion such as equalization (including transmitter prefiltering). One favorable aspect
of these channels is that they are essentially time in-variant.
Thus, one can develop a set of models that pertain to the
expected link distances among network nodes.
Another issue that must be addressed is interference. As
shown in [18] for the intracomputer-chassis environment, various clock and other signals (and their harmonics) inevitably
leak from components and are radiated from wired transmission lines. It is possible to characterize these signals via
experiment and through the literature, and develop our transmission schemes to account for this interference. The best
approach is to use spectral bands that are relatively free of such
signals, when possible. In the future, spread spectrum may be
used to suppress interference, but in the near term, we will
use interference avoidance and will investigate interference
suppression as needed via equalization.

Fig. 20. Conceptual illustration of four-monopole antenna arrays for onchip wireless interconnects. The main picture is the cross section of a single
monopole, while the inset shows the 3-D arrangement.

Any wireless channels characteristics are intimately related

to the antennas used at the transmitter and receiver. Hence,
our channel characterization will require concurrent antenna
design and optimization. Depending upon frequency band,
we may be able to use small arrays at the highest frequencies (several hundred GHz). The challenge there is impedance
matching and ensuring that manufacturing of such minute
structures does not cause appreciable deviation from physical
design parameters. Accounting for pattern-deforming effects
of nearby structures is also important.
To develop models for the channels, we make use of analysis to the full wave electromagnetics solvers (HFSS [48]).
One initial design we have explored is an array of antennas
above the top metallization layer of the chip. In the example,
here, we employ four monopoles above a ground plane that is
the top metallization layer of a chip. These antennas are fed
from beneath, allowing an antenna farm separate from the
transceiver electronics that reside in the lower IC layers. The
top metallization layer serves as a ground plane, and may be
covered by a thin layer of dielectric material such as silicon
dioxide or polyimide. Above the dielectric layer will be air,
and possibly also a casing. Fig. 20 illustrates the structure of
one of the monopoles and 3-D sketch of the entire model. The
entire chip is covered in a ceramic box (for thermal purposes),
and the monopoles are near the square surface corners.
Results obtained with HFSS for this four-monopole array
structure are shown in Fig. 21 in terms of the loss between
antenna pairs (insertion loss, in dB) versus frequency along a
side (16 mm) and a diagonal across 22.62 mm. If we declare the
bandwidth to be the smallest frequency span for which the loss
varies by at most 1 dB, bandwidths ranging from 46 GHz are
attained with this simple design. Note that the channels are not
at exactly 90 GHz, but would be centered as desired by slight
tuning of the antennas; channel bandwidths could also be considerably enlarged with the use of fixed equalizers. The ground
plane size is also exaggerated for expediting the numerical computations, hence more realistic results with ground planes of
actual size will not be quite as good.

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197

(insertion loss) is slightly less than that of free-space due to the

antenna gains, and the 10-dB return loss bandwidth is approximately 6 GHz for these simple antennas in the idealized closed
chamber conditions.
ACKNOWLEDGMENT
The authors would like to thank Ansoft Corporation for their
generous contribution.
R EFERENCES

Fig. 21. Insertion loss versus frequency for four-monopole arrangement with
90 GHz design frequency along the side-to-side and diagonal directions.

Our channel models can be used to explore tradeoffs among

potential modulation and equalization schemes, largely via
simulations. We are currently building an extensive modeling
and simulation environment that contains multiple dispersive
channel models to simulate our proposed wireless transmission and reception schemes and evaluate their performance.
This will be done concurrently with simulation of several
duplexing/MUX and MA schemes for the frequency bands,
data rates, and links of interest.
VII. C ONCLUSION
The significance of -power wireless links to build flexible and efficient interconnects in HPC systems has been
emphasized and explicated in terms of system, communication channel, and circuit design. The system and channel
requirements for the wireless interconnects have been underlined. In particular, the viability of nano-scale DG-MOSFETs
as an alternative to conventional CMOS devices in designing high-efficiency mm-wave circuits in wireless interconnects
is explored via a two-stage cascade LNA design primarily
intended for ultralow-power compact OOK transceivers. The
area and performance improvements in the proposed two-stage
cascode LNA based on 32 nm DG-MOSFETs with CS inductive degeneration is verified quantitatively and simulation,
along with its unique capability for dynamic gain switching, a
feature not found in conventional CMOS circuits without additional area and delay overhead. A comparative analysis shows
that the proposed LNA should have impressive performance
metrics that exceed the bulk MOSFET and even match SiGe
counterparts. The ultralow power dissipation ( 12.1 mW),
area efficiency, high frequency operation (90 GHz), a wide
3-dB bandwidth of the LNA (10 GHz) makes it ideally suited
for the OOK receivers where the power (gain) level may be
adjusted depending on the link distance via DG-MOSFETs
back gates. A three-stage PA operating up to 90 GHz as
well as a varactor less VCO exploiting gain-tuning capability
of DG-MOSFETs are also illustrated. Additionally, a fourmonopole antenna array structure is also studied for on-chip
interconnects via full-wave simulations. The attenuation

[1] P. Ramm, A. Klumpp, J. Weber, and M. M. V. Taklo, 3D system-on-chip

technologies for more than Moore systems, Microsyst. Technol., vol. 16,
no. 7, pp. 10511055, 2010.
[2] A. Ganguly et al., Scalable hybrid wireless network-on-chip architectures for multicore systems, IEEE Trans. Comput., vol. 60, no. 10,
pp. 14851502, Oct. 2010.
[3] P. Y. Chiang et al., Short-range, wireless interconnect within a computing chassis: Design challenges, IEEE Des. Test. Comput., vol. 27,
no. 4, pp. 3243, Jul./Aug. 2010.
[4] M. Chang et al., CMP network-on-chip overlaid with multi-band RF
interconnect, in Proc. IEEE Int. Symp. High Perform. Comput. Archit.,
Salt Lake City, UT, USA, 2008, pp. 191202.
[5] L. Carloni, P. Pande, and Y. Xie, Networks-on-chip in emerging interconnect paradigms: Advantages and challenges, in Proc. ACM/IEEE
Int. Symp. Netw. Chip (NoCs), San Diego, CA, USA, 2009, pp. 93102.
[6] D. Halperin, S. Kandula, J. Padhye, P. Bahl, and D. Wetherall,
Augmenting data center networks with multi-gigabit wireless links, in
Proc. ACM SIGCOMM 2011 Conf., Toronto, ON, Canada, pp. 3849.
[7] S. Lee et al., A scalable micro wireless interconnect structure for
CMPs, in Proc. Int. Conf. Mobile Comput. Netw. (Mobicom), Beijing,
China, 2009, pp. 217228.
[8] R. Stevens et al., Architectures and technology for extreme
scale computing, Dept. Energy, Off. Sci., Washington, DC, USA,
Tech. Rep. PNNL-19379, Dec. 2009.
[9] C. Chun et al., DSENTA tool connecting emerging photonics with
electronics for opto-electronic networks-on-chip modeling, in Proc.
IEEE Int. Symp. Netw. Chip (NOCS), Copenhagen, Denmark, 2012,
pp. 201210.
[10] S. Kaya et al., On ultra-short wireless interconnects for NoCs and
SoCs: Bridging the THz Gap, in Proc. IEEE 56th Int. Midwest
Symp. Circuits Syst. (MWSCAS), Columbus, OH, USA, Aug. 2013,
pp. 804808.
[11] D. Matolak et al., Wireless networks-on-chips: Architecture, wireless
channel, and devices, IEEE Wireless Commun. Mag., vol. 19, no. 5,
pp. 5865, Oct. 2012.
[12] D. DiTomaso, A. Kodi, S. Kaya, and D. Matolak, iWISE: Inter-router
wireless scalable express channels for network-on-chips (NoCs) architecture, in Proc. IEEE Symp. High-Perform. Interconnects, Santa Clara,
CA, USA, 2011, pp. 1118.
[13] S. Deb, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo, Wireless
NoC as interconnection backbone for multicore chips: Promises and
challenges, IEEE J. Emerg. Sel. Topic Circuits Syst., vol. 2, no. 2,
pp. 228239, Jun. 2012.
[14] S. Voinigescu et al., Characterization and modelling of a SiGe HBT
technology for transceiver applications in the 100-300 GHz range,
IEEE Trans. Microw. Theory Techn., vol. 60, no. 12, pp. 40244034,
Dec. 2012.
[15] A. Balteanu, S. Shopov, and S. P. Voinigescu, A 2 44gb/s 110GHz wireless transmitter with direct amplitude and phase modulation in
45-nm SOI CMOS, in Proc. IEEE Comp. Semicond. Integr. Circuit
Symp. (CSICS), Monterey, CA, USA, Oct. 2013, pp. 14.
[16] L. Samoska, An overview of solid-state integrated circuit amplifiers
in the submillimeter-wave and THz regime, IEEE Trans. THz Sci.
Technol., vol. 1, no. 1, pp. 924, Sep. 2011.
[17] T. Kleine-Ostmann and T. Nagatsuma, A review on terahertz communications research, J. Infrared Millim. THz. Waves, vol. 32, no. 2,
pp. 143171, 2011.
[18] Y. P. Zhang, Z. M. Chen, and M. Sun, Propagation mechanisms of radio
waves over intra-chip channels with integrated antennas: Frequencydomain measurements and time-domain analysis, IEEE Trans. Antennas
Propag., vol. 55, no. 10, pp. 29002906, Oct. 2007.

198

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 34, NO. 2, FEBRUARY 2015

[19] E. Genender et al., Simulating the multipath channel with a reverberation chamber: Application to bit error rate measurements, IEEE Trans.
Electromagn. Compat., vol. 52, no. 4, pp. 766777, Nov. 2010.
[20] D. A. Hill et al., Aperture excitation of electrically large, lossy cavities, IEEE Trans. Electromagn. Compat., vol. 36, no. 3, pp. 169178,
Aug. 1994.
[21] G. L. Stuber, Principles of Mobile Communication. Dordrecht,
The Netherlands: Kluwer, 2001.
[22] J. D. Parsons, The Mobile Radio Propagation Channel. Hoboken, NJ,
USA: Wiley, 2000.
[23] T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. Wong, and F. Boeuf,
The end of CMOS scaling: Toward the introduction of new materials and structural changes to improve MOSFET performance,
IEEE Circuits Devices Mag., vol. 21, no. 1, pp. 1626, Jan./Feb. 2005.
[24] I. Ferain, C. A. Colinge, and J.-P. Colinge, Multigate transistors as the
future of classical metal-oxide-semiconductor field-effect transistors,
Nature, vol. 479, pp. 310316, Nov. 2011.
[25] J.-J. Kim and K. Roy, Double gate-MOSFET subthreshold circuit for
ultralow power applications, IEEE Trans. Electron Devices, vol. 51,
no. 9, pp. 14681474, Sep. 2004.
[26] A. Amara and O. Rozeau, Planar Double-Gate Transistor. Dordrecht,
The Netherlands: Springer, 2009.
[27] A. Lazaro and B. Iniguez, RF and noise performance of double gate
and single gate SOI, Solid State Electron., vol. 50, no. 5, pp. 826842,
2006.
[28] W. Zhao and Y. Cao, Predictive technology model for nano-CMOS
design exploration, ACM J. Emerg. Technol. Comput. Syst., vol. 3, no. 1,
pp. 117, 2007.
[29] B. Razavi, RF Microelectronics. Boston, MA, USA: Prentice Hall, 2012.
[30] J.-P. Raskin, T. M. Chung, V. Kilchytska, D. Lederer, and D. Flandre,
Analog/RF performance of multiple gate SOI devices: Wideband simulations and characterization, IEEE Trans. Electron Devices, vol. 53,
no. 5, pp. 10881095, May 2006.
[31] D. S. Gardner et al., Review of on-chip inductor structures with
magnetic films, IEEE Trans. Magn., vol. 45, no. 10, pp. 47604766,
Oct. 2009.
[32] F. Gardiol, Microstrip Circuits. Hoboken, NJ, USA: Wiley, 1994.
[33] Y. Sun, J. Borngraber, F. Herzel, and W. Winkler, A fully integrated 60 GHz LNA in SiGe: C BiCMOS technology, in Proc. IEEE
Bipolar/BiCMOS Circuits Technol. Meeting, Santa Barbara, CA, USA,
2005, pp. 1417.
[34] W. Abadeer, R. A. Groves, and P. Hansen, Inductor for integrated
circuits, U.S. Patent 6 714 113 B1, Mar. 2004.
[35] E. Hammerstad and O. Jensen, Accurate models for microstrip
computer aided design, in Proc. IEEE MTT-S Int. Microw. Symp.,
Washington, DC, USA, 1980, pp. 407409.
[36] T. Yao, M. Gordon, K. Yau, M. Yang, and S. P. Voinigescu, 60-GHz
PA and LNA in 90-nm RF-CMOS, in Proc. IEEE Radio Freq. Integr.
Circuits (RFIC) Symp., San Francisco, CA, USA, 2006, pp. 47.
[37] W.-S. Kim, X. Li, and M. Ismail, A 2.4 GHz CMOS low noise amplifier
using an inter-stage matching inductor, in Proc. IEEE Midwest Symp.
Circuits Syst., Las Cruces, NM, USA, 1999, pp. 10401043.
[38] L. Samoska et al., Cryogenic MMIC low noise amplifiers for W-band
and beyond, in Proc. Int. Symp. Space THz Technol., Tucson, AZ, USA,
Apr. 2011, pp. 14.
[39] A. Leuther et al., Metamorphic HEMT technology for low noise applications, in Proc. InP Rel. Mater. Conf., Newport Beach, CA, USA,
May 2009, pp. 188191.
[40] B. Floyd et al., SiGe bipolar transceiver circuits operating at 60 GHz,
IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 156167, Jan. 2005.
[41] S. Pellarano, Y. Palaskas, and K. Soumyanath, A 64 GHz LNA with
15.5 dB gain and 6.5 dB NF in 90 nm CMOS, IEEE J. Solid-State
Circuits, vol. 43, no. 7, pp. 15421552, Jul. 2008.
[42] N. Li et al., A 24 dB gain 51-68 GHz CMOS low noise amplifier
using asymmetric-layout transistors, in Proc. Eur. Solid-State Circuits
Conf. (ESSCIRC), Seville, Spain, 2010, pp. 342345.
[43] S. Laha, S. Kaya, A. Kodi, and D. Matolak, 60 GHz OOK transmitter
in 32 nm DG FinFET technology, in Proc. IEEE Int. Conf. Wireless
Circuits Syst. (ICWITS), Maui, HI, USA, 2012, pp. 14.
[44] Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices. Cambridge,
U.K.: Cambridge Univ. Press, 1998.
[45] S. Laha and S. Kaya, Analog Circuits. Rijeka, Croatia: InTech,
Dec. 2012, ch. Radio Frequency IC Design with nanoscale
DG-MOSFETSs.

[46] R. Merritt. (Oct. 16, 2012). TSMC taps ARMs V8 on road to 16-nm
FinFET, EE Times. [Online]. Available: http://www.Eetimes.com/elect
ronicsnews/4398727/TSMC-taps-ARM-V8-in-road-to-16-nm-FinFET
[47] D. W. Matolak, A. Kodi, and S. Kaya, Channel modeling for wireless
networks-on-chips, IEEE Commun. Mag., vol. 51, no. 6, pp. 180186,
Jun. 2013.
[48] (Dec. 2013). Ansys Corp. [Online]. Available: http://ansoft.com/
Soumyasanta Laha (S09) received the B.Sc. degree in physics from the
University of Calcutta, Kolkata, India, the M.Sc. degrees in applied physics
with concentration in microelectronics and embedded digital systems with
distinction from the Sikkim Manipal Institute of Technology, Gangtok, India,
and the University of Sussex, Sussex, U.K., in 2001, 2003, and 2007, respectively, and the Ph.D. degree in electrical engineering from the Russ College
of Engineering and Technology, Ohio University, Athens, OH, USA, in 2014.
His current research interests include nanoscale energy-efficient RF
transceivers. He has published over 20 papers in the above areas and has over
three years of industry experience in analog electronics, embedded systems,
and RFIC design in India and U.K.
Mr. Laha was the recipient of the Stocker Research Fellowship Award by
Ohio University.
Savas Kaya (SM01) received the M.Phil. degree from the University of
Cambridge, Cambridge, U.K., and the Ph.D. degree from the Imperial College
of Science, Technology, and Medicine, London, U.K., in 1994 and 1998,
respectively.
He was a Post-Doctoral Researcher at the University of Glasgow, Glasgow,
U.K., from 1998 to 2001, where he researched on transport and scaling
in Si/SiGe MOSFETs and fluctuation phenomena in decanano MOSFETs.
He is currently with the Russ College of Engineering, Ohio University,
Athens, OH, USA. His current research interests include transport theory,
device modeling and process integration, nanofabrication, nanostructures, and
nanobiosensors.
David W. Matolak (SM88) received the B.S. degree from Pennsylvania State
University, University Park, State College, PA, USA, the M.S. degree from
the University of Massachusetts, Amherst, MA, USA, and the Ph.D. degree
from the University of Virginia, Charlottesville, VA, USA, all in electrical
engineering.
He was with the Rural Electrification Administration, Washington,
DC, USA, the UMass LAMMDA Laboratory, Amherhst, AT&T Bell
Laboratories, North Andover, MA, USA, the University of Virginias
Communication Systems Laboratory, Charlottesville, Lockheed Martin
Tactical Communication Systems, Salt Lake City, UT, USA, the
MITRE Corporation, McLean, VA, USA, and Lockheed Martin Global
Telecommunications, Reston, VA, USA, for over 20 years on communication
systems. From 1999 to 2012, he was with the School of Electrical Engineering
and Computer Science, Ohio University, Athens, OH, USA, and since 2012, he
has been with the Department of Electrical Engineering, University of South
Carolina, Columbia, SC, USA. His current research interests include communication over fading channels, radio channel modeling, and ad hoc networking.
William Rayess (S12) received the B.E. degree in computer and communications engineering from Notre Dame University, Zouk Mosbeh, Lebanon,
and the MCTP degree from Ohio University, Athens, OH, USA, in 2008 and
2009, respectively. He is currently pursuing the Ph.D. degree in electrical
engineering from the University of South Carolina, Columbia, SC, USA.
Dominic DiTomaso (S06) received the B.S. and M.S. degrees in electrical
engineering and computer science from Ohio University, Athens, OH, USA, in
2010 and 2012, respectively, where he is currently pursuing the Ph.D. degree
from the Department of Electrical Engineering and Computer Science.
His current research interests include wireless interconnects,
network-on-chips, and computer architecture.
Avinash Kodi (SM06) received the M.S. and Ph.D. degrees in electrical
and computer engineering from the University of Arizona, Tucson, AZ, USA,
in 2003 and 2006, respectively.
He is currently an Associate Professor with the Department of Electrical
Engineering and Computer Science, Ohio University, Athens, OH, USA.
His current research interests include computer architecture, optical
interconnects, chip multiprocessors, and network-on-chips.
Prof. Kodi was the recipient of the National Science Foundation CAREER
Award in 2011.