CSO - 03 - Addition and Subtraction of Signed Binary Numbers

COMPUTER STRUCTURE
AND ORGANIZATION
Course titular:
DUMITRACU Eugen
Chapter
ADDITION AND
SUBTRACTION OF
SIGNED BINARY
NUMBERS
CONTENT
FXP addition in direct code
FXP addition device in direct code
FXP subtraction in direct code
Addition/subtraction device in FXP direct code
FXP addition in 2s complement code
FXP subtraction in 2s complement code
Addition/subtraction device in FXP 2s
complement code
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FXP ADDITION IN DIRECT CODE

We considered operands 0|A|<1 and 0|B|<1 in direct
code.
The result is 0|S|<1, in the same format as A and B.
If the result has |S|>1 should be detected an error.
A very important feature of operations with numbers
represented in direct code is that the sign bit of the
result is generated separately from its bits because the
sign bit has no weight.
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Block diagram of a binary adder for signed numbers
represented in FXP direct code
Where
/ binary adder/subtracter for unsigned numbers;
OBG overflow bit generator;
SBG sign bit generator;
IOG internal operation signal generator.
go to slide 13
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Case I: A0 and B0
The operands are represented as A=0,|A| and B=0,|B|
Thus S=A+B=0,|S|
Because the numbers has the same sign for some cases will appear
overflow. So, there are two sub-cases:
0|A|+|B|<1
In this case Overflow=0, and the result is correctly represented in direct
code
|A|+|B| 1
The result cant be represented in considered format. So, will be
generated an overflow error (Overflow=1)
The sign bit is irrelevant.
Observation! In both sub-cases the internal operation coincides with
the external operation!
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Case II: A 0 and B 0

Because the sum of two numbers with opposite sign is less than each of
the two numbers, it is obvious that the overflow may not occur
(Overflow = 0).
Will be analyzed according to the sign of the results next two subcases:
|A| |B|
The sign bit of sum is Ss=0. So, the result is positive.
In this case |S|=|A|-|B|, the result is correctly represented in direct
code.
This 1 is not physical represented, it is
outside the format. It will appear as
|A|<|B|
Cout=1 (borrow).
The result is negative, thus Ss=1.
The result is |S|=|B|-|A|=-(|A|-|B|)=1-(|A|-|B|)= | A | | B |
The result is correct but represented in 2s complement code and
should be transform in direct code.
Observation! In both sub-cases the internal operation is different than
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Case III: A 0 and B 0

Because the sum of two numbers with opposite sign is less than each of
the two numbers, it is obvious that the overflow may not occur
(Overflow = 0).
|A| |B|
The sign bit of sum is Ss=1. So, the result is negative.
In this case |S|=|A|-|B|, the result is correctly represented in direct
code.
This 1 is not physical represented, it is
outside the format. It will appear as
|A|<|B|
Cout=1 (borrow).
The result is positive, thus Ss=0.
The result is |S|=|B|-|A|=-(|A|-|B|)=1-(|A|-|B|)= | A | | B |
The result is correct but represented in 2s complement code and
should be transform in direct code.
Observation! In both sub-cases the internal operation is different than
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Case IV: A < 0 and B < 0
Because the sum of two negative is a negative number,the sum is
S=A+B=1,|S|. In this case may be appear overflow.
Will be analyzed the next two sub-cases:
0 |A|+|B|< 1
In this case |S|=|A|+|B|, the overflow doesnt appear, the result is
correctly represented in direct code. The sign bit of sum is Ss=1
|A|+|B| 1
The result cant be represented in considered format. So, will be
generated an overflow error (Overflow=1).
The sign bit is irrelevant.
Observation! In both sub-cases the internal operation coincides with
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Examples:
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10

Conclusions:
If operands A and B has the same sign:
The internal operation coincides with the external operation;

The output Cout is carry out because the operation is addition;
The sign bit of result coincides with the sign bit of operands;
If |A|+|B|<1, the result is correct and represented in direct code;
If |A|+|B|1, then Cout=1 and an error signal is generated for
overflow.
If operands A and B has opposite signs:
The internal operation is different than the external operation;

There is no overflow;
The output Cout is an borrow because the operation is subtraction;
If |A| |B|, the result is correct and represented in direct code;
If |A|<|B|, the result is correct and represented in 2s complement
code and Cout=1;
Whenever Cout=1, the result appears in 2s complement code and
should be converted in direct code
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CONTENT
complement code
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FXP ADDITION DEVICE IN DIRECT CODE

The synthesis of an addition device in direct code is based
on using of a elementary binary adder and generating
the following signals (see figure from slide 5):
IntOP internal operation (0 - addition, 1 - subtraction);
Ss sign bit (0 - positive, 1 - negative);
Overflow overflow format signal, active on high level;
CF2 signal indicates the representation code of the result
(0 direct code representation, 1 2s complement
code representation).
The synthesis of these signals is based on conclusions from
slide 11, which allow generation of truth table for
signals IntOP, Ss, Overflow, CF2.
The truth table of signals for addition device in direct code:
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As Bs Cout || IntOP
0
0
0 ||
0
0
0
1 ||
0
0
1
0 ||
1
0
1
1 ||
1
1
0
0 ||
1
1
0
1 ||
1
1
1
0 ||
0
1
1
1 ||
0
After minimization:
IntOP = As Bs
Ss = As Cout + BsCout
Overflow = Cout(As Bs)
CF2 = Cout
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Ss
0
0
0
1
1
0
1
1
Overflow CF2
0
0
1
0
0
0
1
0
0
0
1
0
0
1
-
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The Design method described above has three
disadvantages:
it is laborious and requires some experience in the
design of logical devices;
it is incomplete in the sense that in some cases the
result is in complementary code which requires a
further step of converting in direct code (why?)
the solution is suitable for integrated circuit
implementation of medium and small scale but not for
FPGA implementation.
For FPGA implementation we use a different approach,
more natural, strarting from the mode how human
realizes adding signed numbers.
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test case
|| case1 case2 case3 case4 case5 case6 case7 case8
iaA
|| 55
iaB
|| 2A
oaSum || 7F
oOverflow || 0
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55
7F
*
1
55
AA
2B
0
55
F5
A0
0
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AA
1A
90
0
AA
7A
50
0
AA
85
AF
0
AA
FF
*
1
18
CONTENT
complement code
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FXP SUBTRACTION IN DIRECT CODE

Subtraction by adding 2s complement of a
subtrahend absolute value
(minuend - subtrahend = difference) (descazut scazator = diferenta)
The method is based on the following property (FXP

representation of fractional numbers):
|A| -|B| = 1 + |A| -|B| = |A| + (1 -|B|) = |A| + | B |
In the above formula the minus sign refers to the internal

operation!
The method has the advantage that for subtract is
necessary an adder, which greatly reduces the
complexity of schemes to carry out operations of
addition / subtraction.
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FXP SUBTRACTION IN DIRECT CODE

Examples:
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CONTENT
complement code
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ADDITION/SUBTRACTION DEVICE IN FXP

DIRECT CODE
FXP Addition/Subtraction device in direct code
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ADDITION/SUBTRACTION DEVICE IN FXP

DIRECT CODE
FXP Addition/Subtraction device in direct code
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CONTENT
complement code
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FXP ADDITION IN 2s COMPLEMENT CODE

There are two fundamental differences between addition in
direct code and addition in 2s complement code:
1. In case of adding in 2s complement code the sign bit is
treated as any other bit of number so the addition is
done one 1+m ranks. This means that the correct sign
bit resulting from the addition process and is not

generated in a separate block of addition device.
2. The intern operation is the same with external

operation
Further, as addition in direct code, we perform a detailed
analysis of the 4 cases (8 sub-cases) possible.
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Case I: A0 and B0
The operands are represented as in direct code A=0,|A| and
B=0,|B|
Because the sum of positive numbers is a positive number, then
S=A+B=0,|S|
The numbers has the same sign for some cases can appear overflow.
So, there are two sub-cases:
Sign bit
Sign bit
0|A|+|B|<1
A+B=0+|A|+0+|B|=0+|A+B|=0+|S|
The result is correctly represented 2s complement code and it hasnt
overflow (Overflow=0).
Its observed that C0=C-1=0.
|A|+|B| 1
A+B=0+|A|+0+|B|=0+1+|S|=120+|S|
Obviously, the result is absurd because the sum of two positive
numbers can not be negative!
This is because the format is overflow (Overflow=1).
Its observed that C0=0 and C-1=1.
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Case II: A 0 and B <0
Because numbers havent the same sign, it is obvious than the result of
addition is a subunit number and overflow doesnt appear.
C-1
C0
Result
Sign bit
Sign bit
|A| |B|
sign bit
A+B=0+|A|+1+1-|B|=120+|A|+1-|B|= 121+ 020+|A|-|B|
C-1
Sign bit
Sign bit
Result
In this case C0=C-1=1.
sign bit
|A|<|B|
A+B=0+|A|+1+1-|B|=120+|A|+(1-|B|)= 120+ 1+|A|-|B|=
= 120+ (1-(|B|-|A|))= 120+ |B|-|A|
It is observed that the sign bit is correct and the correct value of sum is
in 2's complement code, so the result is correct in 2s complement
code.
As in previous cases, C0 = C-1 = 0.
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Case III: A < 0 and B 0
As previous case, the result of the addition is a subunit number and
overflow not exceeding occur.
|A| |B|
A+B=1+|A|+0+|B|=1+(1-|A|)+0+|B|= 120+(1-(|A|-|B|))=
= 120+ |A|-|B|
It is noted that the sign bit is correct and the correct value of sum
appears in the 2s complement code, so the result is correct in 2s
complement code.
Additionally, we see that C0 = C-1 = 0.
Result
C-1
C0
Sign bit
Sign bit
sign bit
|A|<|B|
A+B=1+|A|+0+|B|= 1+(1-|A|)+|B|= 121+ 0 20 +|B|-|A|
Also in this cases, C0 = C-1 = 1.
The result is correct in 2s complement code.
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Case IV: A < 0 and B < 0
The operands are represented in 2s complement code as A=1,|A| and B=1,|B|
Because the sum of negative numbers is a negative number, then S=A+B=1,|S|
The numbers has the same sign, as in case I, for some cases can appear overflow.
0|A|+|B|<1
A+B=1+|A|+1+|B|=1+(1-|A|)+1+(1-|B|)=
= 121+120+(1-(|A|+|B|))=121+120+(|A|+|B|)
The result is correctly represented 2s complement code and it hasnt overflow
(Overflow=0).
Its observed that C0=C-1=1.
|A|+|B| 1
A+B= 1+|A|+1+|B|= 121+020+(1-|A|)+(1-|B|)=
= 121+020+1+1-(|A|+|B|)= 121+020+1+1-(1+|S|)=
= 121+020+(1-|S|)=121+020+|S|
Obviously, the result is absurd because the sum of two negative numbers can not be
positive!
This is because the format is overflow (Overflow=1).
Its observed that C0=1 and C-1=0.
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Conclusions:
In all analyzed cases the internal operation coincides
with the external operation.
If operands A and B has the same sign:
The result is correct in 2s complement only if the sum of

absolute values of the numbers is subunit (<1) (Overflow=0);
The result is wrong (Overflow=1) if the sum of absolute values
of the numbers is higher then 1, because of overflow.
If operands A and B has opposite signs:
There is no overflow (Overflow=0);

The results is always correct in 2s complement code
Whenever overflow occurs, then C0 <> C-1.

In all other cases C0 = C-1
Then Overflow = C0 C-1
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Examples:
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CONTENT
complement code
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FXP SUBTRACTION IN 2s COMPLEMENT CODE

A-B = 121 + A - B = A + (1 -B) = A + B
In the above formula the minus sign refers to the external

operation!
From the above formula results that the subtraction of two
numbers represented in 2s complement code can be
realized by adding minuend with extended 2's
complement of subtrahend.
This allows a very simple implementation of an
adder/subtractor for numbers represented in 2s
complement code.
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FXP SUBTRACTION IN 2s COMPLEMENT CODE

Examples:
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CONTENT
complement code
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ADDITION/SUBTRACTION DEVICE IN FXP 2s

COMPLEMENT CODE
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COMPLEMENT CODE
If iOperation = 0 oS = A + B + 02-m = A + B;
If iOperation = 1 oS = A + B + 12-m = A + B =
= 121+ A B = A - B
because the bit of rank 21 has no physical representation.
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COMPLEMENT CODE
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COMPLEMENT CODE
VHDL model
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COMPLEMENT CODE
VHDL model
test case ||case1 case2 case3 case4 case5 case6 case7 case8
iaA
iaB
oaSum
oOverflow
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|| 55
|| 2A
|| 7F
|| 0
55
7F
*
1
55
D6
2B
0
55
8B
E0
0
D6
1A
F0
0
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D6
7A
50
0
D6
FB
D1
0
D6
11
*
1
41
QUESTIONS?
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42

CSO - 03 - Addition and Subtraction of Signed Binary Numbers

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COMPUTER STRUCTURE

FXP ADDITION IN DIRECT CODE

FXP ADDITION IN DIRECT CODE

FXP ADDITION IN DIRECT CODE

FXP ADDITION IN DIRECT CODE

Case II: A 0 and B 0

FXP ADDITION IN DIRECT CODE

Case III: A 0 and B 0

FXP ADDITION IN DIRECT CODE

FXP ADDITION IN DIRECT CODE

FXP ADDITION IN DIRECT CODE

The internal operation coincides with the external operation;

If operands A and B has opposite signs:

The internal operation is different than the external operation;

FXP ADDITION DEVICE IN DIRECT CODE

FXP ADDITION DEVICE IN DIRECT CODE

FXP ADDITION DEVICE IN DIRECT CODE

FXP ADDITION DEVICE IN DIRECT CODE

FXP ADDITION DEVICE IN DIRECT CODE

FXP ADDITION DEVICE IN DIRECT CODE

|| case1 case2 case3 case4 case5 case6 case7 case8

FXP SUBTRACTION IN DIRECT CODE

The method is based on the following property (FXP

In the above formula the minus sign refers to the internal

FXP SUBTRACTION IN DIRECT CODE

ADDITION/SUBTRACTION DEVICE IN FXP

ADDITION/SUBTRACTION DEVICE IN FXP

FXP ADDITION IN 2s COMPLEMENT CODE

bit resulting from the addition process and is not

2. The intern operation is the same with external

FXP ADDITION IN 2s COMPLEMENT CODE

FXP ADDITION IN 2s COMPLEMENT CODE

FXP ADDITION IN 2s COMPLEMENT CODE

FXP ADDITION IN 2s COMPLEMENT CODE

FXP ADDITION IN 2s COMPLEMENT CODE

The result is correct in 2s complement only if the sum of

If operands A and B has opposite signs:

There is no overflow (Overflow=0);

Whenever overflow occurs, then C0 <> C-1.

FXP ADDITION IN 2s COMPLEMENT CODE

FXP SUBTRACTION IN 2s COMPLEMENT CODE

In the above formula the minus sign refers to the external

FXP SUBTRACTION IN 2s COMPLEMENT CODE

ADDITION/SUBTRACTION DEVICE IN FXP 2s

ADDITION/SUBTRACTION DEVICE IN FXP 2s

ADDITION/SUBTRACTION DEVICE IN FXP 2s

ADDITION/SUBTRACTION DEVICE IN FXP 2s

ADDITION/SUBTRACTION DEVICE IN FXP 2s

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