EEE596 ASIC DESIGN

Slot :B1+TB1 & B2+TB2

Instructor:

Dr. K.Sivasankaran,
Associate Professor,
VLSI Division,
School of Electronics Engineering,
VIT University
ksivasankaran@vit.ac.in
ksivasankaran.vlsi@gmail.com
Mobile: 9994256440
Cabin: TT238

Outline

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

Objective and Outcomes

Objective of the Course:
To study the issues relating to the design of application-specific integrated
circuits (ASICS) for digital systems.
Course Outcomes
After completion of this course :
Students will be able to design and synthesize a complex digital functional
block using Verilog HDL.
Students will demonstrate an understanding of how to optimize the
performance, area, and power of a complex digital functional block, and the
tradeoffs between these.
Students will demonstrate an understanding of issues involved in ASIC
design, including technology choice, Timing analysis, tool-flow, testability.
Module-I

ASIC DESIGN

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

Syllabus
Introduction
Implementation Strategies for Digital ICs: Custom IC Design, Cell-based Design Methodology. Array based
implementation approaches. Traditional and Physical Compiler based ASIC Flow.
Digital ASIC Design using Verilog HDL
Verilog HDL: Levels of Abstraction, Hierarchical modeling and Delay modeling, Verilog constructs, FSM,
Memory modeling. Complex Digital System Design Examples.
RTL Simulation and Synthesis
Functional Simulation: Test bench Wrappers. Event-based Simulation: Event-based Simulation. Cyclebased Simulation.
RTL Synthesis: An overview of the synthesis based ASIC design flow. Synthesis Environment. technology
library: technology libraries, logic library basics, delay calculations.
Partitioning and Coding Styles: Partitioning for synthesis, Coding guideline for synthesis. Logic Inference:
Order dependence. Optimization and mapping constraints (clock, delay, area, design). Instantiating special
operators and black boxes. FSM synthesis, Performance-driven synthesis.
Static Timing Analysis
Overview of timing verification and static timing analysis. Critical path. Timing exceptions. Multicycle
paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width). Practical usage
of timing analysis.
Design for Testability
Types of DFT. Scan Insertion. Design Rules, DFT guidelines. Built-in-Self-Test(BIST):Test pattern Generation
Exhaustive , Pseudo Random , Pseudo Exhaustive , Output Response Analysis , Logic BIST architectures
With and without scan chains , Register Reconfiguration , Boundary Scan and core testing.

Module-I

ASIC DESIGN

Text book / References

1. T.R.Padmanabhan, B.Bala Tripura Sundari, Design through Verilog HDL Wiley
Interscience, 2004.
2. Himanshu. Bhatnagar, Advanced ASIC Chip Synthesis (2/e).KAP.2002
3. Farzad Nekoogar, Timing Verification of Application-Specific Integrated Circuits
Farzad Nekoogar, Prentice-Hall. 1999
4. M. Bushnell and V. D. Agarwal, "Essentials of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits", KAP, 2000
5. Donald E. Thomas, Philip R. Moorby, The Verilog Hardware Description
Language (5/e) KAP. 2002
6. Maheshwari, Naresh, Sapatnekar, S Timing Analysis and Optimization of
Sequential Circuits. 1998, Springer. ISBN: 978-0-7923-8321-5
7. Prime Time user guide
8. Michael John Sebastian Smith, Application Specific Integrated Circuits 2012,
Pearson Education.

Module-I

ASIC DESIGN

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

Mode of Evaluation

Module-I

Component

Marks

Weightage

Assessment Test

50

20

Surprise Test

10

10

Assignment

20

20

Term end Exam

100

50

Total

100

ASIC DESIGN

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

10

Picture of Part of ENIAC (Electronic Numerical Integrator And

Calculator)

Module-I

ASIC DESIGN

11

ENIAC FROM ANOTHER ANGLE

Module-I

ASIC DESIGN

12

ENIAC vs. Microcomputer

ENIAC
Size : 30 x 50 ft
Weight : 30 tons
Tubes : 18 K
Resistors: 70 K
Capacitors : 10 K
Switches : 6 K
Power : 150 kW
Cost (1940) : US $ 400 K

Module-I

ASIC DESIGN

Microcomputer
Size : inch x inch
Weight : nil
Power < light bulb
Speed : 20 times faster
Memory : larger, more
computing capacity
Cost < $300 (compare
with $ 400 K + inflation
over 34 years).

13

Miniaturization: December 23, 1947

From left: Bardeen, Shockley, Brattain

Nobel Winners of Physics in 1956
Module-I

First Point Contact Transistor of

Bardeen and Brattain
ASIC DESIGN

14

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ASIC DESIGN

15

Module-I

ASIC DESIGN

16

Levels of Integration

Small Scale Integration (<10 Transistors)

Medium Scale Integration (<1000 Transistors)
Large Scale Integration (<10000 Transistors)
Very Large Scale Integration( > million Transistors)
Giga Scale Integration (> billion Transistors)

Module-I

ASIC DESIGN

17

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ASIC DESIGN

18

Trends in Integrated Circuits

Reduce the device geometry ( Scaling)
more circuit blocks in a chip (Processors)
higher speed (Novel devices)
low power consumption (Silicon Technology)

Module-I

ASIC DESIGN

19

Moores law

Module-I

Size of the device

Fabrication complexity
Device Reliability

ASIC DESIGN

Source: Intel

20

More Moore & More than Moore

[ITRS, 2011]
Module-I

ASIC DESIGN

21

Courtesy: Intel

Module-I

ASIC DESIGN

22

Why Scaling?
Technology shrinks by 0.7/generation
With every generation can integrate 2x more functions per
chip for about the same $/chip
Cost of a function decreases by 2x
But
How to design chips with more and more functions?
Design engineering population does not double every two
years
Hence, a need for more efficient design methods
Exploit different levels of abstraction

Module-I

ASIC DESIGN

23

Scaling Issues
Log(Idrain)
MOSFET
Ideal switch
switch

ON state
Current
OFF state
Current

OFF State
Current

[Navakanta Bhat, 2007]

Vgate
Threshold (Vth)

SCE, High Leakage Current (Reducing Lg)

Gate Leakage (Reducing tox)
High Ioff (Reducing Voltage)

Module-I

ASIC DESIGN

24

Design Abstraction Levels

SYSTEM

MODULE
+
GATE

CIRCUIT

DEVICE
G
S
n+
Module-I

ASIC DESIGN

D
n+
25

ITRS Projections

Module-I

ASIC DESIGN

26

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

27

Module-I

ASIC DESIGN

28

Fact findings to scaling

Cross section of a single
human hair can contain
thousands of transistors !!!

~ 40,000 (65 nm node; LG ~ 50

nm) transistors could fit on the
cross section of a hair.

Different scales inside a chip

Gate

2x2 cm
M1

M1

Source
NiSi

Drain
contact

10x10 mm

M1

NiSi

Silicon channel

4x4 m
500x500 nm
Module-I

ASIC DESIGN

30

Technology is getting complex

1970
Si
B, P, Al
SiO2

Feature size (m)

10
1
0.1
0.01
0.001
1970 1980 1990 2000 2010 2020
Year

2000
SiGe
Metal gates
High-k dielectrics
Low-k dielectrics
Cu interconnects
W plug
Co-silicide
Ti-silicide
Ni-silicide
BPSG
Poly-Si
Si3N4
Oxi-nitride
As, B, P, Al, SiO2, Si.

Tri-gate width/height optimization

C. Auth et al., pp.131, VLSI2012 (Intel)

PMOS channel
under the gate

S/D region showing the

SiGe epitaxy

A fin width of 8nm to balance SCE and Rext

A fin height of 34nm to balance drive current vs. capacitance
Module-I

ASIC DESIGN

32

Intels 45nm Transistor

High K dielectric
Metal gate
Strained silicon

Module-I

ASIC DESIGN

33

Future - nanoFET devices

VG

VS

FET with:
Carbon nanotubes.
Self-aggregated organic nanotubes.

VD

Molecular transistors.

Extensive modeling and comprehensive understanding are

mandatory.

Alternatives to existing electronic systems

Emerging nanotechnology
drivers

Emerging nanotechnology
solutions

Quantum
Dots
Molecular
devices
NT arrays
DNA self
assembly

Module-I

SETs

NanotubeFE
Ts

RTD

Nanoscale
CMOS

Molecular orientations
as Bits
Molecules
in Solution

DNA strands as
Bits
Self assembled
NT

ASIC DESIGN

Logic

Memory
Technology

35

Performance parameters of a MOSFET

How can we categorize a MOSFET good or bad?
Threshold voltage (Vth)
Off-state leakage current (Ioff)
On-state current (Ion)
Transconductance (gm)
Channel conductance (gd)
Sub-threshold slope (S)
Drain voltage (Vdd)
Channel mobility ()
S/D resistance (Rs and Rd)
DIBL

Lower
Lower
Higher
Higher
Higher
Smaller
Lower
Higher
Lower
Lower

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

37

ASIC
Application Specific Integrated Circuit
E.g. Chip designed solely for use in cell phone
A chip that can be designed by an engineer with no particular
knowledge of semiconductor physics or semiconductor
processes.

Module-I

ASIC DESIGN

38

What is an FPGA?

ASIC DESIGN

Interconnection switches

I/O

I/O

Module-I

Logic
block

I/O

Field Programmable Gate Array

Gate Array
Two-dimensional array of logic
gates
Traditionally connected with
customized metal
Field Programmable
Field programmability is
achieved through switches
(Transistors controlled by memory
elements or fuses)
One FPGA can serve every
customer
FPGA: re-programmable hardware

I/O

39

FPGA vs. ASIC

FPGA = Field Programmable Gate Array
flexibility of software + speed of hardware

ASIC = Application Specific Integrated Circuits

Module-I

ASIC DESIGN

40

Traditional System Design

Ethernet
MAC

Audio
Codec

Interrupt
Controller

GP I/O
Address
Decode
Unit

CPU
(uP / DSP)

CLK

SRAM

Module-I

Power Supply

CLK
CLK

Memory
Controller

SRAM

SRAM

SDRAM

ASIC DESIGN

Timer

UART
CoProc.

SDRAM

custom
IF-logic

Display
Controller

41

Next Step...

Ethernet
MAC

FPGA

Audio
Codec

Interrupt
Controller

GP I/O
Address
Decode
Unit

CPU
(uP / DSP)

CLK

SRAM

Module-I

Power Supply

CLK
CLK

Memory
Controller

SRAM

SRAM

SDRAM

ASIC DESIGN

Timer

UART
CoProc.

SDRAM

custom
IF-logic

Display
Controller

42

Audio
Codec

EPROM

Power Supply

SRAM

Module-I

SRAM

SRAM

ASIC DESIGN

SDRAM

SDRAM

43

Course Objective & Outcomes

Syllabus

Evaluation Procedure

Integrated Circuit An Overview & Evolution

VLSI- Device Perspective

VLSI-System Perspective

Typical IC Design Flow

Integrated Circuit Food Chain

Discussion

Module-I

ASIC DESIGN

44

Typical Design Flow

Module-I

ASIC DESIGN

45

Module-I

ASIC DESIGN

46