TEHNICI DE PROIECTARE PENTRU

STRUCTURI VLSI
MARIUS ENACHESCU SALA B109 - MARIUS.ENACHESCU@DCAE.PUB.RO
2014
SEMESTRUL 1
MIERCURI 13-15

EVOLUTIA CALCULULUI CU AJUTORUL

COMPONENTELOR ELECTRONICE
Comunicarea
devine gratis!!!
Memoria
devine gratis!!!
Calculul
devine gratis!!!
1980

1990

2000

2010

SCHITA UNUI HOME COMPUTER

PREDICTED VS. REAL
1954 predicted for 2004

iMAC G5 @2004

MEMORIA CALCULATORULUI DEVINE GRATIS!!!

Today

1956

1952

Sau

IBM 701
Magnetic Tape
Drive

COMUNICATIA ?
Global growth of mobile, Internet, broadband, and fixed telephone
line subscribers

Source: www.itu.int/ITU-D/ict/statistics/
Source: Wiki

INTERFATA UTILIZATOR - MASINA DE CALCUL

Punch Card

Paper Tape

IBM Model M. Manufactured 1989.

Wiki: Paper tape relay operation at US

FAA's Honolulu flight service station in 1964.

True-3D Optical Ranging keyboard, 2005.

PRIMUL TRANSISTOR
1947 @ Bell Laboratories
William Shockley (seated at Brattain's
laboratory bench), John Bardeen (left)
and Walter Brattain (right)
NOBEL price in physics - 1956

PRIMUL CIRCUIT INTEGRAT

1947 @ Fairchild Semiconductor
Echipa condusa de Jay Last

PRIMUL PROCESOR INTEGRAT

1971 @ Intel
2300 tranzistori
108kHz

MOORES LAW

Small Scale Integration (SSI) 7404 inverter - 10 gates

Medium Scale Integration (MSI) 74161 counter 103 gates
Large Scale Integration (LSI) 8-bit uC 104 gates
Very Large Scale Integration (VLSI) incepand din anii 1980

1965 Gordon Moore a prezis dublarea numarului de tranzistoare odata la 18 luni,

In cazul Intel: dublarea s-a produs odata la 26 de luni.

VLSI WHAT MAKES IT POSSIBLE?

Stiinta de a proiacta si fabrica circuite electrinice:

Tehnologie complexa pusa in practica de generatii de cercetatori si practica

Metodologia de proiectare asistata de CAD tools
Fabricatie experti

Provocarile importante:

Cost redus
Putere consumata redusa
Aplicatii care vor schimba omenirea: industria masinilor, industria medicala.

EVOLUTIA CAD-TOOLS
Whats next?
Results
(design productivity)

Synthesis Cadence, Synopsys

Schematic entry Daisy, Mentor, Valid
Transistor entry Calma, Computervision, Magic
Effort (EDA tool effort)

Year
1950 - 1965

Design Tools
Manual Design

1965 - 1975

Layout editors
Automatic routers( for PCB)
Efficient partitioning algorithm

1975 - 1985

Automatic placement tools

Well Defined phases of design of circuits
Significant theoretical development in all phases

1985 1995

Performance driven placement and routing tools

Parallel algorithms for physical design
Significant development in underlying graph theory
Combinatorial optimization problems for layout

1995 2002

Interconnect layout optimization, Interconnectcentric design, physical-logical codesign

2002 - present

Physical synthesis with more vertical integration

for design closure (timing, noise, power, P/G/clock,
manufacturability)

DESIGN FLOW

CLOCK SPEED

Power Wall

F s-a dublat la fiecare 36 luni

FEATURE SIZE SCALING

Intel 4004 10um feature size

Intel Core 2 Duo 45nm feature size
Proces nou la fiecare 2-3 ani
Cu 30% mai mic
Efectele parazite din ERA nano
@45nm trade-offs power-delay

PRETUL UNUI TRANZISTOR

SCALAREA TENSIUNII DE ALIMENTARE

DENSITATEA DE PUTERE

FIGURE OF MERIT

ARM TEST CHIPS TRENDS

40G Dual-A9

40G Dual-A15

40G Dual-A15

28HPM Dual A57 /

Quad A53
DDR3 PHY

DDR3 PHY

SCP Cortex-M3
DMC400 Quad

Dual

CortexA57 NIC400 CortexA53

L2 2MB

CCI400

L2 1MB

MaliT624
HD
PCI
Express LCD

Elba

Aquila

Trends for ARM A-class cores:

Garuda

Increased performance at GHz frequencies

Multi-core, multi-voltage and multi-power domains configurations
Clock-gating and power-gating are standard
Technology scaling & VDD reduction, both I and I increase (even at constant
power)

Delivering higher current impacts VDD integrity

JUNO

Both IR (I) and Ldi/dt increase (I and t due to high Fmax)

VDD SCALING AND PDN IMPEDANCE

VDD scaling forces drastic drop in supply impedance

Even at constant power:

Vdd , Idd |Zrequired|
Impedance Requirements of
High-Performance Processors

Example:
Assume 100A supplied at 1V
10%VDD drop = 100mV
|Zrequired| = 100mV/100A = 1 m

Required Impedance ()

10

-1

10

Since around 90nm:

-2

10

|Zrequired| 1 m!
-3

10

0.6

0.5

0.4

0.3

Technology (m)

0.2

0.1

Source: Elad Alon, ISSCC 2009

22

REFERINTE
IEEE
1. CMOS Circuit Design, Layout and Simulation by R. Jacob Baker,H.W.Li, and D.E.
Boyce

2. Analog VLSI Signal and Information Process by Mohammed Ismail and Terri Faiz
3. Analysis and Design of Analog Integrated circuits by Paul R. Gray and
R.G.Meyer

4. Weste, Neil and Harris, David, Principles of CMOS VLSI Design - A Circuits and
Systems Perspective, 4th Edition Addison-Wesley, MA, 2010