MEMORANDUM

TO:

DR. CHANG

FROM:

JONATHAN TAYLOR

SUBJECT: CRIB: CONSOLIDATED RENAME, ISSUE, AND BYPASS

DATE:
CC:

12/11/14
N/A

The primary goal of this paper was to describe an architecture that replaced the typical
reorder buffer and other associated hardware with a single system that attempted to streamline
the entire process. It did this via a rearrangement of the typical hardware model in order to
achieve high instruction level parallelism(ILP). Additionally it found that their redesign not only
yielded similar performance to common OoO processors it was more power-efficient as well.
The major contribution of this paper was to note that a redesign of the overall way in
which we approach ILP could lead to gains as far as power and die size is concerned. This is
primarily due to their use of registers which are not codified through some form of memory,
rather they are determined logically. Additionally they looked into a version of their architecture
that utilized a deeper pipeline in order to abuse some of the potential for a faster clock speed.
Overall their major contribution was adding another architecture to those that need to be
considered when designing a processor.
Their major weaknesses are that they are limiting the architectures that they are
comparing their suggested processor to without really justifying why they are doing so. They
state that they will justify why they limited the x86 processors instruction window in section 5
but never actually do so. Additionally it seems as if they were ignoring some of the results that
occurred when looking at the power consumption of Int CRIB vs ALU+Bypass and FP CRIB vs
FP+Bypass which colors their results slightly.
The weaknesses are not such that they should deter future research. Therefore, I
personally wonder if there are ways to get around the int and fp limitations when comparing
them to an OoO processor and think that future research should attempt to determine whether
or not this is a viable thing to implement. Additionally a further line of study would be to compare
the operations of these processors when dealing with code that has multiple branch prediction
errors as well as potential cache coherence issues. This could yield further insight as to the
performance difference between the two architectures and may reveal whether or not the power
and die size tradeoff is acceptable when looking at OoO vs a CRIB-like architecture.
Lastly a potential exam question for this article would be to describe the reasons behind
why the power consumption of the CRIB is so low. Potential reasons given in the paper are things
such as a latch system being utilized over an actual register file as well as less hardware that is
needed for maintenance of the OoO execution which allows the power requirements to be
lowered.