Expt.

No: 07
Date:

MODELLING AND SIMULATION OF NMOS AND CMOS

CIRCUITS USING SPICE

AIM:
To model and simulate a NMOS and CMOS using Tanner T-Spice v13.0.

SOFTWARE REQUIRED:
Tanner T-Spice v13.0

THEORY:
(1) 2-Input NOR Gate with CMOS Logic
The NOR gate is a digital logic gate that implements logical NOR - it behaves according to
the truth table. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or
both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR
operator. It can also be seen as an AND gate with all the inputs inverted.
Symbol and Truth Table:

(2) 2-Input NAND Gate with CMOS Logic:

The NAND gate is a digital logic gate that implements logical NAND - it behaves
according to the truth table. A LOW output (0) results if both the inputs to the gate are HIGH (1);
if one or both input is LOW (0), a HIGH output (1) results. NAND is the result of the negation of
the AND operator.
Symbol and Truth Table:

(3) Differential amplifier with NMOS Logic

Differential Amplifier is the basic building block of every OP AMP and is the
basis of high speed digital logic circuit family, called Emitter Coupled Logic

(ECL) and they are commonly used for analog circuits. The name Differential
Amplifier is because of, the Amplifier will find out the Difference between two input
sources connected to the base of two transistors and amplify the Difference.

ALGORITHM:
1. Open S-Edit window.
2. Go to File -> New -> New design
3. Go to Cell -> New View
4. Add libraries file to the New Cell.
5. Instance the devices by using appropriate library files.
6. Save the design and setup the simulation.
7. Run design and observe waveforms.
8. Observe input and output waveform by giving appropriate inputs.

CMOS Circuit (NOR Gate) in T-SPICE:

Schematic Diagram:

T-SPICE Netlist:
.probe
.option probev
.option probei
.option probeq
.lib "C:\Documents and Settings\USER\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib"
+ tt
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out N_1 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Gnd N_2 Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 N_3 N_1 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 N_3 N_2 Out Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_1 Vdd Gnd DC 5
VVoltageSource_3 N_2 Gnd BIT({0100101111} )
VVoltageSource_2 N_1 Gnd BIT({0100101111} )
********* Simulation Settings - Analysis section *********
.tran/Powerup 20u 20u
.end

OUTPUT WAVEFORM:

CMOS Circuit (NAND Gate) in T-SPICE:

Schematic Diagram:

T-SPICE Netlist:
.probe
.option probev
.lib "C:\Documents and Settings\USER\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib"
+ tt
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out N_3 N_1 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Gnd N_2 N_1 Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_1 Out N_4 Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MPMOS_2 Vdd N_5 Out Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 N_4 N_3 BIT({010111000} PW=500n )
VVoltageSource_2 N_5 N_2 BIT({0100101111} PW=500n )
********* Simulation Settings - Analysis section *********
.tran 20u 20u
.end

OUTPUT WAVEFORM:

NMOS Circuit (Differential Amplifier ) in T-SPICE:

Schematic Diagram:

T-SPICE Netlist:
.probe
.option probev
.option probei
.option probeq
.lib "C:\Documents and Settings\USER\My Documents\Tanner EDA\Tanner Tools
v13.0\Libraries\Models\Generic_025.lib"
+ tt
********* Simulation Settings - Parameters and SPICE Options *********
*-------- Devices: SPICE.ORDER > 0 -------RResistor_1 Vdd Out R=10k
RResistor_2 Vdd Out R=10k
MNMOS_1 Out N_2 Gnd Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
MNMOS_2 Gnd N_3 Out Gnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u
VVoltageSource_3 Vdd Gnd DC 5
VVoltageSource_1 N_2 Gnd DC 5
VVoltageSource_2 N_3 Gnd DC 5
ICurrentSource_1 Gnd Gnd DC 5u
********* Simulation Settings - Analysis section *********
.tran/Powerup 20u 20u
.end

OUTPUT WAVEFORM:

RESULT:
Thus the CMOS and NMOS circuit is modeled and simulated using Tanner T-Spice v13.0.