BRANCH, CALL & TIME

DELAY LOOPS

Branching :
Conditional:
BC

XXXX (Label) ;Branch if C = 1

BNC YYYYY
BZ
BNZ
BN
BNN
BOV

;Branch if C = 0

Looping :

A set of instructions - repeating for a

number of times.
ADD 32 to WREG

MOVLW 24
MOVWF 50
MOVLW 32
ADDWF 50
ADDWF 50
ADDWF 50
ADDWF 50
ADDWG 50

ADD 32 to WREG

DECFSZ.. for
#include<P18F452.INC>
LOOPING
ORG 0
MOVLW 5H
#include<P18
MOVWF 50H
CLRF WREG
F452.INC>
ABOVE ADDLW 10H
DECFSZ 50H, F
ORG 0
GOTO ABOVE
MOVLW MOVWF 20H
5H
MOVWF

DECF AND BNZ are replaced by DECFSZ. Save memory space.

When GOTO is used, it can jump anywhere (Long). But, all conditional
jumps are short. Hence, for long jump, use DECFSZ and GOTO.

Loop Inside the Loop.

Nested Loop

NESTED LOOP
; SUBROUTINE

Maximum count in a register is 255 (FF).

LOOP INSIDE A LOOP NESTED

ORG 80H

DELAY1

LOOP..

;Main program
ORG 50

MOVWF 21H
L2

MOVWF 22H

L1

NOP

MOVLW 5H

NOP

movwf 00h

DECF 22H

movlw 10h

BNZ L1

AGAIN

addlw 25h

COMF PORTC

DECF 21H
BNZ L2

Write a program loop to Read PORTB,

complement it and output this data in PORTC,
repeat it 50000 times.

The Opcode of Branch

All conditional branches are short jumps.
instruction

Means Address of the target must be within 256

bytes of the content of the PC.
First Byte in the instruction is Opcode and the
second byte is the relative address.
If the second byte is positive, the jump is forward. If
it is negative, jumps backward.
The second byte can be a value between -128 and
+127 (MSB is for sign Remaining 7 bits for
magnitude : 27 = 128).

Address of the target..

Target address is relative to the content of the PC.

Address of the next instruction (Content of PC) +

2 * second byte of the branching instruction is the target
address.

This is because each instruction occupies 2 memory

locations (two consecutive addresses).

instruction

E1 is the opcode for BNZ. 02 is the relative address.

E3 is the opcode for BNC. F9 is the relative address (- 7).

GOTO.

GOTO IS A LONG JUMP.

ie., it can jump to any memory location

in the

2M memory.

A 32 bit instruction with 12 bits as

opcode.

Remaining 20 bits represent

the 20 bit address

of the target

location.
As the Is
lsbitissufficient?..........
always 0 (Even address

only), it can take care of the 2M

GOTO

BRA .

Another unconditional branch.

2 byte instruction

First 5 bits are opcode and the rest (lower 11

bits) are relative address of the target
location. (000-7FF). MSB is for sign bit Remaining 10 bits means 1 k.

BRA .

Forward and Backward jumps are possible.

- 1024 (1k) to + 1023 bytes relative to the

current content of PC.

Is like a conditional branch except that the

11 bits are used for offset addressing instead
of 8 bits in conditional branching.

Relative address is signed number 10 bits

BRA

CALL instruction.

Used to call a subroutine made to

avoid code

repetition.

4 Byte instruction.

12 bits opcode and 20 bit address of

subroutine

(Similar to

GOTO : LSB =

0).

Subroutine can be anywhere in the 2M

memory.

CALL instruction.

PC is loaded with the address of the

first instruction of

the subroutine.

After finishing the execution of the

subroutine, the last

instruction of all

subroutines, RETURN transfers control

back to the caller.

Stack .

Stack is used to store very critical

information temporarily.

LIFO Memory.

Stores the content of the registers

reused in the called routine (eg. : PC,
Status register).

Needs as the number of registers are

limited.

Stack Pointer

Register - used to access the stack

Address of the TOS.

5 bit size 00H to 1FH : 32 (25)

locations possible.

Contains the location of the last stored

data

(Next data to be stored in

location
SP+1)
Stack
. data.
Hence,
location
0 is not
availableTop
for the
Thus
we have only 31 locations available for the

As
the
data
is
pushed
into
the
stack,
data storage in stack.

PIC Stack 31 21

PUSH POP.

Storing to stack is called PUSH.

In PIC, each CALL results in a PUSH.

PC is

stored to stack, SP is

automatically incremented by one

Maximum 31 nested CALL s are
possible.

Taking back from stack to registers is

called

POP.

RCALL . (Relative
2 Byte instruction (Call is 4 Byte
CALL)

instruction)

Saves ROM 2 Bytes /

CALL.

11 bits are used for RELATIVE address.

Address of the subroutine (SR) must

be within 2k address from the current
PC content.

[PC] + 2* Relative address = Address

CALL Vs RCALL

CALL Vs RCALL

62 + 2 *00F = 80

PIPELINING

To increase the speed of the

processing.

In PIC, 2 phases FETCH, EXECUTE.

CPU will fetch and execute at the

same time.

Instruction Cycle Time

Time taken by the CPU to execute an
.

instruction.

Most of the instructions take only one

or two

instruction cycles to execute

(Number of

cycles for each instruction

will be provided by the

manufacturer).

Depends on the Oscillator, externally

Instruction Cycle Time

The
.following shows the crystal frequency
for three different PIC-based systems.
Find the period of the instruction cycle in
each case.
(a) 4 MHz (b) 16 MHz
(c) 20 MHz
(a)

4/4 = 1 MHz;

instruction cycle time is 1/1 MHz

= 1 us (microsecond)

(b) 16 MHz/4 = 4 MHz; instruction cycle time = 1/4 MHz

= 0.25 us = 250 ns (nanosecond)
(c) 20 MHzl4 = 5 MHz; instruction cycle = 1/5 MHz = 0.2 us
= 200 ns

Branch penalty

Overlapping of fetch and execution of

the instruction is widely used in C such
as PIC.

For the concept of pipelining to work,

we
need a buffer or queue in which some
instructions are pre-fetched and ready to
be executed.

Branch penalty

In case of a Flush, the execution unit

must wait until the fetch unit fetches the
new instruction.

Called a branch penalty.

Is the extra instruction cycle needed
to fetch the instruction from the
branched target location instead of
executing the instruction

right below

Branch penalty

Vast majority of PIC instructions take

only

one

instruction cycle, some instructions

take two or three
instruction cycles.

Eg. : GOTO, BRA, CALL, and all the

conditional
branch instructions.

Instruction execution
For
a PIC18 system of 16 MHz, find how long
time
it takes to execute each of the following
instructions:

(a) MOVLW (1) (b) DECF (1) (c) MOVWF (1)

(d) ADDLW (1) (e) NOP (1) (f) GOTO (2) (g) CALL

(2) (h) BNZ (2 /1)

The machine cycle for a system of 16 MHz is 0.25 s.
Given in red shows instruction cycles for each of the

(a)

MOVLW Ox55

Inst.
Cycles
1

(b)

DECF MYREG

1x0.25 s = 0.25s

(c)

MOVWF

1x0.25 s = 0.25s

(d)

ADDLW

1x0.25 s = 0.25 s

(e)

NOP

1x0.25 s = 0.25 s

(f)

GO TO

2x0.25 s =

(g)

CALL

2 x0.25 s = 0.5 s

Instruction

(h)

BNZ

2/1

Time to
execute
1x0.25 s = 0.25 s

(0.5 s
Taken, 0.25 s if it
falls through.)

0.5 s
0.5 /
0.25 s

Delay in the loop

Find the time delay in executing the

code given below if the crystal
INSTRUCTION

CYC
LES

MOVLW

FF

MOVWF

20H

frequency is 16 MHz:
TOP

NOP

NOP

NOP

DECF 20H,F

BNZ

2 /1

TOP

RETURN
Time delay of
[( 255x6)+ 1 +1 + 11] 0.25 s = 383.25
s. As the last BNZ takes only 1 cycle, 383 s is the

PIC MULTISTAGE EXECUTION

PIPELINE
Use super pipeline to increase the
instruction execution speed.

Split the phases (Execution here) in to

many small steps, that are executed in
parallel.

Execution of many instructions are

overlapped.

Speed is limited to the slowest stage of

PIC MULTISTAGE EXECUTION

PIPELINE
In
PIC 18, the execution of instruction
takes 4 clock periods of the oscillator.