Ug130 (Spartan3kit)

Spartan-3
Starter Kit Board

User Guide
UG130 (v1.1) May 13, 2005
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Spartan-3 Starter Kit Board User Guide

UG130 (v1.1) May 13, 2005
The following table shows the revision history for this document.
Version
Revision
04/26/04
1.0
Initial Xilinx release.
06/07/04
1.0.1
Minor modifications for printed release.
07/21/04
1.0.2
Added information on auxiliary serial port connections to Chapter 7.
05/13/05
1.1
Clarified that SRAM IC10 shares eight lower data lines with A1 connector.
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UG130 (v1.1) May 13, 2005
Table of Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1: Introduction
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Component Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2: Fast, Asynchronous SRAM

Address Bus Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable and Output Enable Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRAM Data Signals, Chip Enables, and Byte Enables . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3: Four-Digit, Seven-Segment LED Display

Chapter 4: Switches and LEDs
Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Push Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 5: VGA Port

Signal Timing for a 60Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 6: PS/2 Mouse/Keyboard Port

Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 7: RS-232 Port

Chapter 8: Clock Sources
Chapter 9: FPGA Configuration Modes and Functions
FPGA Configuration Mode Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Program Push Button/DONE Indicator LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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Chapter 10: Platform Flash Configuration Storage

Platform Flash Jumper Options (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Read Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disable Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
38
39
40
Chapter 11: JTAG Programming/Debugging Ports

JTAG Header (J7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5). . . . . . . . . . . . . . . . . . 42
Chapter 12: Power Distribution

AC Wall Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 13: Expansion Connectors and Boards

Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
A1 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A2 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
B1 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Expansion Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix A: Board Schematics

Appendix B: Reference Material for Major Components
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UG130 (v1.1) May 13, 2005
Preface
About This Guide

This user guide describes the components and operation of the Spartan-3 Starter Kit
Board.
Guide Contents
This manual contains the following chapters:
Chapter 1, Introduction
Chapter 2, Fast, Asynchronous SRAM
Chapter 3, Four-Digit, Seven-Segment LED Display
Chapter 4, Switches and LEDs
Chapter 5, VGA Port
Chapter 6, PS/2 Mouse/Keyboard Port
Chapter 7, RS-232 Port
Chapter 8, Clock Sources
Chapter 9, FPGA Configuration Modes and Functions
Chapter 10, Platform Flash Configuration Storage
Chapter 11, JTAG Programming/Debugging Ports
Chapter 12, Power Distribution
Chapter 13, Expansion Connectors and Boards
Appendix A, Board Schematics
Appendix B, Reference Material for Major Components

UG130 (v1.1) May 13, 2005
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Preface: About This Guide
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UG130 (v1.1) May 13, 2005
Chapter 1
Introduction
The Xilinx Spartan-3 Starter Kit provides a low-cost, easy-to-use development and
evaluation platform for Spartan-3 FPGA designs.
Key Components and Features

Figure 1-1 shows the Spartan-3 Starter Kit board, which includes the following
components and features:
200,000-gate Xilinx Spartan-3 XC3S200 FPGA in a 256-ball thin Ball Grid Array
package (XC3S200FT256) 1
4,320 logic cell equivalents
Twelve 18K-bit block RAMs (216K bits)
Twelve 18x18 hardware multipliers
Four Digital Clock Managers (DCMs)
Up to 173 user-defined I/O signals
2Mbit Xilinx XCF02S Platform Flash, in-system programmable configuration

PROM 2
1Mbit non-volatile data or application code storage available after FPGA

configuration
Jumper options allow FPGA application to read PROM data or FPGA

configuration from other sources 3
1M-byte of Fast Asynchronous SRAM (bottom side of board, see Figure 1-3)
Two 256Kx16 ISSI IS61LV25616AL-10T 10 ns SRAMs
Configurable memory architecture

-
Single 256Kx32 SRAM array, ideal for MicroBlaze code images
Two independent 256Kx16 SRAM arrays
Individual chip select per device
Individual byte enables
3-bit, 8-color VGA display port
9-pin RS-232 Serial Port
DB9 9-pin female connector (DCE connector)
RS-232 transceiver/level translator
Uses straight-through serial cable to connect to computer or workstation serial

port
Second RS-232 transmit and receive channel available on board test points

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Digilent Low-Cost 23
Parallel Port to JTAG Included
Cable
Parallel Cable IV 24
MutliPro Desktop Tool
JTAG Connector
Low-Cost JTAG
Download Cable
Connector
22
A1 Expansion
Header
21
XCF02S 2Mbit
Configuration
PROM
A2 Expansion
Header
20
Platform Flash
Option Jumpers
B1 Expansion
Header
19
256Kx16
10ns SRAM
Configuration
DONE LED
18
PROGRAM
Push Button
17
Configuration
Mode Select
Jumpers
16
4
1
256Kx16
10ns SRAM
5
8-color
VGA Port
RS-232 Port
Serial Port
XC3S200
Spartan-3
FPGA
RS-232
Driver
Auxiliary 15
Oscillator Socket
PS/2 Port
50 MHz
Oscillator
4 Character
7-Segment LED
14
10
11
13
4 Push Buttons
8 Slide Switches
8 LEDs
12
VCCO
Power On
LED
26
3.3V 27
Regulator
2.5V 28
Regulator
1.2V 29
Regulator
5 VDC, 2A Supply
AC Wall Adapter
100-240V AC Input Included
50-60 Hz 25
UG130_c1_01_042504
Figure 1-1: Xilinx Spartan-3 Starter Kit Board Block Diagram
PS/2-style mouse/keyboard port
Four-character, seven-segment LED display
Eight slide switches
Eight individual LED outputs
Four momentary-contact push button switches
9
10
11
12
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UG130 (v1.1) May 13, 2005
Component Locations
50 MHz crystal oscillator clock source (bottom side of board, see Figure 1-3)
Socket for an auxiliary crystal oscillator clock source
FPGA configuration mode selected via jumper settings
Push button switch to force FPGA reconfiguration (FPGA configuration happens

automatically at power-on) 17
LED indicates when FPGA is successfully configured
Three 40-pin expansion connection ports to extend and enhance the Spartan-3 Starter
Kit Board 19 20 21
14
15
16
18
See www.xilinx.com/s3boards for compatible expansion cards
Compatible with Digilent, Inc. peripheral boards

https://digilent.us/Sales/boards.cfm#Peripheral
FPGA serial configuration interface signals available on the A2 and B1 connectors

-
PROG_B, DONE, INIT_B, CCLK, DONE
JTAG port
Digilent JTAG download/debugging cable connects to PC parallel port
JTAG download/debug port compatible with the Xilinx Parallel Cable IV and
MultiPRO Desktop Tool 24
AC power adapter input for included international unregulated +5V power

supply 25
Power-on indicator LED
26
On-board 3.3V
28
22
for low-cost download cable
27
, 2.5V
, and 1.2V
29
23
23
regulators
Component Locations
Figure 1-2 and Figure 1-3 indicate the component locations on the top side and bottom side
of the board, respectively.

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21
20
A1 Expansion Connector
31
27
24
VGA
16
17
XILINX
XC3S200
FPGA
18
DONE
25
19
2Mbit
PlatformFlash
B1 Expansion Connector
3.3V
22
5
PROG
POWER
POWER
26
RS-232
RS-232
7
15
10
12
30
PS/2
9
11
13
ug130_c1_02_042704
Figure 1-2: Xilinx Spartan-3 Starter Kit Board (Top Side)
256Kx16
SRAM
256Kx16
SRAM
2.5V
28
29
50
MHz
1.2V
14
ug130_c1_03_042704
Figure 1-3: Xilinx Spartan-3 Starter Kit Board (Bottom Side)
10
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UG130 (v1.1) May 13, 2005
Chapter 2
Fast, Asynchronous SRAM

The Spartan-3 Starter Kit board has a megabyte of fast asynchronous SRAM, surfacemounted to the backside of the board. The memory array includes two 256Kx16 ISSI
IS61LV25616AL-10T 10 ns SRAM devices, as shown in Figure 2-1. A detailed schematic
appears in Figure A-8.
ISSI
256Kx16 SRAM
(10 ns)
(see
Table
(see
Table2-3)
2-3)
I/O[15:0]
A[17:0]
CE1
(P7)
CE
UB1
(T4)
UB
LB1
(P6)
LB
IC10
WE
OE
Spartan-3
FPGA
ISSI
256Kx16 SRAM
(10 ns)
(see
Table
(see
Table2-4)
2-4)
I/O[15:0]
(see
Table
(see
Table2-1)
2-1)
A[17:0]
CE2
(N5)
CE
UB2
(R4)
UB
LB2
(P5)
LB
WE
(G3)
WE
OE
(K4)
OE
IC11
(xx) = FPGA pin number

UG130_c2_01_042604
Figure 2-1: FPGA to SRAM Connections

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The SRAM array forms either a single 256Kx32 SRAM memory or two independent
256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable
(OE#), and address (A[17:0]) signals. However, each device has a separate chip select
enable (CE#) control and individual byte-enable controls to select the high or low byte in
the 16-bit data word, UB and LB, respectively.
The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it
alternately provides high-density data storage for a variety of applications, such as digital
signal processing (DSP), large data FIFOs, and graphics buffers.
Address Bus Connections

Both 256Kx16 SRAMs share 18-bit address control lines, as shown in Table 2-1. These
address signals also connect to the A1 Expansion Connector (see Expansion Connectors,
page 47).
Table 2-1: External SRAM Address Bus Connections to Spartan-3 FPGA
12
Address Bit
FPGA Pin
A1 Expansion Connector Pin
A17
L3
35
A16
K5
33
A15
K3
34
A14
J3
31
A13
J4
32
A12
H4
29
A11
H3
30
A10
G5
27
A9
E4
28
A8
E3
25
A7
F4
26
A6
F3
23
A5
G4
24
A4
L4
14
A3
M3
12
A2
M4
10
A1
N3
A0
L5
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Write Enable and Output Enable Control Signals
Write Enable and Output Enable Control Signals

Both 256Kx16 SRAMs share common output enable (OE#) and write enable (WE#) control
lines, as shown in Table 2-2. These control signals also connect to the A1 Expansion
Connector (refer to Expansion Connectors, page 47).
Table 2-2: External SRAM Control Signal Connections to Spartan-3 FPGA

Signal
FPGA Pin
OE#
K4
16
WE#
G3
18
SRAM Data Signals, Chip Enables, and Byte Enables

The data signals, chip enables, and byte enables are dedicated connections between the
FPGA and SRAM. Table 2-3 shows the FPGA pin connections to the SRAM designated
IC10 in Figure A-8. Table 2-4 shows the FPGA pin connections to SRAM IC11. To disable an
SRAM, drive the associated chip enable pin High.
Table 2-3: SRAM IC10 Connections

Signal
FPGA Pin
IO15
R1
IO14
P1
IO13
L2
IO12
J2
IO11
H1
IO10
F2
IO9
P8
IO8
D3
IO7
B1
19
IO6
C1
17
IO5
C2
15
IO4
R5
13
IO3
T5
11
IO2
R6
IO1
T8
IO0
N7
CE1 (chip enable IC10)
P7
UB1 (upper byte enable IC10)
T4
LB1 (lower byte enable IC10)
P6

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Table 2-4: SRAM IC11 Connections
14
Signal
FPGA Pin
IO15
N1
IO14
M1
IO13
K2
IO12
C3
IO11
F5
IO10
G1
IO9
E2
IO8
D2
IO7
D1
IO6
E1
IO5
G2
IO4
J1
IO3
K1
IO2
M2
IO1
N2
IO0
P2
CE2 (chip enable IC11)
N5
UB2 (upper byte enable IC11)
R4
LB2 (lower byte enable IC11)
P5
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Chapter 3
Four-Digit, Seven-Segment LED Display

The Spartan-3 Starter Kit board has a four-character, seven segment LED display
controlled by FPGA user-I/O pins, as shown in Figure 3-1. Each digit shares eight common
control signals to light individual LED segments. Each individual character has a separate
anode control input. A detailed schematic for the display appears in Figure A-2.
The pin number for each FPGA pin connected to the LED display appears in parentheses.
To light an individual signal, drive the individual segment control signal Low along with
the associated anode control signal for the individual character. In Figure 3-1, for example,
the left-most character displays the value 2. The digital values driving the display in this
example are shown in blue. The AN3 anode control signal is Low, enabling the control
inputs for the left-most character. The segment control inputs, A through G and DP, drive
the individual segments that comprise the character. A Low value lights the individual
segment, a High turns off the segment. A Low on the A input signal, lights segment a of
the display. The anode controls for the remaining characters, AN[2:0] are all High, and
these characters ignore the values presented on A through G and DP.
AN3 (E13)
AN2 (F14)
AN1 (G14)
AN0 (D14)
(E14)
(N16)
1 DP
(F13)
(R16)
(G13)
a
b
c
d
(N15)
dp
c
d
dp
b
g
c
d
dp
c
d
dp
(P15)
(P16)
UG130_c3_01_042704
Figure 3-1: Seven-Segment LED Digit Control

Table 3-1 lists the FPGA connections that drive the individual LEDs comprising a sevensegment character. Table 3-2 lists the connections to enable a specific character. Table 3-3
shows the patterns required to display hexadecimal characters.

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Table 3-1: FPGA Connections to Seven-Segment Display (Active Low)

Segment
FPGA Pin
E14
G13
N15
P15
R16
F13
N16
DP
P16
Table 3-2: Digit Enable (Anode Control) Signals (Active Low)

Anode Control
AN3
AN2
AN1
AN0
FPGA Pin
E13
F14
G14
D14
Table 3-3: Display Characters and Resulting LED Segment Control Values
16
Character
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The LED control signals are time-multiplexed to display data on all four characters, as
shown in Figure 3-2. Present the value to be displayed on the segment control inputs and
select the specified character by driving the associated anode control signal Low. Through
persistence of vision, the human brain perceives that all four characters appear
simultaneously, similar to the way the brain perceives a TV display.
AN3
AN2
AN1
AN0
{A,B,C,D,E,F,G,DP}
DISP3
DISP2
DISP1
DISP0
UG130_c3_02_042404
Figure 3-2: Drive Anode Input Low to Light an Individual Character

This scanning technique reduces the number of I/O pins required for the four
characters. If an FPGA pin were dedicated for each individual segment, then 32 pins are
required to drive four 7-segment LED characters. The scanning technique reduces the
required I/O down to 12 pins. The drawback to this approach is that the FPGA logic must
continuously scan data out to the displaysa small price to save 20 additional I/O pins.

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Chapter 4
Switches and LEDs

Slide Switches
The Spartan-3 Starter Kit board has eight slide switches, indicated as 11 in Figure 1-2. The
switches are located along the lower edge of the board, toward the right edge. The switches
are labeled SW7 through SW0. Switch SW7 is the left-most switch, and SW0 is the rightmost switch. The switches connect to an associated FPGA pin, as shown in Table 4-1. A
detailed schematic appears in Figure A-2.
Table 4-1: Slider Switch Connections

Switch
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
FPGA Pin
K13
K14
J13
J14
H13
H14
G12
F12
When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board. A 4.7K series resistor provides nominal input protection.
Push Button Switches

The Spartan-3 Starter Kit board has four momentary-contact push button switches,
indicated as 13 in Figure 1-2. These push buttons are located along the lower edge of the
board, toward the right edge. The switches are labeled BTN3 through BTN0. Push button
switch BTN3 is the left-most switch, BTN0 the right-most switch. The push button
switches connect to an associated FPGA pin, as shown in Table 4-2. A detailed schematic
appears in Figure A-2.
Table 4-2: Push Button Switch Connections

Push Button
BTN3 (User Reset)
BTN2
BTN1
BTN0
FPGA Pin
L14
L13
M14
M13
Pressing a push button generates a logic High on the associated FPGA pin. Again, there is
no active debouncing circuitry on the push button.
The left-most button, BTN3, is also the default User Reset pin. BTN3 electrically behaves
identically to the other push buttons. However, when applicable, BTN3 resets the provided
reference designs.

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Chapter 4: Switches and LEDs
LEDs
The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above
the push button switches, indicated by 12 in Figure 1-2. The LEDs are labeled LED7
through LED0. LED7 is the left-most LED, LED0 the right-most LED. Table 4-3 shows the
FPGA connections to the LEDs.
Table 4-3: LED Connections to the Spartan-3 FPGA

LED
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
FPGA Pin
P11
P12
N12
P13
N14
L12
P14
K12
The cathode of each LED connects to ground via a 270 resistor. To light an individual
LED, drive the associated FPGA control signal High, which is the opposite polarity from
lighting one of the 7-segment LEDs.
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Chapter 5
VGA Port
The Spartan-3 Starter Kit board includes a VGA display port and DB15 connector,
indicated as 5 in Figure 1-2. Connect this port directly to most PC monitors or flat-panel
LCD displays using a standard monitor cable.
Pin 5
Pin 1
Pin 10
Pin 6
Pin 15
Pin 11
DB15 VGA Connector
(front view)
DB15
Connector
270
Red
1
6
11
(R12)
(T12)
(R11)
270
Green
2
7
12
270
Blue
3
8
Horizontal Sync
HS (R9)
13
4
9
Vertical Sync
VS
14
(T10)
10
15
GND
UG130_c5_01_042604
Figure 5-1: VGA Connections from Spartan-3 Starter Kit Board

As shown in Figure 5-1, the Spartan-3 FPGA controls five VGA signals: Red (R), Green (G),
Blue (B), Horizontal Sync (HS), and Vertical Sync (VS), all available on the VGA connector.
The FPGA pins that drive the VGA port appear in Table 5-1. A detailed schematic is in
Figure A-7.

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Chapter 5: VGA Port
Table 5-1: VGA Port Connections to the Spartan-3 FPGA

Signal
FPGA Pin
Red (R)
R12
Green (G)
T12
Blue (B)
R11
Horizontal Sync (HS)
R9
Vertical Sync (VS)
T10
Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green,
and Blue. The series resistor uses the 75 VGA cable termination to ensure that the color
signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level.
Drive the R, G, and B signals High or Low to generate the eight possible colors shown in
Table 5-2.
Table 5-2: 3-Bit Display Color Codes

Red (R)
Green (G)
Blue (B)
Resulting Color
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics
Standards Association (VESA). The following VGA system and timing information is
provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode.
For more precise information or for information on higher VGA frequencies, refer to
documents available on the VESA website or other electronics websites:
Video Electronics Standards Association

http://www.vesa.org
VGA Timing Information

http://www.epanorama.net/documents/pc/vga_timing.html
Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode
rays) to display information on a phosphor-coated screen. LCD displays use an array of
switches that can impose a voltage across a small amount of liquid crystal, thereby
changing light permitivity through the crystal on a pixel-by-pixel basis. Although the
following description is limited to CRT displays, LCD displays have evolved to use the
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Signal Timing for a 60Hz, 640x480 VGA Display
same signal timings as CRT displays. Consequently, the following discussion pertains to
both CRTs and LCD displays.
Within a CRT display, current waveforms pass through the coils to produce magnetic fields
that deflect electron beams to transverse the display surface in a raster pattern,
horizontally from left to right and vertically from top to bottom. As shown in Figure 5-2,
information is only displayed when the beam is moving in the forward directionleft to
right and top to bottomand not during the time the beam returns back to the left or top
edge of the display. Much of the potential display time is therefore lost in blanking
periods when the beam is reset and stabilized to begin a new horizontal or vertical display
pass.
pixel 0,0
pixel 0,639
640 pixels are displayed each

time the beam traverses the screen
VGA Display
Current
through the
horizontal
deflection
coil
pixel 479,0
pixel 479,639
Retrace: No
information
is displayed
during
this time
Stable current ramp: Information is

displayed during this time
Total horizontal time

Horizontal display time
time
"back porch"
retrace time
"back porch"
HS
Horizontal sync signal
sets the retrace frequency
"front porch"
UG130_c5_02_051305
Figure 5-2: CRT Display Timing Example

The size of the beams, the frequency at which the beam traces across the display, and the
frequency at which the electron beam is modulated determine the display resolution.

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Chapter 5: VGA Port
Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The Spartan-3 Starter Kit board uses three bits per pixel, producing
one of the eight possible colors shown in Table 5-2. The controller indexes into the video
data buffer as the beams move across the display. The controller then retrieves and applies
video data to the display at precisely the time the electron beam is moving across a given
pixel.
As shown in Figure 5-2, the VGA controller generates the HS (horizontal sync) and VS
(vertical sync) timings signals and coordinates the delivery of video data on each pixel
clock. The pixel clock defines the time available to display one pixel of information. The VS
signal defines the refresh frequency of the display, or the frequency at which all
information on the display is redrawn. The minimum refresh frequency is a function of the
displays phosphor and electron beam intensity, with practical refresh frequencies in the
60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh
frequency defines the horizontal retrace frequency.
VGA Signal Timing

The signal timings in Table 5-3 are derived for a 640-pixel by 480-row display using a
25 MHz pixel clock and 60 Hz 1 refresh. Figure 5-3 shows the relation between each of the
timing symbols. The timing for the sync pulse width (TPW) and front and back porch
intervals (TFP and TBP) are based on observations from various VGA displays. The front
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 5-3: 640x480 Mode VGA Timing

Symbol
Vertical Sync
Parameter
Horizontal Sync
Time
Clocks
Lines
Time
Clocks
Sync pulse time
16.7 ms
416,800
521
32 s
800
TDISP
Display time
15.36 ms
384,000
480
25.6 s
640
TPW
Pulse width
64 s
1,600
3.84 s
96
TFP
Front porch
320 s
8,000
10
640 ns
16
TBP
Back porch
928 s
23,200
29
1.92 s
48
TS
TS
TFP
TDISP
TBP
TPW
UG130_c5_03_051305
Figure 5-3: VGA Control Timing
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VGA Signal Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board fast SRAM is an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.

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26
Chapter 5: VGA Port
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Chapter 6
PS/2 Mouse/Keyboard Port

The Spartan-3 Starter Kit board includes a PS/2 mouse/keyboard port and the standard 6pin mini-DIN connector, labeled J3 on the board and indicated as 9 in Figure 1-2.
Figure 6-1 shows the PS/2 connector, and Table 6-1 shows the signals on the connector.
Only pins 1 and 5 of the connector attach to the FPGA. A detailed schematic appears in
Figure A-7.
1
3
5
2
4
6
UG130_c6_01_042404
Figure 6-1: PS/2 DIN Connector

Table 6-1: PS/2 Connections to the Spartan-3 FPGA
PS/2 DIN Pin
Signal
DATA (PS2D)
Reserved
GND
Voltage Supply
CLK (PS2C)
Reserved
FPGA Pin
M15
GND
M16
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a
host device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data.
Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit
words that include a start, stop and odd parity bit. However, the data packets are
organized differently for a mouse and keyboard. Furthermore, the keyboard interface
allows bidirectional data transfers so the host device can illuminate state LEDs on the
keyboard.
The PS/2 bus timing appears Table 6-2 and Figure 6-2. The clock and data signals are only
driven when data transfers occur, and otherwise they are held in the idle state at logic
High. The timings define signal requirements for mouse-to-host communications and

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27
bidirectional keyboard communications. As shown in Figure 6-2, the attached keyboard or

mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
Table 6-2: PS/2 Bus Timing

Symbol
Parameter
Min
Max
TCK
Clock High or Low time
30 s
50 s
TSU
Data-to-clock setup time
5 s
25 s
THLD
Clock-to-data hold time
5 s
25 s
Edge 0
TCK TCK
Edge 10
CLK (PS2C)
THLD
TSU
DATA (PS2D)
'0' start bit
'1' stop bit

UG130_c6_02_042404
Figure 6-2: PS/2 Bus Timing Waveforms

The following site contains additional information on the PS/2 bus protocol:
PS/2 Mouse/Keyboard Protocol

http://panda.cs.ndsu.nodak.edu/~achapwes/PICmicro/PS2/ps2.htm
Keyboard
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
Figure 6-3.
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends a F0 key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed
or not. The host determines which character is intended.
Some keys, called extended keys, send an E0 ahead of the scan code and furthermore,
they may send more than one scan code. When an extended key is released, a E0 F0 keyup code is sent, followed by the scan code.
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Keyboard
ESC
76
`~
0E
1!
16
TAB
0D
Caps Lock
58
Shift
12
F1
05
F2
06
2@
1E
3#
26
Q
15
W
1D
A
1C
F4
0C
4$
25
E
24
S
1B
Z
1Z
Ctrl
14
F3
04
5%
2E
R
2D
D
23
X
22
F5
03
6^
36
T
2C
F
2B
C
21
F6
0B
7&
3D
Y
35
G
34
V
2A
F8
0A
8*
3E
U
3C
H
33
B
32
Alt
11
F7
83
9(
46
I
43
J
3B
N
31
F10
09
-_
4E
=+
55
0)
45
O
44
K
42
M
3A
F9
01
P
4D
L
4B
,<
41
Space
29
[{
54
;:
4C
>.
49
F11
78
F12
07
E0 75
Back Space
E0 74
66
]}
5B
'"
52
\|
5D
E0 6B
Enter
5A
/?
4A
E0 72
Shift
59
Alt
E0 11
Ctrl
E0 14
UG130_c6_03_042404
Figure 6-3: PS/2 Keyboard Scan Codes

The host can also send data to the keyboard. Table 6-3 provides a short list of some oftenused commands.
Table 6-3: Common PS/2 Keyboard Commands

Command
Description
ED
Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard acknowledges receipt of
an ED command by replying with an FA, after which the host sends another byte to set LED
status. The bit positions for the keyboard LEDs appear in Table 6-4. Write a 1 to the specific bit to
illuminate the associated keyboard LED.
Table 6-4: Keyboard LED Control

7
Ignored
Caps
Lock
Num
Lock
Scroll
Lock
EE
Echo. Upon receiving an echo command, the keyboard replies with the same scan code EE.
F3
Set scan code repeat rate. The keyboard acknowledges receipt of an F3 by returning an FA,
after which the host sends a second byte to set the repeat rate.
FE
Resend. Upon receiving a resend command, the keyboard resends the last scan code sent.
FF
Reset. Resets the keyboard.

The keyboard sends data to the host only when both the data and clock lines are High, the
Idle state.
Because the host is the bus master, the keyboard checks whether the host is sending data
before driving the bus. The clock line can be used as a clear to send signal. If the host
pulls the clock line Low, the keyboard must not send any data until the clock is released.
The keyboard sends data to the host in 11-bit words that contain a 0 start bit, followed by
eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a 1
stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to
30 kHz, and data is valid on the falling edge of the clock as shown in Figure 6-2.

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The following site contains more information on PS/2 keyboard interfaces:
The AT-PS/2 Keyboard Interface

http://panda.cs.ndsu.nodak.edu/~achapwes/PICmicro/keyboard/atkeyboard.html
Mouse
A mouse generates a clock and data signal when moved; otherwise, these signals remain
High indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit
words to the host. Each of the 11-bit words contains a 0 start bit, followed by 8 data bits
(LSB first), followed by an odd parity bit, and terminated with a 1 stop bit. Each data
transmission contains 33 total bits, where bits 0, 11, and 22 are 0 start bits, and bits 10, 21,
and 32 are 1 stop bits. The three 8-bit data fields contain movement data as shown in
Figure 6-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse status byte

1
Start bit
Idle state
X direction byte
1 XS YS XV YV P
Stop bit
Y direction byte
0 X0 X1 X2 X3 X4 X5 X6 X7 P
0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 P
Stop bit
Start bit
Stop bit
Idle state
Start bit
UG130_c6_04_042404
Figure 6-4: PS/2 Mouse Transaction

As shown in Figure 6-5, a PS/2 mouse employs a relative coordinate system wherein
moving the mouse to the right generates a positive value in the X field, and moving to the
left generates a negative value. Likewise, moving the mouse up generates a positive value
in the Y field, and moving down represents a negative value. The XS and YS bits in the
status byte define the sign of each value, where a 1 indicates a negative value.
+Y values (YS=0)
-X values
(XS=1)
+X values
(XS=0)
-Y values (YS=1)
UG130_c6_05_042404
Figure 6-5: The Mouse Uses a Relative Coordinate System to Track Movement
The magnitude of the X and Y values represent the rate of mouse movement. The larger the
value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when
the X or Y values exceed their maximum value, an overflow condition. A 1 indicates
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Voltage Supply
when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat
every 50 ms or so.
The L and R fields in the status byte indicate Left and Right button presses. A 1 indicates
that the associated mouse button is being pressed.
The following site contains additional information on interfacing to a PS/2-style mouse:
The PS/2 Mouse Interface

http://panda.cs.ndsu.nodak.edu/~achapwes/PICmicro/mouse/mouse.html
Voltage Supply
Most modern keyboards and mice work equally well from a 3.3V or 5V supply. The voltage
supply for the PS/2 port is selectable via the JP2 jumper, indicated as 30 in Figure 1-2,
located immediately above the PS/2 connector along the right edge. The 3.3V setting is
preferred as the FPGAs output signals operate from the 3.3V supply. The JP2 jumper
should be positioned as shown in Table 6-5 by default.
Jumper JP2
Setting
3.3V
(DEFAULT)
3.3V
JP2
JP2
VU
5V
VU
PS/2 Port
Supply Voltage
3.3V
Table 6-5: PS/2 Port Supply Voltage Options
Some older keyboards and mice are 5V only. Consequently, the JP2 jumper should be set
for 5V operation as shown in Table 6-5. The Spartan-3 FPGA can tolerate 5V signals due to
the 270 series resistors on the PS/2 data and clock signals connected to the FPGA. See the
schematic in Figure A-7 for more details.

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UG130 (v1.1) May 13, 2005
Chapter 7
RS-232 Serial Port

The Spartan-3 Starter Kit board has an RS-232 serial port. The RS-232 transmit and receive
signals appear on the female DB9 connector, labeled J2, indicated as 6 in Figure 1-2. The
connector is a DCE-style port and connects to the DB9 DTE-style serial port connector
available on most personal computers and workstations. Use a standard straight-through
serial cable to connect the Spartan-3 Starter Kit board to the PCs serial port.
DB9
Connector
6
Pin 5
Pin 1
Pin 9
Pin 6
DB9 Serial Port Connector

(front view)
Maxim MAX3232
RS232 Voltage
Translator
Spartan-3 FPGA
TXD
DOUT1
DIN1
7
3
RIN1
ROUT1
R13
RXD
T13
8
4
9
5
TXD-A
DOUT2
DIN2
GND
T14
RXD-A
RIN2
ROUT2
Receiver
N10
LD7 LD6 LD5

FPGA pin number
Transmitter
J1 Header
Auxiliary Serial Port
UG130_c7_01_072104
Figure 7-1: RS-232 Serial Port

Figure 7-1 shows the connection between the FPGA and the DB9 connector, including the
Maxim MAX3232 RS-232 voltage converter, indicated as 7 in Figure 1-2. The FPGA
supplies serial output data as LVTLL or LVCMOS levels to the Maxim device, which in
turn, converts the logic value to the appropriate RS-232 voltage level. Likewise, the Maxim

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Chapter 7: RS-232 Serial Port
device converts the RS-232 serial input data to LVTLL levels for the FPGA. A series resistor
between the Maxim output pin and the FPGAs RXD pin protects against accidental logic
conflicts. A detailed schematic appears in Figure A-7.
Hardware flow control is not supported on the connector. The ports DCD, DTR, and DSR
signals connect together, as shown in Figure 7-1. Similarly, the ports RTS and CTS signals
connect together.
The FPGA connections to the Maxim RS-232 translator appear in Table 7-1.
Table 7-1: Accessory Port Connections to the Spartan-3 FPGA

Signal
FPGA Pin
RXD
T13
TXD
R13
RXD-A
N10
TXD-A
T14
An auxiliary RS-232 serial channel from the Maxim device is available on two 0.1-inch
stake pins, indicated as J1 in the schematic and 8 in Figure 1-2. The J1 stake pins are in
the lower left corner of the board, to the right of the DB9 serial connector, below the Maxim
RS-232 voltage translator, and to the left of the individual LEDs. The transmitter output
from the Maxim device drives the bottom stake pin while the receiver input connects to the
top stake pin.
The FPGA auxiliary RS-232 connections to the Maxim device appear in Table 7-1 with
signals RXD-A and TXD-A. Ignore the pin numbers listed on the silkscreen markings next
to the stake pins as these apply to the connections to the DB9 connector.
Place a jumper across the stake pins for an easy loop-back test. Alternately, create custom
serial ports by attaching the stake pins to other types of serial connectors such as male or
female DB9 or DB25 cable connectors or even create null modem connections.
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Chapter 8
Clock Sources
The Spartan-3 Starter Kit board has a dedicated 50 MHz Epson SG-8002JF series clock
oscillator source and an optional socket for another clock oscillator source. Figure A-5
provides a detailed schematic for the clock sources.
The 50 MHz clock oscillator is mounted on the bottom side of the board, indicated as 14
in Figure A-5. Use the 50 MHz clock frequency as is or derive other frequencies using the
FPGAs Digital Clock Managers (DCMs).
Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs

http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf
The oscillator socket, indicated as

footprint.
15
in Figure 1-2, accepts oscillators in an 8-pin DIP
Table 8-1: Clock Oscillator Sources

UG130 (v1.1) May 13, 2005
Oscillator Source
FPGA Pin
50 MHz (IC4)
T9
Socket (IC8)
D9
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Chapter 9: FPGA Configuration Modes and Functions
Chapter 9
FPGA Configuration Modes and

Functions
FPGA Configuration Mode Settings
In most applications for the Spartan-3 Starter Kit Board, the FPGA automatically boots
from the on-board Platform Flash memory whenever power is applied or the PROG push
button is pressed. However, the board supports all the available configuration modes via
the J8 header, indicated as 16 in Figure 1-2. Table 9-1 provides the available option
settings for the J8 header. Additionally, the JP1 jumper setting is required when using
Master Serial configuration mode, as further described in Platform Flash Jumper Options
(JP1).
The default jumper settings for the board are:
All jumpers in the J8 header are installed
The JP1 jumper is in the Default position
Table 9-1: Header J8 Controls the FPGA Configuration Mode
Master Serial
Header J8
Settings
Jumper JP1
Setting
GND J8
JP1
MODE
Configuration
Mode
<M0:M1:M2>
<0:0:0>
M0 M1 M2
GND J8
<1:1:1>
DEFAULT. The FPGA automatically boots from the Platform

Flash.
JP1
JP1
The FPGA attempts to boot from a serial configuration source

attached to either expansion connector A2 or B1.
JP1
Another device connected to either the A2 or B1 expansion

connector provides serial data and clock to load the FPGA.
JP1
The FPGA attempts to boot from a parallel configuration source

attached to the B1 expansion connector.
MODE
Slave Serial
or
Description
M0 M1 M2
GND J8
MODE
Master Parallel
<1:1:0>
M0 M1 M2
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Program Push Button/DONE Indicator LED
Table 9-1: Header J8 Controls the FPGA Configuration Mode (Continued)
Slave Parallel
Header J8
Settings
Jumper JP1
Setting
GND J8
JP1
Another device connected to the B1 expansion connector

provides parallel data and clock to load the FPGA.
JP1
The FPGA waits for configuration via the four-wire JTAG

interface.
MODE
Configuration
Mode
<M0:M1:M2>
<0:1:1>
Description
M0 M1 M2
GND J8
MODE
JTAG
<1:0:1>
M0 M1 M2
Program Push Button/DONE Indicator LED

The Spartan-3 Starter Kit Board includes two FPGA configuration functions, located near
the VGA connector and the AC power input connector, as shown in Figure 9-1. The PROG
push button, shown as 17 in Figure 9-1, drives the FPGAs PROG_B programming pin.
When pressed, the PROG push button forces the FPGA to reconfigure and reload it
configuration data.
VGA
The DONE LED, shown as 18 in Figure 9-1, connects to the FPGAs DONE pin and lights
up when the FPGA is successfully configured.
VGA
17
18
DONE
PROG
UG130_c9_03_042704
Figure 9-1: The PROG Button and the DONE LED

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Chapter 10
Platform Flash Configuration Storage

The Spartan-3 Starter Kit board has an XCF02S serial configuration Flash PROM to store
FPGA configuration data and potentially additional non-volatile data, including
MicroBlaze application code. To configure the FPGA from Platform Flash memory, all
three jumpers must be installed on the J8 header, indicated as 16 in Figure 1-2.
Platform Flash Jumper Options (JP1)

The Platform Flash has three optional settings controlled by the JP1 jumper, which is
located in the upper right-hand corner of the board, adjacent to the Platform Flash
configuration PROM. The JP1 jumper is indicated as 3 in Figure 1-2. A detailed
schematic is provided in Figure A-4. Table 10-1 summarizes the available options, which
are described in more detail below.
Table 10-1: Jumper JP1 Controls the Platform Flash Options

Option
Jumper JP1
Setting
Default
JP1
The FPGA boots from Platform Flash. No additional data storage is available.
Flash Read
JP1
The FPGA boots from Platform Flash, which is permanently enabled. The FPGA
can read additional data from Platform Flash.
Disable
JP1
Jumper removed. Platform Flash is disabled. Other configuration data source

provides FPGA boot data.
Description
Default Option
For most applications, this is the default jumper setting. As shown in Figure 10-1, the
Platform Flash is enabled only during configuration when the FPGAs DONE pin is Low.
When the DONE pin goes High at the end of configuration, the Platform Flash is disabled
and placed in low-power mode.

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Flash Read Option
Spartan-3 FPGA
Platform Flash
JP1
M0
DIN/D0
D0
M1
INIT_B
OE/RESET
M2
DONE
CE
CCLK
CLK
Default
MODE
J8
USER I/O
RCLK
UG130_c10_01_060704
Figure 10-1: Default Platform Flash Option
Flash Read Option

The Spartan-3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM. The
XC3S200 FPGA on the board only requires slightly less than 1Mbit for configuration data.
The remainder of the Platform Flash is available to store other non-volatile data, such as
revision codes, serial numbers, coefficients, an Ethernet MAC ID, or code for an embedded
processor, such as MicroBlaze, within the FPGA.
To allow the FPGA to read from Platform Flash after configuration, the JP1 jumper must be
properly positioned, as shown in Figure 10-2. When the jumper is in this position, the
Platform Flash is always enabled. After FPGA configuration completes, the FPGA
application drives the INIT_B pin High, FPGA pin N9. Consequently, the Platform Flash
data pointer is not reset and points to the additional data following the FPGA
configuration data. To read any subsequent data, the FPGA application generates
additional clock pulses on the RCLK signal from FPGA pin A14. After configuration, the
FPGAs CCLK output is three-stated with a pull-up resistor to VCCAUX (2.5V). The
Platform Flash presents serial data on the FPGAs DIN pin, pin M11.
Spartan-3 FPGA
Platform Flash
JP1
M0
(M11)
DIN/D0
(N9)
D0
M1
INIT_B
M2
DONE
CE
CCLK
CLK
Flash Read
OE/RESET
MODE
J8
(A14)
USER I/O
RCLK
UG130_c10_02_060404
Figure 10-2: Read Additional Data from Platform Flash by Setting the JP1 Jumper
The resistor between the CCLK output and FPGA pin A14 prevents any accidental
conflicts between the two signals.

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Chapter 10: Platform Flash Configuration Storage
Additional FPGA logic is required to read the Platform Flash data, as described in the
following application note.
XAPP694: Reading User Data from Configuration PROMs

http://www.xilinx.com/bvdocs/appnotes/xapp694.pdf
Disable Option
If the JP1 jumper is removed, then the Platform Flash is disabled, potentially allowing
configuration via an expansion board connected to one of the expansion connectors.
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UG130 (v1.1) May 13, 2005
Chapter 11
JTAG Programming/Debugging Ports

The Spartan-3 Starter Kit board includes a JTAG programming and debugging chain. Both
the Spartan-3 FPGA and the Platform Flash devices are part of the JTAG chain, as shown in
Figure 11-1. Additionally, there are two JTAG headers for driving the JTAG signals from
various supported JTAG download and debugging cables. A Digilent JTAG3 low-cost
parallel to JTAG cable is included as part of the kit and connects to the J7 header.
Digilent
JTAG3
Parallel
Cable IV
Parallel
Cable 3
Header
J7
MultiPro
Desktop
Tool
Header
J5
22
24
Spartan-3 FPGA
(XC3S400FT256C)
10
TDI
TMS
TCK
TDO
PlatformFlash
(XCF02S)
TDI
TDO
TMS
TCK
x Header pin number
UG130_c11_01_042504
Figure 11-1: Spartan-3 Starter Kit Board JTAG Chain
JTAG Header (J7)

This J7 JTAG header consists of 0.1-inch stake pins and is indicated as 22 in Figure 1-2,
located toward the top edge of the board, directly below the two expansion connectors.
The Digilent low-cost parallel port to JTAG cable fits directly over the J7 header stake pins,
as shown in Figure 11-2. When properly fitted, the cable is perpendicular to the board.
Make sure that the signals at the end of the JTAG cable align with the labels listed on the
board. The other end of the Digilent cable connects to the PCs parallel port. The Digilent
cable is directly compatible with the Xilinx iMPACT software. The schematic for the
Digilent cable appears in Figure A-9.

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TMS
TDI
TDO
2.8V
TCK
GND
UP TO 5V
VCC
23
21
J7
TMS
TDI
TDO
TCK
GND
VDD
20
22
UG130_c11_02_042704
Figure 11-2: Digilent JTAG Cable Provided with Kit Connects to the J7 Header
The J7 header also supports the Xilinx Parallel Cable 3 (PC3) download/debugging cable
when using the flying leaders. Again, make sure that the signals at the end of the JTAG
cable align with the labels listed on the board.
Figure A-4 provides a detailed schematic of the J7 header and the JTAG programming
chain.
Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5)

The J5 header, shown as
cables listed below:
24
in Figure 1-2, supports the Xilinx download/debugging
MultiPro Desktop Tool

http://www.xilinx.com/bvdocs/publications/ds114.pdf
Parallel Cable IV (PC IV)

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/cables6.html
Use the 14-pin ribbon cable supplied with both cables to connect to the J5 header. DO NOT
use the flying leads that are also provided with some cables. Although the MultiPro
Desktop Tool and the Parallel Cable IV support multiple FPGA configuration modes, the
Spartan-3 Starter Kit board only supports the JTAG configuration method. The header is
designed for a keyed socket. However, the Spartan-3 Starter Kit uses only stake pins. The
outline of the keyed connector appears around the J5 header, as shown in Figure 11-3.
When properly inserted, the keyed header matches the outline on the board and the ribbon
cable crosses over the top edge of the board. The red-colored lead indicates pin 1 on the
cable and should be on the left side.
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UG130 (v1.1) May 13, 2005
Parallel Cable IV/MultiPro Desktop Tool JTAG Header (J5)
Red trace
indicates pin 1
21
20
24
J5
Parallel Cable IV
JTAG
Notch on outline
matches key on header
UG130_c11_03_042704
Figure 11-3: Use 14-Pin Ribbon Cable to Connect Parallel Cable IV or the MultiPro
Desktop Tool to the J5 Header

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UG130 (v1.1) May 13, 2005
Chapter 12
Power Distribution
AC Wall Adapter
The Spartan-3 Starter Kit includes an international-ready AC wall adapter that produces a
+5V DC output. Connect the AC wall adapter to the barrel connector along the left edge of
the board, indicated as 25 in Figure 1-2. There is no power switch to the board. To
disconnect power, remove the AC adapter from the wall or disconnect the barrel connector.
The POWER indicator LED, shown as 26 in Figure 1-2, lights up when power is properly
applied to the board. If the jumpers in the J8 header and JP1 header are properly set and
there is a valid configuration data file in the Platform Flash memory, then the DONE
indicator LED, shown as 18 in Figure 1-2, also lights up.
The AC wall adapter is directly compatible for North America, Japan, and Taiwan locales.
Other locations might require a socket adapter to convert from the North American
standard to the local power socket standard. The AC wall adapter operates from 100V to
240V AC input, at 50 or 60 Hz.
Voltage Regulators
There are multiple voltages supplied on the Spartan-3 Starter Kit Board, as summarized in
Table 12-1.
Table 12-1: Voltage Supplies and Sources

Voltage
+5V DC
Source
Supplies
AC Wall Adapter, 5V switching power supply

( 25 in Figure 1-2)
3.3V regulator
Optionally, PS/2 port via jumper JP2 setting
Pin 1 (VU) on A1, A2, B1 expansion connectors
+3.3V DC
National Semiconductor LM1086CS-ADJ 3.3V

regulator ( 27 in Figure 1-2)
2.5V and 1.2V regulators

VCCO supply input for all FPGA I/O banks
Most components on the board
Pin 3 on A1, A2, B1 expansion connectors
+2.5V DC
STMicroelectronics LF25CDT 2.5V regulator

( 28 in Figure 1-2)
VCCAUX supply input to FPGA
+1.2V DC
Fairchild Semiconductor FAN1112 1.2V

regulator ( 29 in Figure 1-2)
VCCINT supply input to FPGA
Overall, the 5V DC switching power adapter that connects to AC wall power powers the
board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the

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Chapter 12: Power Distribution
2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply
inputs to the FPGAs I/O banks and powers most of the components on the board.
The 2.5V regulator supplies power to the FPGAs VCCAUX supply inputs. The VCCAUX
voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and
supplies some of the I/O structures. In specific, all of the FPGAs dedicated configuration
pins, such as DONE, PROG_B, CCLK, and the FPGAs JTAG pins, are powered by VCCAUX.
The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V
supply has a current shunt resistor to prevent reverse current.
Finally, a 1.2V regulator supplies power to the FPGAs VCCINT voltage inputs, which
power the FPGAs core logic.
The board uses three discrete regulators to generate the necessary voltages. However,
various power supply vendors are developing integrated solutions specifically for
Spartan-3 FPGAs.
Figure A-3 provides a detailed schematic of the various voltage regulators. Similarly,
Figure A-6 shows the power decoupling capacitors.
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UG130 (v1.1) May 13, 2005
Chapter 13
Expansion Connectors and Boards

Expansion Connectors
The Spartan-3 Starter Kit board has three 40-pin expansion connectors labeled A1, A2, and
B1. The A1 and A2 connectors, indicated as 21 and 20 , respectively, in Figure 1-2, are on
the top edge of the board. Connector A1 is on the top left, and A2 is on the top right. The B1
connector, indicated as 19 in Figure 1-2, is along the right edge of the board.
21
20
B1 Expansion Connector
19
UG130_c12_01_042704
Figure 13-1: Spartan-3 Starter Kit Board Expansion Connectors

Table 13-1 summarizes the capabilities of each expansion port. Port A1 supports a
maximum of 32 user I/O pins, while the other ports provide up to 34 user I/O pins. Some
pins are shared with other functions on the board, which may reduce the effective I/O
count for specific applications. For example, pins on the A1 port are shared with the SRAM
address signals, with the SRAM OE# and WE# control signals, and with the eight leastsignificant data signals to SRAM IC10 only.

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Table 13-1: Expansion Connector Features

Connector
User I/O
SRAM
JTAG
Serial Configuration
A1
32
Address
OE#, WE#
Data[7:0] to IC10 only
A2
34
B1
34
Parallel Configuration
Each port offers some ability to program the FPGA on the Spartan-3 Starter Kit Board. For
example, port A1 provides additional logic to drive the FPGA and Platform Flash JTAG
chain. Similarly, ports A2 and B1 provide connections for Master or Slave Serial mode
configuration. Finally, port B1 also offers Master or Slave Parallel configuration mode.
Each 40-pin expansion header, shown in Figure 13-2, uses 0.1-inch (100 mil) DIP spacing.
Pin 1 on each connector is always GND. Similarly, pin 2 is always the +5V DC output from
the switching power supply. Pin 3 is always the output from the +3.3V DC regulator.
Pin 3: +3.3V
Pin 39
Pin 1: GND
Pin 39
Pin 40
Pin 4
Pin 2: VU
+5V
Pin 40
UG130_c12_02_042504
Figure 13-2: 40-pin Expansion Connector

The pinout information for each connector appears below. The tables include the
connections between the FPGA and the expansion connectors plus the signal names used
in the detailed schematic in Figure A-1.
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UG130 (v1.1) May 13, 2005
A1 Connector Pinout
The A1 expansion connector is located along the top edge of the board, on the left, as
indicated by 21 in Figure 1-2. Table 13-2 provides the pinout for the A1 connector. The
FPGA connections are specified in parentheses.
Table 13-2: Pinout for A1 Expansion Connector

Schematic Name
FPGA Pin
GND
Connector
1
FPGA Pin
Schematic Name
VU (+5V)
VCCO (+3.3V)
VCCO (all banks)
(N8)
ADR0
DB0
(N7)
SRAM IC10 IO0
(L5)
SRAM A0
ADR1
DB1
(T8)
SRAM IC10 IO1
(N3)
SRAM A1
ADR2
DB2
(R6)
SRAM IC10 IO2
10
(M4)
SRAM A2
ADR3
DB3
(T5)
SRAM IC10 IO3
11
12
(M3)
SRAM A3
ADR4
DB4
(R5)
SRAM IC10 IO4
13
14
(L4)
SRAM A4
ADR5
DB5
(C2)
SRAM IC10 IO5
15
16
(G3)
SRAM WE#
WE
DB6
(C1)
SRAM IC10 IO6
17
18
(K4)
SRAM OE#
OE
DB7
(B1)
SRAM IC10 IO7
19
20
(P9)
FPGA DOUT/BUSY
CSA
LSBCLK
(M7)
21
22
(M10)
MA1-DB0
MA1-DB1
(F3)
SRAM A6
23
24
(G4)
SRAM A5
MA1-DB2
MA1-DB3
(E3)
SRAM A8
25
26
(F4)
SRAM A7
MA1-DB4
MA1-DB5
(G5)
SRAM A10
27
28
(E4)
SRAM A9
MA1-DB6
MA1-DB7
(H4)
SRAM A12
29
30
(H3)
SRAM A11
MA1-ASTB
MA1-DSTB
(J3)
SRAM A14
31
32
(J4)
SRAM A13
MA1-WRITE
MA1-WAIT
(K5)
SRAM A16
33
34
(K3)
SRAM A15
MA1-RESET
MA1-INT
(L3)
SRAM A17
35
36
JTAG Isolation
JTAG Isolation
TMS
(C13)
FPGA JTAG TMS
37
38
(C14)
FPGA JTAG TCK
TCK
TDO-ROM
Platform Flash
JTAG TDO
39
40
Header J7, pin 3
TDO-A

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The A1 expansion connector shares connections with the 256Kx16 SRAM devices,
specifically the SRAM address lines, the OE# and WE# control signals, and the eight leastsignificant data lines to SRAM IC10 only. Similarly, the JTAG chain is available on pins 36
through 40. Pin 20 is the FPGA DOUT/BUSY configuration signal and toggles during the
FPGA configuration process.
A2 Connector Pinout
The A2 expansion connector is located along the top edge of the board, on the right, as
indicated by 20 in Figure 1-2. Figure 13-3 provides the pinout for the A2 connector. The
FPGA connections are specified in parentheses.
Most of the A2 expansion connector pins connect only with the FPGA and are not shared.
Pin 35 connects to the auxiliary clock socket, if an oscillator is installed in the socket. Pins
36 through 40 include the signals required to configure the FPGA in Master or Slave Serial
mode.
Table 13-3: Pinout for A2 Expansion Connector

Schematic Name
FPGA Pin
GND
50
Connector
1
FPGA Pin
Schematic Name
VU (+5V)
VCCO (+3.3V)
VCCO (all banks)
(E6)
PA-IO1
PA-IO2
(D5)
(C5)
PA-IO3
PA-IO4
(D6)
(C6)
PA-IO5
PA-IO6
(E7)
10
(C7)
PA-IO7
PA-IO8
(D7)
11
12
(C8)
PA-IO9
PA-IO10
(D8)
13
14
(C9)
PA-IO11
PA-IO12
(D10)
15
16
(A3)
PA-IO13
PA-IO14
(B4)
17
18
(A4)
PA-IO15
PA-IO16
(B5)
19
20
(A5)
PA-IO17
PA-IO18
(B6)
21
22
(B7)
MA2-DB0
MA2-DB1
(A7)
23
24
(B8)
MA2-DB2
MA2-DB3
(A8)
25
26
(A9)
MA2-DB4
MA2-DB5
(B10)
27
28
(A10)
MA2-DB6
MA2-DB7
(B11)
29
30
(B12)
MA2-ASTB
MA2-DSTB
(A12)
31
32
(B13)
MA2-WRITE
MA2-WAIT
(A13)
33
34
(B14)
MA2-RESET
MA2-INT/GCK4
(D9)
Oscillator socket
35
36
(B3)
FPGA PROG_B
PROG-B
DONE
(R14)
FPGA DONE
37
38
(N9)
FPGA INIT_B
INIT
CCLK
(T15)
FPGA CCLK
Connects to (A14) via
390 resistor
(M11)
DIN
39
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UG130 (v1.1) May 13, 2005
B1 Connector Pinout
The B1 expansion connector is located on the right edge of the board, as indicated by 19 in
Figure 1-2. Table 13-4 provides the pinout for the B1 connector. The FPGA connections are
specified in parentheses.
Most of the B1 expansion connector pins connect only with the FPGA and are not shared.
Pins 36 through 40 include the signals required to configure the FPGA in Master or Slave
Serial mode. These same pins plus pins 5, 7, 9, 11, 13, 15, 17, 19, and 20 provide the signals
required to configure the FPGA in Master or Slave Parallel mode.
Table 13-4: Pinout for B1 Expansion Connector

Schematic Name
FPGA Pin
Connector
GND
VCCO (+3.3V)
VCCO (all banks)
PB-DB0
(T3)
FPGA RD_WR_B config
PB-DB1
(N11)
FPGA D1 config
PB-DB2
(P10)
FPGA D2 config
10
PB-DB3
(R10)
FPGA D3 config
11
12
PB-DB4
(T7)
FPGA D4 config
13
14
PB-DB5
(R7)
FPGA D5 config
15
16
PB-DB6
(N6)
FPGA D6 config
17
18
PB-DB7
(M6)
FPGA D7 config
19
PB-CLK
(C15)
MB1-DB1
FPGA Pin
Schematic Name
VU (+5V)
(C10)
PB-ADR0
(E10)
PB-ADR1
(C11)
PB-ADR2
(D11)
PB-ADR3
(C12)
PB-ADR4
(D12)
PB-ADR5
(E11)
PB-WE
(B16)
PB-OE
20
(R3)
FPGA CS_B config
PB-CS
21
22
(C16)
MB1-DB0
(D15)
23
24
(D16)
MB1-DB2
MB1-DB3
(E15)
25
26
(E16)
MB1-DB4
MB1-DB5
(F15)
27
28
(G15)
MB1-DB6
MB1-DB7
(G16)
29
30
(H15)
MB1-ASTB
MB1-DSTB
(H16)
31
32
(J16)
MB1-WRITE
MB1-WAIT
(K16)
33
34
(K15)
MB1-RESET
MB1-INT
(L15)
35
36
(B3)
FPGA PROG_B
PROG-B
DONE
(R14)
FPGA DONE
37
38
(N9)
FPGA INIT_B
INIT
CCLK
(T15)
FPGA CCLK
Connects to (A14) via
390 resistor
(M11)
DIN

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Expansion Boards
Various expansion boards plug into the A1, A2, or B1 connectors as listed below:
52
Spartan-3 Starter Kit Expansion Boards

http://www.xilinx.com/s3boards
Digilent Expansion Boards

https://digilent.us/Sales/boards.cfm#Peripheral
Digilent Breakout Probe Header (TPH1)

https://digilent.us/Sales/Product.cfm?Prod=TPH1
Digilent Breadboard (DBB1)

https://digilent.us/Sales/Product.cfm?Prod=DBB1
Digilent Wire-wrap Board (DWR1)

https://digilent.us/Sales/Product.cfm?Prod=DWR1
Digilent SPP, EPP, ECP Parallel Port (PIO1)

https://digilent.us/Sales/Product.cfm?Prod=PIO1
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UG130 (v1.1) May 13, 2005
Appendix A
Board Schematics
This appendix provides the schematics for the Spartan-3 Starter Kit Board:
Figure A-1, A1, A2, and B1 Expansion Connectors
Figure A-2, Slide Switches, Push Buttons, LEDs, and Four-Character 7-Segment
Display
Figure A-3, Voltage Regulators, JP2 Jumper Setting for PS/2 Port Voltage
Figure A-4, FPGA Configuration Interface, Platform Flash, JTAG Connections,

Jumper JP1
Figure A-5, FPGA I/O Connections, Clock Sources
Figure A-6, Power Decoupling Capacitors
Figure A-7, RS-232 Serial Port, VGA Port, PS/2 Port, Parallel Cable IV JTAG
Interface
Figure A-8, 2x256Kx16 Fast Asynchronous SRAM Interface
Figure A-9, Digilent JTAG3 Low-Cost JTAG Download/Debug Cable

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UG130_ApA_01_051305

UG130 (v1.1) May 13, 2005
Figure A-1: A1, A2, and B1 Expansion Connectors
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NOTE:
SRAM address lines and OE#, WE# controls have shared connections with A1 connector.
Likewise, lower eight data bits to SRAM IC10 are also shared with A1 connector.
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UG130_ApA_02_051305
Figure A-2: Slide Switches, Push Buttons, LEDs, and Four-Character 7-Segment Display

UG130 (v1.1) May 13, 2005
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56
UG130_ApA_03_042704

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Figure A-3: Voltage Regulators, JP2 Jumper Setting for PS/2 Port Voltage
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Figure A-4: FPGA Configuration Interface, Platform Flash, JTAG Connections, Jumper JP1

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UG130_ApA_05_051305

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Figure A-5: FPGA I/O Connections, Clock Sources
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Figure A-6: Power Decoupling Capacitors

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Figure A-7: RS-232 Serial Port, VGA Port, PS/2 Port, Parallel Cable IV JTAG Interface
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1-800-255-7778
Figure A-8:

UG130 (v1.1) May 13, 2005
2x256Kx16 Fast Asynchronous SRAM Interface
www.xilinx.com
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NOTE:
SRAM address lines and OE#, WE# controls have shared connections with A1 connector.
Likewise, lower eight data bits to SRAM IC10 are also shared with A1 connector.
UG130_ApA_08_051305
R
61
62
UG130_ApA_09_042604

UG130 (v1.1) May 13, 2005
Figure A-9: Digilent JTAG3 Low-Cost JTAG Download/Debug Cable
www.xilinx.com
1-800-255-7778
Appendix B
Reference Material for Major

Components
Table B-1 lists the major components on the Spartan-3 Starter Kit Board, including full part
numbers and links to complete device data sheets.
Table B-1: Major Components and Data Sheet Links

Device
1
Vendor
Part Number
Xilinx, Inc.
XC3S200-4FT256C
Spartan-3 FPGA
Xilinx, Inc.
XCF02SVO20C
Platform Flash Configuration Flash PROM

Integrated Silicon
Solutions, Inc. (ISSI)
IS61LV25616AL-10T
256Kx16 Fast Asynchronous SRAM

http://www.issi.com/pdf/61LV25616AL.pdf
Maxim, Intersil
MAX3232, ICL3232
Dual-Channel RS-232 Voltage Translator

http://pdfserv.maxim-ic.com/en/ds/MAX3222-MAX3241.pdf
http://www.intersil.com/data/fn/fn4805.pdf
Epson
SG-8002JF
50 MHz Crystal Oscillator

http://www.knap.at/de/pdf/kat_o/sg8002jf.pdf
Interex
APA-101M-05
5V Switching Regulator
National
Semiconductor
LM1086CS-ADJ
3.3V Regulator
http://www.national.com/pf/LM/LM1086.html#Datasheet
STMicroelectronics
LF25CDT
2.5V Regulator
http://www.st.com/stonline/books/pdf/docs/2574.pdf
Fairchild
Semiconductor
FAN1112
1.2V Regulator
http://www.fairchildsemi.com/ds/FA/FAN1112.pdf
(IC1)
2
(IC9)
4
(IC10, IC11)
7
(IC14)
14
(IC4)
25
27
(IC5)
28
(IC3)
29
(IC12)
Description/Data Sheet Link

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63
www.xilinx.com/s3boards
PN 0402292
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UG130 (v1.1) May 13, 2005
Application Note: Spartan-II, Spartan-3, Virtex, and Virtex-II FPGA Families

R
XAPP694 (v1.0) May 26, 2004
Reading User Data from Configuration

PROMs
Author: Stephan Neuhold
Summary
This application note describes how to retrieve user-defined data from Xilinx configuration
PROMs (XC18V00 and Platform Flash devices) after the same PROM has configured the
FPGA. The method to add user-defined data to the configuration PROM file is also discussed.
The reference design described in this application note may be used in any of the following
Xilinx FPGA architectures: Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II,
and Virtex-II Pro.
Introduction
After an FPGA has been configured, it is often necessary to retrieve user-defined data that is
used by the FPGA during operation. The user-defined data needs to be retrieved from an
external storage device and a control circuit is required to interface to the storage device. This
implies additional time for logic design and board level engineering, not to mention extra board
real estate requirements and a higher FPGA pin count.
Xilinx configuration PROMs are generally used to store an FPGA design, which is downloaded
to the FPGA upon system power-up. In most cases, this is the PROMs only function, and its
capacity is usually not fully used by the FPGA design. This leaves the unused portion of the
PROM as wasted space.
The design in this application note describes how user-defined data can be stored and
retrieved from Xilinx configuration PROMs using existing connections and only one user I/O.
This reduces the FPGA pin count, component count, board space, and overall system cost.
The user-defined data can be an Ethernet MAC ID, bitstream revision code, coefficients,
processor code, ASCII data to be displayed, encryption codes, and so on. A Perl script has
been created that automatically modifies existing configuration PROM files with user-defined
data. The script supports Intel Object (.mcs) and HEX (.hex) file formats, with optional bit
swapping.
Considerations
for PROM
and FPGA
Connections
Figure 1 clearly shows the minimum connections necessary to create a suitable interface
between the PROM and the FPGA. The interface allows the FPGA to retrieve data from the
PROM before and after it has been configured. This is the simplest implementation for reading
user-defined data from a configuration PROM. However, other implementations do exist and
are discussed later in this application note. For an in-depth description of the logic
implementation for Figure 1, see Macro Implementation, page 4.
The connections in Figure 1 are required for the following reasons:
In any master configuration mode, the configuration clock CCLK generated by the FPGA
will stop toggling after the FPGA has been successfully configured, preventing the
PROMs address counter from advancing beyond the FPGA design stored in the PROM.
When the CE pin on the PROM goes High, the PROMs address counter is held reset at
zero. If the CE pin of the PROM is held High, the address counter of the PROM cannot be
advanced. In this state, any data retrieved from the PROM will be the actual FPGA design
and not user-defined data. This is explained in Table 1.
2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
XAPP694 (v1.0) May 26, 2004
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Considerations for PROM and FPGA Connections
When the INIT pin goes Low, indicating either that a CRC error occurred during
configuration or that INIT has become user I/O initialized to a Low state after configuration,
the address counter of the PROM will be held reset to zero. If the OE/RESET pin of the
PROM is held Low, the address counter of the PROM cannot be advanced. In this state,
any data retrieved from the PROM will be the actual FPGA design and not user-defined
data.
VCC
CLK
OE/RESET
CCLK
INIT / USERIO
M0
CE
CF
DIN/D0
XILINX
CONFIGURATION
PROM
TCK
TCK
TMS
TMS
TDI
TDI
PROG
M1
DIN/D0
M2
XILINX FPGA
USERIO
TCK
TMS
TDO
TDI
TDO
TDO
x694_01_033104
Figure 1: PROM and FPGA Connections with Additional Control Signal

Table 1: Truth Table for PROM Control Inputs
Control Inputs
OE/RESET
CE
High
Low
Internal Address(1)
Outputs
DATA
If address TC: increment
Active
If address > TC: do not change
High-Z
Low
Low
Held reset
High-Z
High
High
Held reset
High-Z
Low
High
Held reset
High-Z
Notes:
1.
TC = Terminal Count of address counter. Address = address count.
The above considerations have several solutions:
The CE pin can be connected to ground via a pull-down resistor. This will always enable
the PROM. An alternative is to connect the CE pin to a user I/O pin on the FPGA. This
allows the user to enable or disable the PROM and reduce power consumption.
The OE/RESET pin should be connected to INIT, since this allows the FPGA to reinitiate a
configuration if a CRC error occurs during configuration. The INIT pin becomes user I/O
after configuration and so can be configured to output a logic High to keep the PROM
outputs enabled.
With the OE/RESET pin held High and the CE pin held Low, the PROMs address counter
is able to advance beyond the FPGA configuration data.
In master configuration modes the clock signal to the PROM can be generated by one of
the user I/O and connected in parallel with the CCLK pin. This is a necessity, since the
clock needs to be controlled by the FPGA.
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XAPP694 (v1.0) May 26, 2004
Considerations for PROM and FPGA Connections
The configuration clock CCLK stops toggling after the STARTUP phase of the FPGA has
completed provided the -persist option in BitGen is set to off (default). After CCLK stops
toggling, the pin is 3-stated with a weak pull-up resistor connected to VCCO. However,
depending on configuration options set during bitstream generation the number of CCLK cycles
after the STARTUP phase is uncertain. This makes it difficult to know exactly at what address
the PROMs address counter has stopped, which means that user-defined data stored directly
after the FPGA configuration may not be retrieved reliably. Figure 2 shows this concept
graphically.
This problem can be overcome by employing a mechanism similar to the configuration logic
inside the FPGA. After power-up, the FPGA starts receiving data from the PROM. The FPGA,
however, does not load any data received from the PROM until it has received a
synchronization word. For Xilinx FPGAs based on the Virtex architecture, the synchronization
word is AA995566h. This same idea can be used in the FPGA after configuration to look for
user-defined data.
Note: For more information regarding FPGA configuration, see XAPP501, "Configuration
Quickstart Guidelines," and XAPP138, "Virtex FPGA Series Configuration and Readback." For
information regarding configuration of Virtex-II and Virtex-II Pro devices, see the "Configuration"
chapters of the Virtex-II Platform FPGA User Guide and Virtex-II Pro Platform FPGA User Guide.
After the FPGA has been configured, it sends out clock pulses on the user I/O connected to the
CLK pin of the PROM. With every rising edge of the clock, the PROM's address counter is
incremented by one, and the data at that address is presented on the data pins of the PROM.
XXXXh
User Data Block 1
Sync Pattern
User Data Block 0
Sync Pattern
PROM counter
after configuration
Area of Uncertainty
FPGA
Configuration
PROM counter at start

of configuration = 0000h
x694_02_033104
Figure 2: PROM Memory Map Showing Address Counter Uncertainty

A Perl script exists that adds synchronization patterns and user-defined data to configuration
PROM files. For a detailed description on how to use the script, see Adding User Data to the
PROM, page 7. For now, an example of how to use the script is given. All files used in the
example, including the script, can be found in the \Perl_Script directory of the reference
design archive. See Design Resources, page 11.
The PROM file containing the FPGA configuration is named prom_file.mcs and the file
containing the synchronization patterns and user-defined data is named user_data.txt.
The command line that invokes the script to add the contents of user_data.txt to
prom_file.mcs is:
Xilperl pc.pl -f mcs -swap off -uf user_data.txt -pf prom_file.mcs
XAPP694 (v1.0) May 26, 2004
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Macro Implementation
The script produces a PROM file named new_prom_file.mcs. All files can be examined in
a text editor. The user_data.txt file has four separate blocks of user-defined data, each
defined by a separate synchronization pattern. The synchronization pattern in this example is
8F9FAFBFh and the user-defined data that follows is ASCII encoded data. When converted,
the ASCII code represents:
XAPP 694 DATA BLOCK x
where x represents the current data block.
Other choices of synchronization patterns and user-defined data can be implemented. For a
more detailed description, see Adding User Data to the PROM, page 7, and Other
Implementations, page 10.
Macro
Implementation
din/d0
Shift Register
and
Comparator
data
dout[7:0]
sync_found
data_ready
sync
reset_prom
Control
State
Machine
clock
reset
read
next_sync
din_read_enable
cclk_on
Clock
Management
cclk
x694_03_033104
Figure 3: PROM Reader Macro

Figure 3 shows the macro used to read user-defined data from the PROM after the FPGA has
been configured. A description of the input and output signals and their function can be found
in Table 2.
Table 2: PROM Reader Macro Signal Descriptions and Functions
Signal
I/O
Direction
Description
clock
Input
All signals are registered on the rising of this signal.
reset
Input
This signal resets all logic to the initial state. This signal is
asynchronous and active Low.
din/d0
Input
Data from the PROM is presented on this signal.
read
Input
This signal is used to instruct the macro to retrieve the next

8 bits of data from the PROM. This signal is active Low.
next_sync
Input
This signal is used to instruct the macro to search and find the
next synchronization pattern in the PROM. This signal is
active Low.
dout[7:0]
Output
This is the data bus on which actual user-defined data is

presented. Valid user-defined data is indicated by the
data_ready signal going Low for one clock cycle.
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XAPP694 (v1.0) May 26, 2004
Table 2: PROM Reader Macro Signal Descriptions and Functions (Continued)
I/O
Direction
Description
data_ready
Output
This signal indicates that valid data is present on the dout[7:0]

pins. This signal is active Low.
sync
Output
This signal indicates that a synchronization pattern has been

detected in the data retrieved from the PROM. The signal is
active Low.
reset_prom
Output
This signal outputs a Low whenever the macro is reset. This

signal can be connected to either the CE or OE/RESET pin of
the PROM to reset the PROMs addess counter.
cclk
Output
This signal mimics the CCLK signal from the FPGA during
configuration.
Signal
A description of each block of the macro and the functionality that it provides follows.
Clock Management
This block generates clock enables at appropriate clock edges so that data from the PROM is
captured correctly by the FPGA. It also generates a signal that mimics the CCLK signal
provided during configuration.
With every rising edge of CCLK, new data is presented at the data pins of the PROM. On the
falling edge of CCLK, a clock enable signal allows the data to be captured by the Shift Register
and Comparator block on the rising edge of the system clock. This ensures that an adequate
setup and hold time exists for the input registers of the FPGA.
The CCLK signal is generated by enabling a register that provides a signal equivalent to the
system clock divided down to 10 Mhz. The enable signal to the register is provided by a rotating
logic High through an SRL16. The length of the SRL16 is determined by the system clock
frequency, which the user enters via a parameter. Using this method to "divide" the system
clock is advantageous, since it does not require the use of DLLs or DCMs and still keeps the
circuit synchronous.
Figure 4 shows the timing relationship between the data and CCLK.
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
clock
cclk_on
cclk
din_read_enable
TCAC
din
DATA0
DATA1
DATA
DATA6
TCAC = CCLK-to-data delay of PROM
DATA7
DATA8
x694_04_033104
Figure 4: Clock Management Block Timing
Shift Register and Comparator

This block captures data from the PROM one bit at a time. Whenever a data bit is clocked into
the FPGA, the data is compared to a synchronization pattern to determine the start position of
XAPP694 (v1.0) May 26, 2004
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user-defined data. The length of the synchronization pattern, as well as the pattern itself, can
be user-defined. The pattern can also be changed during the operation of the FPGA. This
allows the user to define and search for multiple sets of user-defined data, a capability that
makes this circuit very flexible.
Upon finding the synchronization pattern, a sync pulse is generated to indicate that
synchronization has been achieved. The sync pulse is valid for as long as the synchronization
pattern remains valid.
Figure 5 shows the timing relationship of the sync signal and the data.
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
clock
din
SYNC n-4
SYNC n-3
SYNC n-2
SYNC n-1
SYNC n
DATA0
DATA1
DATA3
DATA4
sync_found
x694_05_041204
Figure 5: Shift Register and Comparator Block Timing

The Shift Register and Comparator block continues to check for a synchronization pattern,
even when synchronization has already been achieved. If synchronization has been achieved
and the user-defined data also happens to match the synchronization pattern, a sync pulse will
still be generated. Therefore, only the data_ready signal qualifies actual user-defined data. The
data_ready pulse is described in the Control State Machine section.
Control State Machine

This block provides control for all other modules in the macro. It determines how many data bits
to retrieve from the PROM after synchronization, when to search for the next synchronization
pattern, when to retrieve the next byte of user-defined data, and when to reset the PROMs
address counter. Figure 6 shows the different states implemented in the state machine.
Reset
State: PresentData
This state presents retrieved
user-defined data on the dout
output of the macro.
S4
S1
State: Look4Sync
In this state, the design looks
for a synchronization pattern.
S3
State: GetData
In this state, the design retrieves
user-defined data from the PROM.
S2
State: Wait4Active
In this state, the design waits
for user input. User input can be
to retrieve data or look for the
next synchronization pattern.
x694_06_033104
Figure 6: Control State Machine Diagram
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XAPP694 (v1.0) May 26, 2004
Adding User Data to the PROM
Figure 7 shows the timing relationship of the data_ready pulse, together with data on din/dout
and the sync pulse.
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
clock
din
SYNC n-2
SYNC n-1
SYNC n
DATA0
DATA1
DATA6
DATA7
DATA8
sync
dout
DATA[7:0]
DATA[7:0]
data_ready
x694_07_033104
Figure 7: Control State Machine Block Timing
Adding User
Data to the
PROM
In order to read user-defined data from the configuration PROM, a method must exist that
allows the designer to easily add user-defined data to the PROM file. A Perl script that will add
user-defined data to existing PROM files for Intel Object and Hex file formats can be found in
the \Perl_Script directory of the reference design for this application note. The Perl script
does not support Motorola EXORmacs and TEKTRONIX TEK formats. In order to provide an
explanation of what the script does and how it works, some details concerning PROM file
formats are discussed in the next three sections:
Bit swapping
Records, byte counts and checksums
PROM size
Bit Swapping
Every byte of data retrieved from the configuration PROM is presented in a bit-swapped
fashion: that is, the MSb of every byte is read first, and the LSb is read last. It is important to
bear this in mind, as it has an effect on how data is presented and used inside the FPGA. An
example of bit swapping is shown in Figure 8, which illustrates that the way data is presented in
the PROM file differs from the way it is presented inside the FPGA. (The values chosen in the
example are arbitrary.)
PROM Data (hex)
08 67 F3 5A ...
Binary 0000 1000
0110 0111
1111 0011
0101 1010
0001 0000
1110 0110
1100 1111
0101 1010
10
E6
BF
Bit-swapped
This is how the data
reads in the FPGA
Hex
5A
x694_08_033104
Figure 8: bit Swapping of PROM Data
XAPP694 (v1.0) May 26, 2004
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Adding User Data to the PROM

Although other PROM file formats exists, the Perl script discussed in this application note
supports only the Intel Object and Hex file formats, so only these formats are discussed here.
Bit swapping is a feature of the Intel Object (.mcs) and Hex PROM file formats. The Xilinx
iMPACT configuration tool supports both formats. The Hex file format can have bit swapping
enabled or disabled. The bit swapping is important to note when adding user-defined data to
the configuration PROM file, since it influences the way that data is read by the FPGA,
particularly the synchronization pattern. The bit swapping can be dealt with in two ways:
1. The user-defined data can be added to the configuration PROM file without any bit
swapping. The data can then be bit-swapped inside the FPGA, if necessary, after it is read.
2. The user-defined data can be added to the configuration PROM file with every byte having
been bit-swapped already. There is no need to bit-swap the data inside the FPGA after it is
read.
Either of the above mentioned methods is suitable, and although the first option mentions
swapping the bits inside the FPGA, this option does not add logic resources to realize the
interface. The reference design in this application note implements the first option.
As already mentioned, the Hex file format can have bit swapping enabled or disabled. When
using the Perl script, the user can specify whether the user-defined data is to be added in a
bit-swapped fashion or not by using the -swap option. If the -swap option is on, then all bytes
of the user-defined data are bit-swapped before they are added to the existing Hex file. If the
-swap option is off, then the user-defined data is simply appended to the existing Hex file.
When using Intel Object format PROM files, the -swap option must be specified, although the
option has no effect.
Records, Byte Counts and Checksums

When adding user-defined data to an existing configuration PROM file, there are a number of
data fields that need to be added in order for the file to be successfully downloaded into a
PROM. Since the Perl script only supports the Intel Object and Hex file formats, only these are
discussed here. The Hex file formats do not require any additional data fields to be added.
However, the Intel Object file format requires a Start Character, Byte Count, Address, Record
Type, and Checksum fields, in addition to the actual data. The Perl script automatically
calculates these fields and inserts them into the existing PROM file. In order for the script to
calculate these values correctly, the user-defined data must be presented 16 bytes per line.
Table 3 through Table 5 show the record types used by the iMPACT configuration software.
00 =
01 =
04 =
Data Record
End of File Record (signals the end of the file)
Extended Linear Address Record (provides the offset to determine the absolute
destination address)
The checksum is the two's complement of the binary summation of the preceding bytes in the
record (including the byte count, address, and any data bytes), in hexadecimal notation.
The extended linear address record (Type 04) defines bits 16 to 31 of the 32-bit linear base
address. This address will be added to subsequent data record addresses to provide the
absolute address.
Table 3: Input Data Type 00
BC
AAAA
00
hhhh.h
CC
Start
Character
Byte Count
Hex Address
Record Type
hh = 1 Data
Byte
Checksum
2 Characters
4 Characters
2 Characters
2 up to 32
Characters
2 Characters
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XAPP694 (v1.0) May 26, 2004
Reference Design Implementation

:
00
0000
01
FF
Start Character
Byte Count
Hex Address
Record Type
Checksum
2 Characters
4 Characters
2 Characters
2 Characters

:
02
0000
04
hhhh.h
CC
Start
Character
Byte Count
Hex Address
Record Type
2 Byte Offset
Checksum
2 Characters
4 Characters
2 Characters
2 up to 32
Characters
2 Characters
PROM Size
Care must be taken not to add too much user-defined data to the PROM, since this will cause
the configuration tools to reject the PROM file. To select a PROM that can store both the FPGA
configuration and the user-defined data, simply add the number of bits used for the FPGA
configuration to the number of user-defined data bits and synchronization patterns. The
number of bits used for the FPGA configuration can be found by consulting the appropriate
FPGAs data sheet.
Note: A detailed description of how to use the Perl script can be found in the readme.txt file in the
\Perl_Script directory of the reference design.
Reference
Design
Implementation
The reference design described in this application note can be implemented on the Xilinx
Virtex-II High Speed Demo Board. A block diagram of the design is shown in Figure 9.
read
next_sync
dout
data_ready
Debouncer
Debouncer
LCD Driver
(PicoBlaze)
PROM
Reader
LCD_data
LCD_RW
LCD_RS
LCD_E
LCD
Display
sync
cclk
reset_prom
reset_display
clock
reset
FPGA
x694_09_033104
Figure 9: Reference Design for Virtex-II High Speed Demo Board

The user-defined data retrieved from the PROM is displayed on an LCD display. The LCD driver
is implemented using PicoBlaze.
XAPP694 (v1.0) May 26, 2004
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Other
Implementations
Other Implementations
Until now, this application note has dealt with reading user-defined data from a configuration
PROM in a serial fashion. What happens when the PROM is connected in SelectMAP mode?
What if different synchronization patterns need to be used, and how does the designer keep
track of which data block is currently being read?
These questions are dealt with in the following sections.
Parallel Implementation
The reference design described in this application note can be used for several
implementations. A macro that allows the FPGA to read user-defined data from the
configuration PROM in SelectMAP modethat is, 8 bits at a timeis also available. A
connection diagram for this implementation can be seen in Figure 10. The functionality of the
parallel macro is the same as that of the serial macro, except that additional manipulation
needs to be done in the Shift Register and Comparator block.
VCC
CLK
OE/RESET
CCLK
INIT / USERIO
(1)
M0
CE
CF
PROG
M1
D[7:0]
D[7:0]
M2
XILINX
CONFIGURATION
PROM
TCK
TCK
TMS
TMS
TDI
TDI
XILINX FPGA
USERIO
TCK
TMS
TDO
TDI
TDO
TDO
Notes:
1 Mode pin connections may be different for different architectures.
x694_10_033104
Figure 10: PROM and FPGA Connections in SelectMAP Mode

The connections shown in Figure 10 are the same as in Figure 1, except that now an 8-bit
connection exists between the PROM and the FPGA.
Synchronization Patterns
The reference design automatically scales the Shift Register and Comparator blocks
depending on a "length" parameter. The parameter is entered in the HDL code, and the
compiler uses this parameter to scale the block. The "length" parameter is the exponent of 2
that determines the number of bits used in the synchronization pattern:
No. of bits in synchronization pattern = 2length
Therefore, if length = 5 then
No. of bits in synchronization pattern = 25 = 32 bits
Keeping this in mind, the designer can choose different lengths for the synchronization pattern.
Although the pattern may be specified as a certain length, any pattern shorter than the length
specified can be used during operation, since the bits not used will simply be tied to ground.
Multiple Data Blocks

Each block of user-defined data can be specified by using either the same synchronization
pattern or a different synchronization pattern for each block. This is shown in Figure 11.
10
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XAPP694 (v1.0) May 26, 2004
Conclusion
XXXXh
XXXXh
Identical
Synchronization
Patterns
User Data Block 2
User Data Block 2
Sync Pattern 8F9FAFBFh
Sync Pattern F9F53A12h
Unused Space
Unused Space
User Data Block 1
User Data Block 1
Sync Pattern 78CD34BBh
User Data Block 0
User Data Block 0
Sync Pattern AA4499FFh
Area of Uncertainty
Area of Uncertainty
FPGA
Configuration
FPGA
Configuration
Different
Synchronization
Patterns
0000h
0000h
x694_11_033104
Figure 11: Using Identical and Different Synchronization Patterns

Both methods have advantages and disadvantages.
When using a synchronization pattern that remains constant, the user does not have to change
the pattern during operation. However, it is not always clear which data block is the current one.
A counter would need to be implemented in order to keep track of the data blocks.
By using different synchronization patterns for each data block, the blocks can be uniquely
identified and addressed. There is no need to keep track of which data block is currently being
used, since this is indicated by the pattern. The user, however, needs to change the pattern
depending on the data block that is required. This means that the synchronization patterns
need to be stored. The patterns may be hard-coded in the FPGA design or retrieved from preinitialized BlockRAMs. The patterns can also be stored as user-defined data in the PROM. The
first data block in the PROM contains all the synchronization words for all the other data blocks
stored in the PROM. This avoids having to hard-code the patterns in the FPGA design or
initialize BlockRAMs.
Conclusion
The design described in this application shows an efficient and cost-effective approach to
retrieving user-defined data from Xilinx configuration PROMs using existing connections and
only one user I/O.
Design
Resources
The reference design described in this application note can be downloaded from
http://www.xilinx.com/bvdocs/appnotes/xapp694.zip.
Comments and
Feedback
Any comments and feedback about this application and note and the reference design are
encouraged and may be sent to stephan.neuhold@xilinx.com
XAPP694 (v1.0) May 26, 2004
www.xilinx.com
1-800-255-7778
11
Revision
History
12
Revision History
Date
Version
05/26/04
1.0
Revision
www.xilinx.com
1-800-255-7778
XAPP694 (v1.0) May 26, 2004
DS114 (v1.7) August 31, 2006
MultiPRO Desktop Tool

0
Product Specification
Features
In-System Programming/Configuration
Supported by ISE iMPACT download software (v5.1i

SP3 or higher)
Automatically senses and adapts to target I/O voltage
Externally powered using +5V DC power brick
Interfaces to devices operating at 5V (TTL), 3.3V

(LVCMOS), 2.5V, 1.8V, and 1.5V
Supports IEEE 1149.1 (JTAG), Xilinx Slave-Serial, and

Xilinx Slave-SelectMAP
In-system configures the following Xilinx devices:
Same power brick can be used for Parallel

Cable IV
Download speeds up to 10 Megabits per second (Mb/s)
LED status indicators
Virtex series FPGAs
Uses IEEE 1284 ECP protocol for high-speed

communications
Spartan series FPGAs
CoolRunner/CoolRunner-II CPLDs
Uses quick-connect, off-the-shelf IEEE 1284 parallel

cable
Platform Flash PROM family
XC18V00 ISP PROM family
Power cord options for US/Asia/Japan/Europe/UK
XC4000 series FPGAs
XC9500/XL/XV CPLDs
Desktop Device Programming
Device adapters are available for:
XC18V00 ISP PROM family
Platform Flash PROM family
CoolRunner-II CPLD family
Automatically switches power during programming
Automatically identifies and confirms proper adapter

selection
Has short-circuit protection in the event of improper

device insertion
J Drive compatible with IEEE 1532 Programming

Engine
ChipScope ILA and ChipScope Pro compatible
Embedded Development Kit (EDK) compatible
Includes high-performance ribbon cables
14-conductor ribbon cable can be used with

Parallel Cable IV
Intended for development not recommended for

production programming
MultiPRO Desktop Tool Description

The MultiPRO Desktop Tool (Figure 1) is a multi-function
programming and configuration cable. When mated with
MultiPRO device adapters, it can program individual
Platform Flash PROMs, XC18V00 ISP PROMs and
CoolRunner-II CPLDs. Alternatively, the tool can perform
in-system programming or FPGA configuration when
attached to user hardware by way of the included ribbon
cables. IEEE 1149.1 (JTAG), Xilinx Slave-Serial, and Xilinx
Slave-SelectMAP protocols are supported in ISP mode.
A variety of device adapters are available for standalone

programming of Xilinx Platform Flash PROMs, XC18V00
ISP PROMs, and CoolRunner-II CPLDs.
Designed for use in a desktop environment, the MultiPRO

Desktop Tool interfaces to a PC using the industry standard
IEEE 1284 parallel port. An external AC power brick
provides +5V DC to the pod. An integral power switch
facilitates fail-safe connection to target systems.
Figure 1: Xilinx MultiPRO Desktop Tool
20022006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS114 (v1.7) August 31, 2006
www.xilinx.com
PN 0010985 01
1
Device Adapters
A separate device adapter is available for each unique
Platform Flash PROM, XC18V00 ISP PROM, and
CoolRunner-II CPLD package. Adapters attach to the
MultiPRO pod using a 20-pin keyed DIN connector
(Figure 2). Power is automatically applied to the adapter
during programming operations and removed upon
completion. A power status LED is illuminated whenever
power is active. The MultiPRO pod automatically identifies
any adapter that is attached to the DIN connector.
Caution! Devices should never be installed or removed
from sockets while the ACTIVE LED is illuminated.
A polycarbonate label protects the top side of the adapter

printed circuit. Text clearly identifies the device and package
information, the product ordering number, and the index pin
locator needed to orient the device during insertion.
20-pin Keyed
DIN Connector
An aluminum plate is attached to the bottom side of the

printed circuit board to protect circuitry. Rubber feet are
mounted on the bottom of the aluminum plate to avoid
scratching the desk top.
Over-Current Protection
The MultiPRO Desktop Tool monitors the current load of the
adapter when power is provided. If a fault condition exists
on the adapter (e.g., if a device is improperly oriented in the
socket or the device is internally shorted), power is
automatically shut off. The MultiPRO Desktop Tool will not
be damaged if the power pins on the DIN connector are
inadvertently shorted to ground.
Status Indicators
The MultiPRO Desktop Tool uses tri-color LEDs to indicate
the active configuration port and the presence of target
power (Table 1). A red LED indicates that the associated
port has not been selected in iMPACT. An amber LED
indicates that the port is selected but that VREF from the
target hardware is not powered. A green LED indicates that
the port is selected and VREF from the target hardware is
powered.
Power
Status LED
If both the Serial/JTAG and SelectMAP STATUS LEDs are

red, then the Adapter port is active. Power is automatically
switched to adapters only during programming operations.
The adapters red ACTIVE LED is illuminated when power is
ON. The MultiPRO Desktop Tool selects the Serial/JTAG
port by default when powered up.
If both the Serial/JTAG and SelectMAP LEDs are blinking
red, an over-current condition has been detected on the
adapter port. The adapter should be removed and checked
for incorrect device insertion and/or socket damage.
Index Pin Locator

Figure 2: Common Adapter Features
Table 1: Status Indicators
Serial/JTAG LED
SelectMAP LED
Pod Powered
Active Port
VREF Powered
IEEE 1284
Parallel Port
Connected
Off
Off
No
None
N/A
Yes
Amber
Red
Yes
S/JTAG
No
Yes
Green
Red
Yes
S/JTAG
Yes
Yes
Red
Amber
Yes
SelectMAP
No
Yes
Red
Green
Yes
SelectMAP
Yes
Yes
Red
Red
Yes
Adapter
See ACTIVE LED
Yes
Blinking Red
Blinking Red
Over-Current
Adapter
N/A
Yes
Amber
Amber
Yes
None
N/A
No
DS114 (v1.7) August 31, 2006
www.xilinx.com
PN 0010985 01
2
Physical Description
Power Switch
Serial/JTAG LED
+5VDC External Power

Supply Cable
INIT
NC
DIN
DONE
CCLK
PROG
Vref
SelectMAP
IEEE-1284-C
Parallel Port
MultiPRO
Desktop Tool
Model DLC8
Power 5V
0.3A
Serial MP - 1 2 3 4 5
Made in U.S.A.
Adapter Port
STATUS
NC
NC
TDI
TDO
TCK
TMS
Vref
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
CS0
CS1
CS2
PROG
INIT
DONE
BUSY
RDWR
CCLK
D0
D1
D2
D3
D4
D5
D6
D7
Vref
NC
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
JTAG
Serial
Power Port
S/JTAG
SMAP
14-pin Serial/JTAG
Ribbon Cable Connector
34-pin SelectMAP
Ribbon Cable Connector
STATUS
SelectMAP LED
Quick Connect IEEE 1284
Parallel Port Cable
HW-MP-PQ208
ACTIVE
20-Pin Keyed
DIN Connector
Adapter's red
"ACTIVE" LED
1
PIN
Socket
MultiPRO PQ208 Adapter

for CoolRunnerTM- II
ds114_04_090402
Figure 3: MultiPRO Connector Descriptions
External Power Supply

The MultiPRO Desktop Tool requires an external +5V DC
power supply. The power supply is a CE approved switching
regulator that operates from an AC outlet and connects to
the MultiPRO tool using a 5.5 mm x 2.1 mm plug (Figure 4).
A power switch on the MultiPRO case is provided as a
convenience so that all other cables can remain attached.
The standard MultiPRO power supply (CUI Inc.
#DTS050400UC-P5P-KH) is capable of operating from
100VAC to 240VAC at 47 Hz to 63 Hz. The +5V DC output
is rated for 4A. This power supply can also be used with the
Xilinx Parallel Cable IV (configuration cable) instead of the
supplied Power Splitter Cable.
DS114 (v1.7) August 31, 2006
Figure 4: Standard External +5V DC Power Brick
www.xilinx.com
PN 0010985 01
3
IEEE 1284 Cable Specifications
Connecting to Host Computer
Level 1 compliant host parallel ports are only designed to

operate over a maximum cable length of 10 feet. Level 2
compliant ports are designed to operate over a maximum
cable length of 33 feet. MultiPRO uses a Level 2 compliant
cable interface buffer. The MultiPRO case has an integrated
mini-centronics connector for attachment to off-the-shelf
IEEE 1284 cables.
The MultiPRO tool connects to any PC using Windows or

Linux1 through the built-in, standard IEEE 1284 DB25
parallel (printer) port connector2. To fully utilize the higher
speeds of this cable, the host PC must have a parallel port
that is enabled3 to support extended capability port (ECP)
mode. If ECP mode is not enabled, the MultiPRO tool will
default to compatibility mode and will not run at the optimum
speeds listed. Performance also depends on the MultiPRO
Desktop Tool firmware revision and ISE iMPACT software
version.4
Xilinx recommends that the MultiPRO tool be directly

connected to the host parallel port without the use of a switch
box. Software license "dongles" should not be attached to the
parallel port when communicating with the MultiPRO tool.
Notes:
1.
Automatic Voltage Sensing
2.
The MultiPRO Desktop Tool continuously monitors the VREF

pin on the Serial/JTAG and SelectMAP target interface
connectors. The current drain from the target power supply
attached to the VREF pin is less than 10 mA at 3.3V DC. The
target system reference voltage must be regulated and
cannot have a current limiting resistor in series with the
VREF pin on the interface.
No damage will occur to the MultiPRO Desktop Tool if the
target system is powered when the MultiPRO tool is not
powered. However, when powering up a system, it is
preferable to apply power to the MultiPRO tool first, followed
by power to the target system. The sequence should be
reversed when powering down.
The MultiPRO Desktop Tool always puts interface signals
on inactive ports in a 3-state condition.
The MultiPRO output drive voltage levels do not linearly
track voltage changes on the VREF pin. An appropriate
output signal level is established for a range of VREF
voltages. For example, if VREF is any voltage from +3.0V DC
to +5.0V DC, the MultiPRO tool sets the output signals for
the respective port to +3.3V DC.
3.
4.
Refer to ISE software manuals for details regarding supported

operating systems.
Xilinx makes no representations about compatibility with
third-party IEEE 1284 add-on adapters and does not support the
add-on adapters.
Refer to host PC BIOS to see if ECP mode is enabled.
Refer to the MultiPRO Desktop Tool firmware history at
http://www.xilinx.com/support/programr/mp_history.htm.
High Performance Ribbon Cable

Two insulation displacement connector (IDC) ribbon cables
are supplied and recommended for connection to target
systems. See Figure 5 and Figure 6. These cables
incorporate multiple signal-ground pairs and facilitate
error-free connection. A very small footprint, keyed mating
connector is all that is required on the target system. Refer
to Figure 7 and Figure 8 for the appropriate connector pin
assignments and sample vendor part numbers. The
14-conductor ribbon cable can also be used with Parallel
Cable IV.
Refer to Table 2 for the relationship between VREF voltage

and MultiPRO output signal levels.
Table 2: Output Signal Levels as a Function of VREF
VREF Voltage on Target
System
MultiPRO Output
Signal Levels
Units
0.80 to 1.65
1.5
1.65 to 2.00
1.8
2.00 to 3.00
2.5
3.00 to 5.00
3.3
DS114 (v1.7) August 31, 2006
Figure 5: High Performance Ribbon Cables

.
www.xilinx.com
PN 0010985 01
4
6"
Polarizing Key
2
4
6
8
10
12
14
pin#1 indicator stripe
1
3
5
7
9
11
13
Polarizing Key
2
4
6
8
10
12
14
1
3
5
7
9
11
13
Notes:
1. Ribbon cable 14-conductor, 1.0 mm centers round conductor flat cable, 28AWG (7x36) stranded copper conductors;
gray PVC with pin #1 edge marked.
2. 2 mm ribbon, female polarized connectors IDC connection to ribbon, contacts are beryllium copper plated with
30 micro inches gold plating over 50 micro inches nickel, connectors mate to 0.5 mm square posts on 2 mm centers.
ds097_03_081506
6"
Polarizing Key
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
pin#1 indicator stripe
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Polarizing Key
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Notes:
1. Ribbon cable 34-conductor, 1.0 mm centers round conductor flat cable, 28AWG (7x36) stranded copper conductors;
gray PVC with pin #1 edge marked.
2. 2 mm ribbon, female polarized connectors IDC connection to ribbon, contacts are beryllium copper plated with
30 micro inches gold plating over 50 micro inches nickel, connectors mate to 0.5 mm square posts on 2 mm centers.
ds114_09_081506
Figure 6: Ribbon Cable Diagrams
DS114 (v1.7) August 31, 2006
www.xilinx.com
PN 0010985 01
5
0.175"
0.220"
SelectMAP
Signals
0.0787" (2 mm)
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
VREF
NC
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
1.578"
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0.158"
CS0
CS1
CS2
PROG
INIT
DONE
BUSY
RDWR
CCLK
D0
D1
D2
D3
D4
D5
D6
D7
1.618"
0.020" sq. (0.5 mm)

0.215"
0.100"
2x17 (34-position) 2 mm CONNECTOR,

shroulded, keyed, through-hole mount.
Comm Conn part no. 2422-34G2
OUPIIN part no. 3112-34G00SBA/SN
Also available in surface mount or
without keyed shrould
0.0787" (2 mm)
ds114_08_081506
Figure 7: Target Interface 34-Pin Connector Signal Assignments
0.0787" (2 mm)
13
11
9
7
5
3
1
0.791"
INIT
NC 14
NC
NC 12
DIN TDI 10
DONE TDO 8
CCLK TCK 6
PROG TMS 4
VREF VREF 2
0.220"
0.175"
0.158"
Slave
Serial JTAG
Signals Signals
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
0.831"
0.020" sq. (0.5 mm)
0.215"
0.100"
2x17 (14-position) 2 mm CONNECTOR,

shroulded, keyed, through-hole mount.
Comm Conn part no. 2422-14G2
OUPIIN part no. 3112-14G00SBA/SN
Also available in surface mount or
without keyed shrould
0.0787" (2 mm)
ds114_10_081506
Figure 8: Target Interface 14-Pin Connector Signal Assignments
DS114 (v1.7) August 31, 2006
www.xilinx.com
PN 0010985 01
6
Table 3 lists some third-party sources for mating connectors for 2 mm pitch, 14-conductor ribbon cable.
Table 3: Mating Connectors for 2 mm pitch, 14 Conductor Ribbon Cable
Manufacturer
Part Number
Comm Con
2422-14G2
OUPIIN
3112-14G00SBA/SN
Notes: Also available in surface mount or without keyed shroud.
Table 4 lists third-party sources for mating connectors for 2 mm pitch, 34-conductor ribbon cable.
Table 4: Mating Connectors for 2 mm pitch, 34 Conductor Ribbon Cable
Manufacturer
Part Number
Comm Con
2422-34G2
OUPIIN
3112-34G00SBA/SN
Notes: Also available in surface mount or without keyed shroud.
Interface Pin Descriptions

The interface pins for the Serial/JTAG, SelectMAP, and adapter ports are described in Table 5, Table 6, and Table 7,
respectively.
Table 5: Serial /JTAG Port: 14-Pin Ribbon Cable Connector Interface Pin Descriptions
Ribbon
Cable Pin
Number
Slave-Serial
Configuration
Mode
JTAG
Configuration
Mode
Type
Description
VREF
VREF
IN
Target Reference Voltage. This pin should be connected to a

voltage bus on the target system that serves the JTAG or slave serial
interface. For example, when programming a Coolrunner-II device
using the JTAG port, VREF should be connected to the target VAUX
bus.
Notes: The target reference voltage must be regulated and must
not have a current limiting resistor in series with the VREF pin.
PROG
OUT
Configuration Reset. This pin is used to force a reconfiguration of

the target FPGA(s). It should be connected to the PROG_B pin of
the target FPGA for a single device system or to the PROG_B pin of
all FPGAs in parallel in a daisy-chain configuration.
CCLK
OUT
Configuration Clock. FPGAs load one configuration bit per CCLK

cycle in slave-serial mode. CCLK should be connected to the CCLK
pin on the target FPGA for a single device configuration or to the
CCLK pin of all FPGAs in parallel for a daisy-chain configuration.
DONE
IN
Configuration Done. This pin indicates to MultiPRO tool that the

target FPGA(s) have received the entire configuration bit stream. It
should be connected to the DONE pin on all FPGAs in parallel for
daisy-chained configurations. Additional CCLK cycles are issued
following the positive transition of DONE to insure that the
configuration process is complete.
10
DIN
OUT
Configuration Data Input. This is the serial input data stream for
target FPGAs. It should be connected to the DIN pin of the target
FPGA in a single device system or to the DIN pin of the first FPGA
in a daisy-chain configuration.
12
NC
NC
OUT
Test Driver. This pin is reserved for Xilinx diagnostics and should
not be connected to any target circuitry.
14
INIT
NC
BIDIR
Configuration Initialize. This pin indicates that configuration

memory is being cleared. It should be connected to the INIT_B pin
of the target FPGA for a single device system or to the INIT_B pin
on all FPGAs in parallel in a daisy-chain configuration.
DS114 (v1.7) August 31, 2006
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PN 0010985 01
7
Table 5: Serial /JTAG Port: 14-Pin Ribbon Cable Connector Interface Pin Descriptions(Continued)
Ribbon
Cable Pin
Number
Slave-Serial
Configuration
Mode
JTAG
Configuration
Mode
Type
Description
TMS
OUT
Test Mode Select. This is the JTAG mode signal that establishes
appropriate TAP state transitions for target ISP devices. It should be
connected to the TMS pin on all target ISP devices that share the
same data stream.
TCK
OUT
Test Clock. This is the clock signal for JTAG operations and should
be connected to the TCK pin on all target ISP devices that share the
same data stream.
TDO
OUT
Test Data Out. This is the serial output data stream for JTAG
operations and should be connected to the TDO pin on the last ISP
device in the target JTAG chain.
10
TDI
IN
Test Data In. This is the serial input data stream for JTAG
operations and should be connected to the TDI pin on the first ISP
device in the target JTAG chain.
1, 3, 5, 7, 9,
11, 13
GND
GND
Digital Ground
Table 6: SelectMAP Port: 34-Pin Ribbon Cable Connector Interface Pin Descriptions
Ribbon Cable Pin
Number
SelectMAP
Configuration Mode
Type
16
D0
BIDIR
Byte-Wide Data Bus, Bit 0
14
D1
BIDIR
12
D2
BIDIR
10
D3
BIDIR
D4
BIDIR
D5
BIDIR
D6
BIDIR
D7
BIDIR
18
CCLK
OUT
Configuration Clock
20
RDWR
OUT
Configuration Read / Write Control
22
BUSY
IN
Configuration Flow Control
24
DONE
IN
Configuration Done
26
INIT
BIDIR
Configuration Initialize
28
PROG
OUT
Configuration Reset
30
CS2
OUT
Chip Select 2
32
CS1
OUT
Chip Select 1
34
CS0
OUT
Chip Select 0
33
VREF
IN
Target reference voltage
31
NC
No Connection
1, 3, 5, 7, 9, 11, 13,
15, 17, 19, 21, 23,
25, 27, 29
GND
Digital Ground
DS114 (v1.7) August 31, 2006
Description
www.xilinx.com
PN 0010985 01
8
Table 7: Adapter Port: 20-Pin DIN Connector Interface Pin Descriptions

DIN
Pin Number
JTAG
Configuration Mode
Type
A8
TCK
OUT
Test Clock. This is the clock signal for JTAG operations. It is

connected to the TCK pin on the adapter socket.
A2
TMS
OUT
Test Mode Select. This is the JTAG mode signal that establishes
appropriate TAP state transitions for the target device. It is
connected to the TMS pin on the adapter socket.
A4
TDI
OUT
Test Data In. This is the serial input data stream for JTAG
operations and is connected to the TDI pin on the adapter socket.
A6
TDO
IN
Test Data Out. This is the serial output data stream for JTAG
operations and is connected to the TDO pin on the adapter socket.
A1
PEN
OUT
B4
ID1
IN
Adapter ID1. This is the high order bit for the automatic adapter
identification circuit.
A3
ID0
IN
Adapter ID0. This is the low order bit for the automatic adapter
identification circuit.
B1
VREF
IN
Adapter Reference Voltage. This voltage is established by a local

linear regulator on each device adapter according to the
specifications of the device family.
B7, B8, B9, A10,

B10
+5V DC
OUT
A9
EGND
Safety Ground
A5, B5, B6, A7
GND
Digital Ground
MultiPRO POD
Dimensions
Description
Port Enable. Reserved for future applications.
Switched Supply Voltage
5.05
INIT
NC
DIN
DONE
CCLK
PROG
Vref
IEEE-1284-C
Parallel Port
SelectMAP
MultiPRO
Desktop Tool
3.49
Model DLC8
Power 5V
0.3A
Serial MP - 1 2 3 4 5
Made in U.S.A.
Adapter Port
STATUS
NC
NC
TDI
TDO
TCK
TMS
Vref
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
CS0
CS1
CS2
PROG
INIT
DONE
BUSY
RDWR
CCLK
D0
D1
D2
D3
D4
D5
D6
D7
Vref
NC
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
JTAG
Serial
Power Port
S/JTAG
SMAP
3.34
STATUS
5.19
1.13
0.99
ds114_06_090402
Figure 9: MultiPRO Pod Dimensions (inches)
DS114 (v1.7) August 31, 2006
www.xilinx.com
PN 0010985 01
9

!"$

"
%"
!" #"
ds114_07_090402
Figure 10: Typical MultiPRO Adapter Dimensions (inches)
Operating Characteristics
Absolute Maximum Ratings
Symbol
Description
Value
Units
+6.0
0 to 70
40 to +85
VCC
DC Supply Voltage
TA
Operating Temperature Range
TSTG
Storage Temperature Range
PD
Power Dissipation
1.5
IOUT
DC Output Current (Any Output)
16
mA
Min
Max
Units
4.75
5.25
Recommended Operating Conditions

Symbol
Parameter
Conditions
VCC
DC Supply Voltage
VREF
Target Reference Voltage
1.5
5.5
ICC
Operating Current
130
200
mA
DS114 (v1.7) August 31, 2006
External Power Supply
www.xilinx.com
PN 0010985 01
10
Ordering Information
Part Number
Description
HW-MULTIPRO
MultiPRO Desktop Tool for US, Asia, Japan
HW-MULTIPRO-EC
MultiPRO Desktop Tool with European plug
HW-MULTIPRO-UK
MultiPRO Desktop Tool with UK plug
HW-MP-PC44-1
44-pin PLCC Adapter for XC18V00 PROMs
HW-MP-VQ44-1
44-pin VQFP Adapter for XC18V00 PROMs
HW-MP-VQ44-2
44-pin VQFP Adapter for CoolRunner-II CPLDs
HW-MP-CP56
56-ball Chip Scale Adapter for CoolRunner-II CPLDs
HW-MP-VQ100
100-pin VQFP Adapter for CoolRunner-II CPLDs
HW-MP-CP132
132-ball Chip Scale Adapter for CoolRunner-II CPLDs
HW-MP-SO20
20-pin SOIC Adapter for XC18V00 PROMs
HW-MP-PC20
20-pin PLCC Adapter for XC18V00 PROMs
HW-MP-PC44-2
44-pin PLCC Adapter for CoolRunner-II CPLDs
HW-MP-TQ144
144-pin TQFP Adapter for CoolRunner-II CPLDs
HW-MP-FT256
256-ball Fine Pitch Thin BGA Adapter for CoolRunner-II CPLDs
HW-MP-FG324
324-ball Fine Pitch BGA Adapter for CoolRunner-II CPLDs
HW-MP-PQ208
208-pin PQFP Adapter for CoolRunner-II CPLDs
HW-MP-V020
20-pin TSSOP Adapter for Platform Flash PROMs
HW-MP-FS48
48-ball Chip Scale BGA Adapter for Platform Flash PROMs
HW-MP-VO48
48-pin TSOP Adapter for Platform Flash PROMs
HW-MP-QF32
32-pin QFP Adapter for CoolRunner-II CPLDs
HW-MP-QF48
48-pin QFP Adapter for CoolRunner-II CPLDs
Revision History
Date
Version
12/10/02
1.0
12/24/02
1.1
Updated "Features", "Status Indicators", and "Adapter Port: 20-Pin DIN Connector Interface Pin
Descriptions".
01/24/03
1.2
Updated "Features", "Device Adapters", Table 1, "Automatic Voltage Sensing", Table 7, and "Ordering
Information".
04/10/03
1.3
Added list of supported Spartan-3 devices.
04/29/03
1.4
Added Platform Flash PROM family to "Desktop Device Programming", "MultiPRO Desktop Tool
Description", and "Ordering Information". Added "XCF00S/P" to "Device Adapters".
09/29/04
1.5
Added part numbers HW-MP-FS48 and HW-MP-VO48 to table in section "Ordering Information,"
page 11.
Section "External Power Supply," page 3: Changed specification of power supply.
01/04/06
1.6
Updated supported list of Xilinx devices and added recommendation for product usage during
development in section "In-System Programming/Configuration," page 1.
Added part numbers HW-MP-QF32 and HW-MP-QF48 to section "Ordering Information," page 11.
Updated OUPIIN part numbers in Figure 7, Figure 8, Table 3, and Table 4.
Promoted to Product Specification.
08/31/06
1.7
Updated the maximum download speed to 10 MHz and provided references to related firmware and
software requirements.
DS114 (v1.7) August 31, 2006
Revision
www.xilinx.com
PN 0010985 01
11
Parallel Cable IV
Parallel Cable IV
Figure 2-2 Top View of the Parallel Cable IV

The new Xilinx Parallel Cable IV (PC IV) is a high-speed download cable that
configures or programs all Xilinx FPGA, CPLD, ISP PROM, and System ACE MPM
devices. The cable takes advantage of the IEEE 1284 ECP protocol and Xilinx iMPACT
software to achieve download speeds that are over 10 times faster than the PC III.
The cable automatically senses and adapts to target I/O voltages and is able to
accommodate a wide range of I/O standards from 1.5V to 5V.
PC IV supports the widely used industry standard IEEE 1149.1 Boundary Scan (JTAG)
specification using a four-wire interface. It also supports the Xilinx Slave Serial mode
for Xilinx FPGA devices. It interfaces to target systems using a ribbon cable that
features integral alternating ground leads to reduce noise and increase signal
integrity.
The cable is externally powered from either a power brick or by interfacing to a
standard PC mouse or keyboard connection. A
bi-color status LED indicates the presence of operating and target reference voltages.
Connecting to Host Computer

http://toolbox.xilinx.com/docsan/xilinx4/data/docs/pac/cables6.html (1 of 4)15/03/2007 04:15:53 p.m.
Parallel Cable IV
The PC IV connects to any PC using Win98, Win2000, or WinNT (4.0 or higher)

through the standard IEEE 1284 DB25 parallel (printer) port connector. To fully utilize
the higher speeds of this cable, the host PC must have a parallel port that is enabled
to support extended capability port (ECP) mode. If ECP mode is not enabled, the PC
IV will default to compatibility mode and will not run at the optimum speeds listed.
Cable Power
The host interface cable (Figure 2-3) includes a short power jack for connection to
one of two possible +5V DC power sources: (1) an external AC adapter or (2) the
keyboard or mouse port of the host PC (shown). The supplied power splitter cable is
required when using the first option. The splitter cable is installed between the mouse
cable and the standard 6-pin mini-DIN (PS2) connector on the host PC. PC IV
operating current is less than 100 mA. It draws approximately 15 mA from the target
board's reference voltage supply to power the JTAG/Slave Serial buffers.
Figure 2-3 Parallel Cable IV Parallel and PS2 Connection

An insulation displacement (IDC) ribbon cable is supplied and recommended for
connection to target systems. This cable incorporates multiple signal-ground pairs and
facilitates error-free connection. A very small footprint, keyed mating connector is all
that is required on the target system. Refer to RD Redigure for the appropriate
connector pin assignments and sample vendor part numbers.
The Parallel Cable IV can also interface to target systems using flying lead wires.
However, these are not included with PC IV and can be purchased separately from the
Xilinx E-Commerce web site.
Parallel Cable IV
Figure 2-4 High Performance Ribbon Cable

Note Ribbon Cable - 14 conductor 1.0mm centers Round Conductor Flat Cable;
28 AWG (7x36) stranded copper conductors; gray PVC with pin 1 edge marked.
Note 2mm Ribbon Female Polarized Connectors - IDC connection to ribbon;
contacts are beryllium copper plated; 30 micro inches gold plating over 50
micro inches nickel; connectors mate to 0.5mm square posts on 2mm centers.
Target Board Header
Figure 2-5 Target Interface Connector Signal Assignments

Table 2-4 Mating Connectors for 2mm pitch, 14 Conductor Ribbon Cable
SMT.
Right
Angle
Through-Hole
Vertical
Through-Hole
Right Angle
Manufacturer
SMT. Vertical
Molex
87333-1420
N/A
87331-1420
87333-1420
FCI
95615-114
N/A
90309-114
95609-114
Comm Con
Connectors
2475-14G2
N/A
2422-14G2
N/A
Parallel Cable IV
Target Board Requirements

The following are general target board requirements for all target boards
regardless of the type of cable being used. Specific cables and configuration modes
may have additional target board requirements.

The Parallel Cable IV uses a high performance ribbon cable which incorporates
multiple signal-ground pairs. The cable has a single 14- pin connector which
requires a corresponding 14-pin board header with 0.5mm square posts on 2mm
centers.
When you lay out the printed circuit board for use with iMPACT in-system
programming and testing, a few adjustments will make the process of connecting
and downloading easier. Place pins or header on the board so that flying leads or
the high performance ribbon cable can reach them. The length of our flying leads is
either six inches (Parallel Cable) or twelve inches (MultiLINX Cable). The ribbon
cable is recommended for all new designs for the highest speed.
Flying Lead Connectors

Xilinx cables use flying lead connectors that have individual female connectors on
one end that fit onto standard 0.025 square male pins on your target board. Each
lead is labeled to identify the proper pin connection.
Flying Leads
Provide pins on your printed circuit board for your desired configuration
mode. For example, Boundary-Scan configuration would require VCC, GND,
TCK, TDO, TDI and TMS header pins.
These pins must be standard 0.025" square male pins that have dedicated
traces to the target device control pins. You connect to these pins with the
flying lead connector.
While pins may be a couple of inches apart, do not have any two JTAG
connector pins more than six inches apart. The high preformance cable is 6"
long.
Note Keep header pins on your board a minimum of 0.10" apart.
Mode Pin Connections for FPGAs Only
When using download cables to configure a device or chain of devices, you must
set the appropriate device configuration mode. You must set M0, M1, and M2 to
the value specified in the device's databook for the desired mode. Refer to the
Development System Guide or The Programmable Logic Data Book for information
on setting the mode pins.
If you are using a Parallel Download Cable proceed to the Parallel Cable section.
If you have a MultiLINX Cable proceed to the MultiLINX Cable section.
Software and Cable Interface

iMPACT allows for both automatic and manual cable connections.
Cable Auto Connect (Automatic)

Select Output
Cable Auto Connect if you want the software to scan for the
presence of a cable and automatically establish communication. Cable information
is presented in the status bar.
If you select any operation that requires a cable, such as Program or Initialize
Chain, without first selecting a cable connection, iMPACT will attempt to auto
connect.
Cable Setup (Manual)

After connecting the cable to download and verify, power your target board to
enable the software to communicate with the cable and start iMPACT. You can then
set the cable options manually with the following steps:
Cable Setup to display the Cable
1. Select Output
Communication Setup dialog box, shown in the following figure.
Figure 2-1 Cable Communication Setup Dialog Box

2. In the Communication Mode field, select the cable type that you installed for
downloading. The Parallel Cable is supported for the PC only.
3. In the Port Name list box, select the port to use for downloading and
readback. If the port name you want is not listed, select the blank name
from the list box and type in the new port name. This list box saves up to
two user-specified port names.
The Port Name list box contains a list of valid ports for the
platform, as shown in the following table. If you selected the
MultiLINX Cable, the USB port is displayed. If you selected a serial cable,
the serial ports are displayed. If you selected a parallel cable, the parallel
ports are displayed.
Table 2-3 USB, Serial, and Parallel Ports
Platform
USB Ports
Serial Ports
Parallel Ports
Sol
none
/dev/ttya, /dev/ttyb
not supported
HP 10.x
none
/dev/tty00, /dev/tty01 or /dev/

ttya, /dev/ttyb
not supported
PC
USB
com1, com2, com3, com4
lpt1, lpt2, lpt3, lpt4
4. In the Baud Rate list box, select a communications baud rate between the
cable and the host system. You cannot specify the baud rate for a parallel
cable.
Communication speed between the host system and the Cable depends on
host system capability. Refer to the "Valid Baud Rates" table for a list of
valid baud rates.
5. Click OK to accept the selections.

iMPACT will attempt to connect to the cable.
Resetting the Cable

To reset internal logic of the cable after a power glitch, select Output
Cable
Reset to reset the internal logic of the cable. The cable is reinitialized and the
proper baud rate is set.
Reset your cable if you experience a power failure to the target device board.
Disconnecting the Cable

To disconnect the cable connection, select Output
Cable Disconnect.
Note You will need to disconnect the cable if you wish to use the same cable
in a different configuration mode. For instance, if you start using the parallel
cable in boundary-scan mode, then wish to use it for Slave Serial
configuration, you will first have to disconnect it in boundary-scan and
reconnect it in Slave Serial mode.

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Spartan-3

Starter Kit Board

UG130 (v1.1) May 13, 2005

The shadow X shown above is a trademark of Xilinx, Inc.

Spartan-3 Starter Kit Board User Guide

Initial Xilinx release.

Minor modifications for printed release.

Added information on auxiliary serial port connections to Chapter 7.

Spartan-3 Starter Kit Board User Guide

UG130 (v1.1) May 13, 2005

Chapter 2: Fast, Asynchronous SRAM

Chapter 3: Four-Digit, Seven-Segment LED Display

Chapter 5: VGA Port

Chapter 6: PS/2 Mouse/Keyboard Port

Chapter 7: RS-232 Port

Spartan-3 Starter Kit Board User Guide

Chapter 10: Platform Flash Configuration Storage

Chapter 11: JTAG Programming/Debugging Ports

Chapter 12: Power Distribution

Chapter 13: Expansion Connectors and Boards

Appendix A: Board Schematics

Spartan-3 Starter Kit Board User Guide

About This Guide

Chapter 2, Fast, Asynchronous SRAM

Chapter 3, Four-Digit, Seven-Segment LED Display

Chapter 4, Switches and LEDs

Chapter 5, VGA Port

Chapter 6, PS/2 Mouse/Keyboard Port

Chapter 7, RS-232 Port

Chapter 8, Clock Sources

Chapter 9, FPGA Configuration Modes and Functions

Chapter 10, Platform Flash Configuration Storage

Chapter 11, JTAG Programming/Debugging Ports

Chapter 12, Power Distribution

Chapter 13, Expansion Connectors and Boards

Appendix A, Board Schematics

Appendix B, Reference Material for Major Components

Spartan-3 Starter Kit Board User Guide

Preface: About This Guide

Spartan-3 Starter Kit Board User Guide

Key Components and Features

4,320 logic cell equivalents

Twelve 18K-bit block RAMs (216K bits)

Twelve 18x18 hardware multipliers

Four Digital Clock Managers (DCMs)

Up to 173 user-defined I/O signals

2Mbit Xilinx XCF02S Platform Flash, in-system programmable configuration

1Mbit non-volatile data or application code storage available after FPGA

Jumper options allow FPGA application to read PROM data or FPGA

Two 256Kx16 ISSI IS61LV25616AL-10T 10 ns SRAMs

Configurable memory architecture

Single 256Kx32 SRAM array, ideal for MicroBlaze code images

Two independent 256Kx16 SRAM arrays

Individual chip select per device

Individual byte enables

3-bit, 8-color VGA display port

9-pin RS-232 Serial Port

DB9 9-pin female connector (DCE connector)

RS-232 transceiver/level translator

Uses straight-through serial cable to connect to computer or workstation serial

Spartan-3 Starter Kit Board User Guide

Figure 1-1: Xilinx Spartan-3 Starter Kit Board Block Diagram

PS/2-style mouse/keyboard port