Erik Jonsson School of Engineering & Computer Science

Recent Advances in Signal

Processing Techniques for Analog
g
Circuits
Integrated
Yun Chiu
Associate Professor, EE Department
TxACE Professor of Electrical Engineering
g
g
University of Texas at Dallas
E-Mail: chiu.yun@utdallas.edu

TxACE Symposium, 11/15/10

Technology Scaling
Source: www.intel.com

G. Moore, IEDM75

R. Chau, ICSICT04
35
3.5

Supply, Thresholld Voltages [V]

3
2.5
Precision Analog V
Analog
VDD
DD

Digital V
Digital
VDD

1.5

DD

1
0.5
0
250

Threshold Voltages
Threshold
Vth

200

150
100
Technology node [nm]

TxACE Symposium, 11/15/10

50

K. Bult, ISSCC98
-2-

Challenges for Analog/MS/RF Design

Technology
fs, P
Accuracy,
Matching,
Yield
Low
VDD

Variability

SCE,
Leakage

Well Proximity
Effect, STI
Stress

High
Integration
TxACE Symposium, 11/15/10

Complexity
Old days:
SPICE
Magic/L-Edit
DRC rules
Today:
T
d
PDK
Cadence,
Synopsys,
y p y ,
Mentor
HSPICE,
SpectreRF,
AMS ADS
AMS,
ADS
Long sim time,
substrate noise,
crosstalk

-3-

Practicality
Solutions:
Digital
g
correction,, aka
digital calibration,
digital assistance,
digital enhancement,
etc
etc.
Alternative architecture
Dynamic amplifier
CT DSP

Problems:
Robustness, e.g.,
CMRR, PSRR
Adaptation time
Practical concerns and
adoption by industry

Digital Correction of Analog Circuits

History
Dated way back to 1980s (Lee, Hodges, and Gray, Berkeley)
Proliferated in 1990s and 2000s (Berkeley, CMU, Davis, Illinois,
MIT, NCTU, OSU, Stanford, UCSD, etc.)
Started with foreground
g
techniques,
q
, e.g.,
g,p
power-on calibration of an
offset or mismatch. Gradually moved towards background intensive
treatment for tracking environmental variations.
Rationale
With the unprecedented digital processing power available, in-situ
error-correction techniques can be efficiently incorporated on-chip to
mitigate
g
certain analog
g impairments.
p
Thus,, to improve
p
analog
g
performance, to simplify circuits, to save power, and to extend the
roadmap

TxACE Symposium, 11/15/10

-4-

Recent Trend in Data Converter Calibration

Lots of
DSP

ADC

Converters conveniently fit for digital-domain correction techniques.

Recent trend is to treat more analog non-idealities, moving towards
nonlinear corrections.

TxACE Symposium, 11/15/10

-5-

Example: Pipelined ADC

Vo

Active-Cascode
Op Amp
Pseudo-Diff. Inverters

TxACE Symposium, 11/15/10

-6-

Example: Pipelined ADC

VFS/4

VFS/4

Vout

Vout

-VFS/4

-VFS/4

Vin
TxACE Symposium, 11/15/10

Vin
-7-

Recent Trend in Data Converter Calibration

Lots of
DSP

ADC

w/ 9th-order polynomial

-75 dBFS
LDrawn
0.15m
VDD

Archimedes: Give me a place to stand on

on,
and I will move the Earth

1 2V
1.2V

May need lots of correction, PVT sensitivity, adaptation time, testability

O original
Our
i i l iintention
t ti was nott tto cutt corners
TxACE Symposium, 11/15/10

-8-

Error Parameter Extraction (I)

Foreground calibration
Normal conversion paused; often executed at system power-up
power up
Difficult to track environmental variations

Queue-based pseudo-background extraction

Background adaptive calibration
Test signal-free extraction
Reference ADC (equalization with training sequence)
Split ADC (blind equalization)

One-bit PRBS injection

j
to facilitate extraction
Sub-ADC PRBS injection
Sub-DAC PRBS injection

TxACE Symposium, 11/15/10

-9-

Error Parameter Extraction (II)

Ref. ADC Based
(Equalization)

Vin

Ref. ADC
ADC

d(n)

x(n)

DSP

y(n)

e(n)

Wang (2003), Chiu (2004), McNeill (2005), et al.

PRBS B
Based
d
(Dither)

Vin

PRBS( )
PRBS(n)

ADC

x(n)

DSP

y(n)

e(n)

T
Temes
(1996),
(1996) Lewis
L i (1998)
(1998), G
Galton
lt (2000)
(2000), ett al.
l
TxACE Symposium, 11/15/10

- 10 -

Equalization of Data Converter

Chiu, TCAS 04
Wang, CICC 03

Equalization can compensate inter-symbol interference in comm. receivers.

Equalization should also correct inter-stage interference in A/D converters.

TxACE Symposium, 11/15/10

- 11 -

Ahead of the Curve

10

2006 ITRS
2009 ITRS
O ADCs
Our
ADC

CICC08

ADC FoM [pJ/step]

A

ISSCC04

10

VLSI06

ISSCC09

10

-1

ISSCC10

10

Unpubd

Our ADCs
Year

FoM
[fJ/step]

ISSCC04

1680

VLSI06

834

CICC08

5870

ISSCC09

210

ISSCC10

45.6

Unpubd

37.8

-2
2

2005

2008

2011
Year

2014

2017

Figure of Merit (FoM) measures the energy efficiency of ADCs

TxACE Symposium, 11/15/10

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Convergence Time (I)

1.E+11

# of S
Samples

1.E+10
1.E+09
1.E+08

1.E+07
1.E+06

104:1

~4N

1.E+05

1.E+04

6(?)
( )

1.E+03
11

12

13

14

15

16

17

Author

Sample SFDR

XXX

134M

90dB

XXX

40M

80dB

XXX

268M

93dB

XXX

225M

96dB

XXX

400M

98dB

XXX

10k

Ours

22k

95dB

SFDR Bits

Adaptation speed determines the sensitivity, testability, and ultimately

practicality of a treatment.

TxACE Symposium, 11/15/10

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Convergence Time (II)

Digital harmonic distortion correction of pipelined ADC (ISSCC09)

demonstrated an adaptation time of a few minutes.
minutes
TxACE Symposium, 11/15/10

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Why Dithering is Slow?

Analog domain injection

Digital domain correlation

large input signal causes significant interference to the correlation (~22N).

One PRBS typically only identifies one error parameter. Multiple PRBS
injections are necessary for multi-stage, nonlinear calibration.

TxACE Symposium, 11/15/10

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Why Equalization is Fast?

Zero-forcing (ZF) e drops to 0 with the help of a training sequence.

ZF offers the possibility of treating multiple error parameters simultaneously.
p
speed
p
is scalable to the reference speed.
p
Adaptation

TxACE Symposium, 11/15/10

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Equalization of Time-Interleaved (TI) ADC

Analog (0.13-m CMOS)
1X

Digital

Ref.
ADC Dr

ISSCC09
46th ISSCC/DAC SDC Award

r
ADC1
Vin

T/H

1X

D1

ADF1

DLL

1
10

ADC10

D10

ADF10

0.13-um CMOS
AA: 1.01.1 mm2

10

All paths
th are aligned
li
d to
t the
th unique
i
ref.
f ADC after
ft equalization
li ti
TxACE Symposium, 11/15/10

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Measured Spectra of TI-ADC

0

Before Calibration

-10
10

SNDR=31.2dB
SFDR 33 0dB
SFDR=33.0dB

0
-10
10

After Calibration
SNDR=46.7dB
SFDR 65 2dB
SFDR=65.2dB

0
-10
10

-20

-20

-20

-30

-30

-30

-40

-40

-40

-50

-50

-50

-60

-60

-60

-70

-70

-70

-80

-80

-80

-90
0

100 200 300

frequency [MHz]

TxACE Symposium, 11/15/10

-90
0

100 200 300

frequency [MHz]
- 18 -

-90
0

Reference ADC
SNDR=42.2dB
SFDR 60 5dB
SFDR=60.5dB

100 200 300

frequency [kHz]

Self-Equalization Offset Double Conversion

ADC self-equalization no additional reference ADC required!

All capacitor coefficients { Wj } are identified simultaneously!

TxACE Symposium, 11/15/10

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Prototype 12-Bit SAR ADC

The return of SAR amplifying-free

p y g
and superb
p
energy
gy efficiency
y
TxACE Symposium, 11/15/10

- 20 -

Die Photo (0.13-m CMOS)

ISSCC10

TxACE Symposium, 11/15/10

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Measured Performance @ 12-b, 45-MHz

0

SNDR = 60.2 dB
SFDR = 66.4 dB
THD = -61.7 dB

-20

-20

-40

-40

Aft C
After
Cal.
l

-60

dB

dB

B f
Before
C
Cal.
l
-60

-80

-80

-100

-100

-120
0

SNDR = 70.7 dB
SFDR = 94.6 dB
THD = -89.1 dB

5
Freq [MHz]

TxACE Symposium, 11/15/10

-120
0

10

- 22 -

5
Freq [MHz]

10

Convergence Speed
e [LSB]

10
5
0
-5
0

3
4
Number for samples

3
4
Number for samples

3
4
Number for samples

x 10

10
e [LSB
B]

6
4

5
0
-5
0

6
x 10

e [LSB]

10
5
0
-5
0

22000 samples @ 22
22.5
5 MS/s 1 millisecond
TxACE Symposium, 11/15/10

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6
x 10

Comparison of 12-b ADCs

1

FoM (pJ/conv. step)

10

10

-1

10

46 fJ/step @ 22.5 MS/s

31 fJ/step @ 45 MS/s
-2

10
2
10

2000

2002

2004

2006

2008

2010

Year

Active area (mm 2)

10

10

-1

10

0.06 mm2

Total Power: 3.0 mW

-2

10

2000

2002

2004

2006

2008

2010

Year

TxACE Symposium, 11/15/10

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RF Transmitter Equalization

Nonlinear RF Transmitter

Digital Processing
TxACE Symposium, 11/15/10

Linear Feedback Path

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RF TX Distortion Mechanism

TxACE Symposium, 11/15/10

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2D Baseband Adaptive Predistortion

TX
Data

Complex Multiplier
To DAC
I

A p (r) = r -1 Fp (r) cos Gp (r)

Bp (r) = r -1 Fp (r) sin Gp (r)

2-D ML-LUT
Integer
Delay

1-z
Fractional
Delay

Ip + jQp

-2

I+ jQ
LMS
Update

Coarse
Rotation

From
ADC

= A p r + jBp r
N

k=0

2D multilevel LUT compensation of RF TX nonlinearity

Divide-and-conquer results in fast convergence and tracking

TxACE Symposium, 11/15/10

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A p (r)
( ) + jBp (r)
( ) = Ck 2k r

Class-B CMOS PA Prototype

1.2 V

2.5 V

Power Gain

25

15

20

Chip
Boundary

bondwires
To
T
Balun
M7

From
Mixer

M8

M4

10
5

0
0
-5
5

M5
M1

10

thick-oxide
M3

Pout

15

M6

-10
-20

M2

-15

-10

-5

-5
10

Pin [dBm]
60
50

2nd-harmonic
termination

40
30

3.5-GHz
3 5 GHz two
two-stage
stage Class
Class-B
B PA

20

Fabricated in 0.13-m CMOS

10

Measured 55% DE + 25dBm output

p p
power

-5
5

10

15

20

25

Pout [dBm]
TxACE Symposium, 11/15/10

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Die Photo (0.13-m CMOS)

1.7 mm

CICC09

2.7 mm

TxACE Symposium, 11/15/10

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Experimental Setup

System convergence time was measured 2

2.3
3 ms after power
power-on
on reset
reset.
TxACE Symposium, 11/15/10

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Measured OFDM Constellation

Before EQ

After EQ

64-QAM OFDM, PAPR = 9.6 dB, bandwidth = 20 MHz, data rate = 54 Mbps

TxACE Symposium, 11/15/10

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Measured EVM Performance

EQ:
2-D 4-level LUT
DAC/ADC:
80-MS/s, 10-bit
LPF:
35-MHz cut-off

TxACE Symposium, 11/15/10

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Measured ACPR Performance

TxACE Symposium, 11/15/10

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Conclusion

Some recent developments in digital error

correction of analog circuits are reviewed.
Signal
g
p
processing
g is coming
g strong
g from
system side to help analog sustainability.
gp
performance and circuit
Raw analog
robustness needs to be guaranteed before
digital boosters are administered.

TxACE Symposium, 11/15/10

- 34 -

Acknowledgements

Intel Corp.
Analog Devices
Agilent Technology
ITRI, Taiwan
Marvell Semiconductor

TxACE Symposium, 11/15/10

- 35 -