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IC Layout Training Course

Week 3
Prepared by EKLakshya
and
Dan Clein

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IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented EKLakshya and Dan Clein
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What is a Standard Cell Library?

CMOS IC Layout: Concepts, Methodologies and Tools


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Set of Building Blocks with:

Common Interfaces

Synthesis Views

Simulation Views

Layout Views

Cells within library are


generally logic functions

The synthesis process


chooses only cells that are
available in the library.

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Why were Libraries Developed?

Increase in Design Size and


Complexity

Shortage of Personnel to do
Full Custom design
Process improvements such
as more routing layers

Productivity gains from

standard cell interfaces


Automation provided by CAD
tools

CMOS IC Layout: Concepts, Methodologies and Tools


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Standard Cell Characteristics - Design

IC Layout Training Course

Pre-characterized from either

Silicon Measurements

Extracted Layout

Multiple Drive Strengths for

each cell type


CAD Tool Views include:

Function

Timing
Power

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Area
Interface

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Standard Cell Dimensions

Cells are built using a Template

CMOS IC Layout: Concepts, Methodologies and Tools


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Standard Height of the cell


Placement of wells
Placement of NMOS and PMOS
Guidelines for use

Cells are rectangular in shape.


Height and Width depend on:

IC Layout Training Course

Design Rules
Desired Cell Grid
Tools to be supported
Type of Library
Porosity and the Number of
available layers

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Standard Cell Interface


VDD

IC Layout Training Course

VDD

IN1

OUT

VDD

In1

IN2

VDD

In1
Nandx2

Out

Out

Nandx2

In2

VSS

VSS

In2
IN1

OUT

IN2

VSS
Logic Symbol

Layout = standard gate representation

Power Lines are aligned


I/O Pins are well defined:

Schematic = gate representation

Type
Layer
Position
Size

Targeted to specific Place and Route tools

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Standard Cell Power Routing

Power supply issues for the entire


block must be addressed after
the rows are defined.

Strapping and connection of the


power supplies is always
implementing before signal
routing.
Issues to consider are:

CMOS IC Layout: Concepts, Methodologies and Tools


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Connectivity between standard


cells

Tracks routed internally to the


standard cells

Electromigration applied to track


width and number of vias

Resistance

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Standard Cell Interface - Abutment

Cell Abutment from each cell to


all other cells is highly desired
The interface of the cells may
be designed to share
connections

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Power
Wells

Abutment Approaches include:

IC Layout Training Course

Touching Polygons
Half Design Rule
Overlapping Polygons

Key is for Correct by


Construction results - DRC rule
violations are to be avoided at
all costs.

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Standard Cell Interface - Abstract

Cell Abstract:

10

CMOS IC Layout: Concepts, Methodologies and Tools


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Cell boundary
Location and shape of target
pins
Routing obstructions

Cell Boundary must be


rectangular
A set of obstructions for each
routing layer is required.

Obstructions can have any


shape.

They are not restricted to


independent rectangles but
they have to be recognized
by the routing tool

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Standard Cell Interface - Abstract

Full Cell layers

IC Layout Training Course

Metal 1 Only

The picture above shows 3 possible views of an example standard cell:


Full layout
Simple obstruction of the metal 1 and metal 2 for the router
Smart obstruction by over sizing the normal metal1 and generating
only one metal 1 obstruction layer - the router uses less information

11

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Standard Cell Channel Router Example 1


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Example A
IN1

Example C

VDD

VDD

IN2

OUT

a/2

Example B

Metal1

a/2

VDD
Metal2

a/2
IN1

OUT

a/2
IN2

a/2
IN1

OUT

a/2
IN2

Vertical routing
guide

Horizontal
routing guide

VSS
a

a/2
IN1

OUT

12

Channel Router with over the cell


capabilities
Could be 2, 3 metal routing

Channel Router with over the cell


capabilities
Short metal1 horizontal routing

Feed
through

LEGEND of layers
involved in routing

Two (?) Examples:

VSS

IN2

Channel Router without over the cell


routing capabilities
or 1 metal library

VSS

a/2

boundary pins to channel


pin to pin channel - over the cell routing capabilities
??

Filler Cells - Empty Cells for feed-through signals


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Standard Cell Channel Router Example 2


IC Layout Training Course

without

over the cell routing

Two Examples:
Channel used by the router

boundary pins to channel

pin to pin channel - over

Channel used by the router

Full height of the 3 rows including routing

Channel router

the cell routing


Channel router

with

over the cell routing

Channel used by the router - over the cell routing

Filler Cells - Empty Cells


for feed-through signals

13

CMOS IC Layout: Concepts, Methodologies and Tools


ISBN #: 0-7506-7194-7

Channel used by the router - over the cell routing

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Full height of the 3 rows including


routing

capabilities

Standard Cell Place & Route


IC Layout Training Course

Placement complete

Routing complete

Example of student
test chip using
Tanner channel
based router

14

CMOS IC Layout: Concepts, Methodologies and Tools


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Standard Cell Routing Grid (1)


IC Layout Training Course

smallest cell size

bigger cell size

biggest cell size

VDD

VDD

VDD

C
D

A
D

B
VSS

A
B

VSS

B
VSS

Line to line minimum pitch

15

Via to Via pitch

From the presented examples we can easily analyze the 3 types of routing
grids:

Via to line pitch

line to line
via to line
via to via

The benefits for porosity are increasing as the distance between the
routing grids grows.
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Standard Cell Routing Grid (2)

16

From the
presented
examples we can
easily analyze the
2 types of routing
grids:

via to line

via to via

The benefits for


porosity are
increasing as the
distance between
the routing grids
grows
CMOS IC Layout: Concepts, Methodologies and Tools
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IC Layout Training Course

IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
17

CMOS IC Layout: Concepts, Methodologies and Tools


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Gate Arrays

IC Layout Training Course

identically patterned

VDD

VDD

Gate Array: an array of


transistors or groupings of
transistors called base cells.

Out

Out

VSS

Can be Pre-fabricated

Logical definition of the

VSS

standard cells and the


IN

IN

connections between them


are defined by higher level
Basic layers

18

Connectivity shade

CMOS IC Layout: Concepts, Methodologies and Tools


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Full standard cell - buffer

layers only.

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Gate Array Master Slice

IC Layout Training Course

A wafer of base cells without


any standard cells defined

Can be fabricated while the


circuit design is in progress

Custom
made block
surrounded
by power
lines

or manufactured in advance.

Good for:

Multiple designs sharing die

Design in Parallel with


Manufacturing

Chips off the shelf

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Gate Array Benefits

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IC Layout Training Course

Faster Design Time

Wafers prefabricated with base layers


Iterations and optimization to cell placement and interconnect routing is greatly
reduced due to limited placement sites and lower cell density
Revisions to existing design starts with pre-fabricated wafer
Process characteristics such as latch-up are debugged with master slice.

Performance

more opportunities for layout optimizations

Increased Reuse

Master slices can be used for different designs or applications


Cell design easier to port to different process

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Gate Array Drawbacks

Design Flexibility

IC Layout Training Course

Fixed availability of total number of gates


Less opportunity for layout optimization
Less opportunity for custom blocks such as memories

Cell Density

21

Generic base layer cell design results in overhead of unused transistors.

CMOS IC Layout: Concepts, Methodologies and Tools


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Gate Array Uses

IC Layout Training Course

Custom Master Slices

Example of multiple
applications with common
requirements such as a
similar amount of memory

22

CMOS IC Layout: Concepts, Methodologies and Tools


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Cost Savings

Derivatives to a Product

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Gate Arrays Uses

IC Layout Training Course

Embedded Logic
When might an embedded gate array
design style be useful?

The logic portion of the design is


very risky

23

CMOS IC Layout: Concepts, Methodologies and Tools


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The logic is complex

Both of the above are true

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IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
24

CMOS IC Layout: Concepts, Methodologies and Tools


ISBN #: 0-7506-7194-7

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Datapath Cells

IC Layout Training Course

Data - implies that there are


multiple signals

Path - implies that the signals


are manipulated in a serial
fashion

25

CMOS IC Layout: Concepts, Methodologies and Tools


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Example is ALU

Regular Structure

Signal Flow

Multiple Signals or Busses

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Datapath Example Schematic

F2
A (7:0)

O1
(7:0)
C2

B (7:0)

F1
F3
O2
(7:0)

C (7:0)
C1

C3

D (7:0)

26

CMOS IC Layout: Concepts, Methodologies and Tools


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What are the characteristics of


datapath cells that
distinguish them from
standard cells?

Signal Flow - typically there is


a bit of data flowing through
the circuit in a serial sequence
of events

Multiple Signals - several


groups or busses of signals are
flowing through the circuit at
the same time (parallelism)

Layout Challenge is to achieve


Symmetry amongst bits in the
bus because each bit is
processed simultaneously by
the same function
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Datapath General Approach

IC Layout Training Course

F
2

VSS

0 1 2 3 4 5 6 7 8

O
1

Basic bit cell

B
F
1

VDD

F
3

9 vertical routing
channels
C

0
VSS

1 2 3 4 5 6 7 8

O
2

Consider 1 bit and repeat


Use regular layout structure to design
layout
Design for abutment
Consider signal flow

Symmetry between bits is guaranteed!


27

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Datapath Implementation
VSS
0 1

VSS
0 1

VSS
0 1

IC Layout Training Course

VSS

VDD

VDD

End cell

control line

VDD

control line

VDD

for

control line

control lines
2
2

3
3

VSS
4 5
4 5

6
6

7
7

8
8

0
0

1
1

2
2

3
3

VSS
4 5
4 5

6
6

7
7

8
8

0
0

1
1

2
2

3
3

VSS
4 5
4 5

6
6

7
7

8
8

VSS
VSS

End cell

Local logic gates

VDD

VDD

VDD

VDD

control lines

VSS
1 2

VSS
1 2

VSS
1 2

1 2
VSS

1 2
VSS

1 2
VSS

control line

control line

VSS
VSS

Local logic gates

control line

VDD

VDD

VDD

End cell

VDD

for

for

control lines
0

2 3
VSS

Bit #1

2 3
VSS

Bit #2

2 3
VSS

Bit #3

VSS

Logic end

ENDL

CMOS IC Layout: Concepts, Methodologies and Tools


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Second function

1
1

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Third function

0
0

28

First function

Local logic gates

Datapath Detailed Layout Example

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CMOS IC Layout: Concepts, Methodologies and Tools


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IC Layout Training Course

Bus Interface Unit (BIU) - Layout

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CMOS IC Layout: Concepts, Methodologies and Tools


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IC Layout Training Course

IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
31

CMOS IC Layout: Concepts, Methodologies and Tools


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Clock Generators

IC Layout Training Course

Special cells in a library


Buffer or amplify a very heavily loaded signal

What is so special about clock generator cells?

Transistor size: 1500 to 2000 microns for a single


device
Optimizing signal and power connections

Healthy substrate connections

Techniques to reduce supply resistance

Electromigration rules must be strictly followed.

The timing characteristics of clock signals are critical

Symmetrical layout for Clock balancing between 2


clocks

32

CMOS IC Layout: Concepts, Methodologies and Tools


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Clock Generator - Waffle Transistor

IC Layout Training Course

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CMOS IC Layout: Concepts, Methodologies and Tools


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IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
34

CMOS IC Layout: Concepts, Methodologies and Tools


ISBN #: 0-7506-7194-7

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Bond Pad

IC Layout Training Course

Passivation or Overglass
VIA between Metal 2 and Metal 1
Metal 2
Metal 1
N well

35

CMOS IC Layout: Concepts, Methodologies and Tools


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Interface to Chip
Package

Large metal targets


for gold bold wires

Large - around 85x85


microns

Pad metal is the top


layer of metal and
typically has a very
large via connecting
the top layer of metal
to the underlying
layers.

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Bond Pad Design Rules

IC Layout Training Course

Pad to SCRIBE distance

Origin

Window to
window

Origin

d
Ra

us

re
ff

pa

opening

Center to center rule

Origin

Minimum pad output WIDTH


Minimum height of 45 degree connection

Free of any polygon zone


See the arcs around the corners of the
passivation window

36

CMOS IC Layout: Concepts, Methodologies and Tools


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Origin

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n
zo

Pad Cells - What is ESD?

IC Layout Training Course

Electro-Static Discharge is the discharge of a large


amount of charge into a chip.

The most common source of ESD is from the human


body, when a person incorrectly handles an IC.

The resulting voltage can be in excess of 20,000V

ESD damage to electronic devices can occur at any


point from manufacture to field service.
There are layout techniques to protect against ESD
damage!

37

CMOS IC Layout: Concepts, Methodologies and Tools


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Pad Cells - Output Buffers


IC Layout Training Course

Large drivers that send a signal off chip. The width of


these devices are easily in the magnitude of 400-1000
m.

The size of the buffer will depend on:

frequency

power

voltage levels

current drive and functionality

Output buffers have a significant area impact so layout


implementation is important.

38

CMOS IC Layout: Concepts, Methodologies and Tools


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Pad Cells - Output Buffer

PAD output
c

IC Layout Training Course

Power

39

CMOS IC Layout: Concepts, Methodologies and Tools


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Basis Rules and


Guidelines
a - 45 degrees
polygons
b - distance contact to
gate on output
c - distance contact to
gate on power
d - height of increased
width
e - width of increased
width
f - output signal width
g - width of power line
h - gate special length

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Pad Cells - Input Protection

IC Layout Training Course

Input buffers accept signals from outside of the chip. In the specific
case of an I/O cell, a great deal of the ESD protection structures and
techniques are built into the output transistors.

Nevertheless, input protection structures are required to protect the


fragile transistors that buffer the external signal for internal use.
These devices are designed and tested, so if the manufacturer is
providing the layout in a specific process, the device is silicon proven
(?).
Option to variable resistance
Resistor layer

1/3 resistance
PAD connection
40

CMOS IC Layout: Concepts, Methodologies and Tools


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1/3 resistance

1/3 resistance
Signal to the input buffers

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IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
41

CMOS IC Layout: Concepts, Methodologies and Tools


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Memory Design - Architecture

Key Characteristic

fM

fM

fM

fM

M
M
M
M
M
M

M
M
M
M
M
M

M
M
M
M
M
M

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM
fM
fM

Word line strap

Word line

fM

fM

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

M
M
M
M

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

SA

Word line strap

SA_STRAP

WLDRV

WLDRV

WLDRV

SXDEC

WLDRV

WLDRV

WLDRV

SA

Pitch limited layout

Very Specialised

Word line strap

Process

Bit line

Word line strap


fM

fM

fM

M M M M M M M M M M

fM

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

M
M
M
M
M

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

Word line strap

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

fM

SA

SA

SA

SA

SA

SA

SA
SA_STRAP

fM

42

SA
SA_STRAP

fM

fM

YDEC_STRAP

fM

M M M M M M M M M M
M M M M M M M M M M

fM

SA
SA

YDEC

fM

fM

YDEC

SA

Area, Area, Area is key

Challenging Layout

Y select line

SA_STRAP

SA

SA

SA

fM

YDEC_STRAP

SA

SA

Bit line

fM

YDEC

SA

Bit line

fM

SA

SA

SA_STRAP

fM

SA

SXDEC

fM

M
M
M
M
M
M

SA_STRAP

SA

WLDRV
fM

M
M
M
M
M
M

fM

YDEC

WLDRV
fM

fM

fM

M
M
M
M
M
M

fM

YDEC_STRAP

SA

fM

M
M
M
M
M
M

fM

YDEC

fM

M
M
M
M
M
M

fM

SA

fM

M
M
M
M
M
M

fM

SA

fM

M
M
M
M
M
M

fM

YDEC

fM

fM

SXDEC

WLDRV

CORE Address and I/O

SA

SA

Word line strap

SA_STRAP

SA

SA

SA

SA

SA

SA

SA
SA_STRAP

Word line strap

SA

Word line strap

CMOS IC Layout: Concepts, Methodologies and Tools


ISBN #: 0-7506-7194-7

IC Layout Training Course

SA_STRAP

Word line strap

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Memory Design - Process Complexity


Word line

isolator
Metal 2
isolator
Metal 1

Read/Write
data

Sense
Amplifier

fM fM fM fM fM fM fM fM

Sense
Amplifier

fM M M M M M M fM

Sense
Amplifier

fM M M M M M M fM

fM M M M M M M fM

fM M M M M M M fM

fM fM fM fM fM fM fM fM

Layer Legend
Metal3

Friendly cells

Friendly cells

Select
transistor

Node
capacitor

Vertical cut in DRAM silicon over the memory


Read/Write select

Bit line

VCP plate

IC Layout Training Course

Sense
Amplifier
Sense
Amplifier
Sense
Amplifier

isolator
Upper plate poly
isolator
Node poly
isolator
Bit line poly
isolator
Gate poly
isolator
Silicon level

DRAM cell schematic and 4 poly layers process to accommodate


the cell capacitor
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Memory Design - Pitch Limited Cells

44

WL
Driver

WL
Driver

WL
Driver

WL
Driver

Sense
Amplifier

Sense
Amplifier

Sense
Amplifier

Sense
Amplifier

Strap

Strap

Strap

Strap

Strap

Strap

Strap

Strap

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Sense
Amplifier

Pitch limited layout

Restricted in one dimension


and must interface to a
leader.

All the planning efforts


should be focused in
minimizing the size in the
unrestricted dimension.

Pitch Limited Cells

Sense
Amplifier
Sense
Amplifier
Sense
Amplifier

Wordline Driver

Wordline Strap

Sense Amplifier

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Memory Design - Example

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Memory Design - Wordline Strap


Polygate wordline

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Metal wordline

#1 No Strapping - Electrically equivalent but impractical

#2 Regular Strapping - Only issue is testability. If a contact fails then the WL is


functional but weak. This condition is harder to detect than an outright failure.

#3 Asymmetric Strapping - Breaks in Gate poly address the contact failure


testability issue. If a contact fails then cells are inaccessible.

#4 Double Contacts - Possibly the optimal configuration but incurs an area


penalty relative to the other options.

#5 Symmetric Strapping - A better variation to #3 because WL performance is


symmetrical relative to the contact point.
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Laser Fuse Cells - Guidelines

IC Layout Training Course

Poor
Better
Smaller length

Independent fuse window

Multiple fuses in the same window

Best advisable

Fuse layer
Poly connection to the metal1

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CMOS IC Layout: Concepts, Methodologies and Tools


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Hard guard ring around fuses


made of active and metal1

Equally space fuses


Minimize the number
of rows
Minimize spacing
between rows
Minimize the number
of fuses
Document fuse
locations
Place required
alignment keys

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Memory Design - Wordline Strap

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Memory Design - Wordline Driver

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CMOS IC Layout: Concepts, Methodologies and Tools


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IC Layout Training Course

Laser fuse cells - reason and concept


IC Layout Training Course

DRAM memories are especially susceptible to process defects

Memory cells, wordline drivers, sense amplifiers, y-decoders are


highly susceptible to failure for this reason.

50

Redundant circuitry

Repairing DRAMs once they have been fabricated

Spare wordline drivers, sense amplifiers and y-decoders

Laser fuses : Disconnect the failing portions of the chip

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Laser Fuse Cells - Example

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CMOS IC Layout: Concepts, Methodologies and Tools


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IC Layout Training Course

IC Layout Training Course

Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
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CMOS IC Layout: Concepts, Methodologies and Tools


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Chip Finishing Cells - Identification

IC Layout Training Course

Fuse laser
alignment key
NIKON to
align masks
PAD 0 index
for the
packaging

A symbolic
representation of a
fuse row

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CMOS IC Layout: Concepts, Methodologies and Tools


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Examples are:

alignment keys for processing


equipment

structures for process dicing,


monitoring and packaging.

identification marks that may


be big enough to see with the
naked eye

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Chip Finishing - Scribe


CHIP

CHIP

Scribe line is the


middle of the
distance between 2
chips on the wafer

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

See the
enlarged vertical
view of the
"valley" between
chips

Cutting axis

Metal 4
Metal 3
Metal 2
Metal 1
Scribe width

Silicon wafer level

Chip to Scribe line

54

IC Layout Training Course

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Metal 4
Metal 3
Metal 2
Metal 1
Scribe width

Chip to Scribe line

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Memory Core

IC Layout Training Course

Memory Core
SEAL RING
SCRIBE

Memory Core

Control Logic Circuitry

Chip Finishing Cells - Seal Ring

Memory Core

VBB PUMP

Please analyze the VBB pump position, it should be as close


as possible to the seal ring.
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CMOS IC Layout: Concepts, Methodologies and Tools


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