Professional Documents
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Week 3
Prepared by EKLakshya
and
Dan Clein
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented EKLakshya and Dan Clein
2
Common Interfaces
Synthesis Views
Simulation Views
Layout Views
Shortage of Personnel to do
Full Custom design
Process improvements such
as more routing layers
Silicon Measurements
Extracted Layout
Function
Timing
Power
Area
Interface
Design Rules
Desired Cell Grid
Tools to be supported
Type of Library
Porosity and the Number of
available layers
VDD
IN1
OUT
VDD
In1
IN2
VDD
In1
Nandx2
Out
Out
Nandx2
In2
VSS
VSS
In2
IN1
OUT
IN2
VSS
Logic Symbol
Type
Layer
Position
Size
Resistance
Power
Wells
Touching Polygons
Half Design Rule
Overlapping Polygons
Cell Abstract:
10
Cell boundary
Location and shape of target
pins
Routing obstructions
Metal 1 Only
11
Example A
IN1
Example C
VDD
VDD
IN2
OUT
a/2
Example B
Metal1
a/2
VDD
Metal2
a/2
IN1
OUT
a/2
IN2
a/2
IN1
OUT
a/2
IN2
Vertical routing
guide
Horizontal
routing guide
VSS
a
a/2
IN1
OUT
12
Feed
through
LEGEND of layers
involved in routing
VSS
IN2
VSS
a/2
without
Two Examples:
Channel used by the router
Channel router
with
13
capabilities
Placement complete
Routing complete
Example of student
test chip using
Tanner channel
based router
14
VDD
VDD
VDD
C
D
A
D
B
VSS
A
B
VSS
B
VSS
15
From the presented examples we can easily analyze the 3 types of routing
grids:
line to line
via to line
via to via
The benefits for porosity are increasing as the distance between the
routing grids grows.
CMOS IC Layout: Concepts, Methodologies and Tools
ISBN #: 0-7506-7194-7
16
From the
presented
examples we can
easily analyze the
2 types of routing
grids:
via to line
via to via
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
17
Gate Arrays
identically patterned
VDD
VDD
Out
Out
VSS
Can be Pre-fabricated
VSS
IN
18
Connectivity shade
layers only.
Custom
made block
surrounded
by power
lines
or manufactured in advance.
Good for:
20
Performance
Increased Reuse
Design Flexibility
Cell Density
21
Example of multiple
applications with common
requirements such as a
similar amount of memory
22
Cost Savings
Derivatives to a Product
Embedded Logic
When might an embedded gate array
design style be useful?
23
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
24
Datapath Cells
25
Example is ALU
Regular Structure
Signal Flow
F2
A (7:0)
O1
(7:0)
C2
B (7:0)
F1
F3
O2
(7:0)
C (7:0)
C1
C3
D (7:0)
26
F
2
VSS
0 1 2 3 4 5 6 7 8
O
1
B
F
1
VDD
F
3
9 vertical routing
channels
C
0
VSS
1 2 3 4 5 6 7 8
O
2
Datapath Implementation
VSS
0 1
VSS
0 1
VSS
0 1
VSS
VDD
VDD
End cell
control line
VDD
control line
VDD
for
control line
control lines
2
2
3
3
VSS
4 5
4 5
6
6
7
7
8
8
0
0
1
1
2
2
3
3
VSS
4 5
4 5
6
6
7
7
8
8
0
0
1
1
2
2
3
3
VSS
4 5
4 5
6
6
7
7
8
8
VSS
VSS
End cell
VDD
VDD
VDD
VDD
control lines
VSS
1 2
VSS
1 2
VSS
1 2
1 2
VSS
1 2
VSS
1 2
VSS
control line
control line
VSS
VSS
control line
VDD
VDD
VDD
End cell
VDD
for
for
control lines
0
2 3
VSS
Bit #1
2 3
VSS
Bit #2
2 3
VSS
Bit #3
VSS
Logic end
ENDL
Second function
1
1
Third function
0
0
28
First function
29
30
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
31
Clock Generators
32
33
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
34
Bond Pad
Passivation or Overglass
VIA between Metal 2 and Metal 1
Metal 2
Metal 1
N well
35
Interface to Chip
Package
Origin
Window to
window
Origin
d
Ra
us
re
ff
pa
opening
Origin
36
Origin
n
zo
37
frequency
power
voltage levels
38
PAD output
c
Power
39
Input buffers accept signals from outside of the chip. In the specific
case of an I/O cell, a great deal of the ESD protection structures and
techniques are built into the output transistors.
1/3 resistance
PAD connection
40
1/3 resistance
1/3 resistance
Signal to the input buffers
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
41
Key Characteristic
fM
fM
fM
fM
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
Word line
fM
fM
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
SA
SA_STRAP
WLDRV
WLDRV
WLDRV
SXDEC
WLDRV
WLDRV
WLDRV
SA
Very Specialised
Process
Bit line
fM
fM
M M M M M M M M M M
fM
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
fM
SA
SA
SA
SA
SA
SA
SA
SA_STRAP
fM
42
SA
SA_STRAP
fM
fM
YDEC_STRAP
fM
M M M M M M M M M M
M M M M M M M M M M
fM
SA
SA
YDEC
fM
fM
YDEC
SA
Challenging Layout
Y select line
SA_STRAP
SA
SA
SA
fM
YDEC_STRAP
SA
SA
Bit line
fM
YDEC
SA
Bit line
fM
SA
SA
SA_STRAP
fM
SA
SXDEC
fM
M
M
M
M
M
M
SA_STRAP
SA
WLDRV
fM
M
M
M
M
M
M
fM
YDEC
WLDRV
fM
fM
fM
M
M
M
M
M
M
fM
YDEC_STRAP
SA
fM
M
M
M
M
M
M
fM
YDEC
fM
M
M
M
M
M
M
fM
SA
fM
M
M
M
M
M
M
fM
SA
fM
M
M
M
M
M
M
fM
YDEC
fM
fM
SXDEC
WLDRV
SA
SA
SA_STRAP
SA
SA
SA
SA
SA
SA
SA
SA_STRAP
SA
SA_STRAP
isolator
Metal 2
isolator
Metal 1
Read/Write
data
Sense
Amplifier
fM fM fM fM fM fM fM fM
Sense
Amplifier
fM M M M M M M fM
Sense
Amplifier
fM M M M M M M fM
fM M M M M M M fM
fM M M M M M M fM
fM fM fM fM fM fM fM fM
Layer Legend
Metal3
Friendly cells
Friendly cells
Select
transistor
Node
capacitor
Bit line
VCP plate
Sense
Amplifier
Sense
Amplifier
Sense
Amplifier
isolator
Upper plate poly
isolator
Node poly
isolator
Bit line poly
isolator
Gate poly
isolator
Silicon level
44
WL
Driver
WL
Driver
WL
Driver
WL
Driver
Sense
Amplifier
Sense
Amplifier
Sense
Amplifier
Sense
Amplifier
Strap
Strap
Strap
Strap
Strap
Strap
Strap
Strap
Sense
Amplifier
Sense
Amplifier
Sense
Amplifier
Sense
Amplifier
Wordline Driver
Wordline Strap
Sense Amplifier
45
Metal wordline
Poor
Better
Smaller length
Best advisable
Fuse layer
Poly connection to the metal1
47
48
49
50
Redundant circuitry
51
Week Three
Standard Cell Libraries
Gate Arrays
Datapath
Clock buffers
Pad Cells
Memory cells
Chip Finishing Cells
Presented by Xyz and Dan Clein
52
Fuse laser
alignment key
NIKON to
align masks
PAD 0 index
for the
packaging
A symbolic
representation of a
fuse row
53
Examples are:
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
CHIP
See the
enlarged vertical
view of the
"valley" between
chips
Cutting axis
Metal 4
Metal 3
Metal 2
Metal 1
Scribe width
54
Metal 4
Metal 3
Metal 2
Metal 1
Scribe width
Memory Core
Memory Core
SEAL RING
SCRIBE
Memory Core
Memory Core
VBB PUMP