Professional Documents
Culture Documents
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,
PVPIT, Budhgaon.
shindesir.pvp@gmail.com
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Wishbone
CoreFrame
Marble
performance Bus)
APB (Advanced Peripheral
Bus)
Avalon
CoreConnect
PLB (Processor Local Bus)
OPB (On-chip Peripheral Bus)
STBus
Type I (Peripheral protocol)
Type II (Basic Protocol)
Type III (Advanced protocol)
PI bus
OCP
VCI (Virtual Component Interface)
SiliconBackplane Network
Wishbone
CoreFrame
Marble
performance Bus)
APB (Advanced Peripheral
Bus)
Avalon
CoreConnect
PLB (Processor Local Bus)
OPB (On-chip Peripheral
Bus)
STBus
Type I (Peripheral protocol)
Type II (Basic Protocol)
Type III (Advanced protocol)
PI bus
OCP
VCI (Virtual Component
Interface)
SiliconBackplane Network
AMBA bus
AMBA is Advanced Microcontroller Bus Architecture
The AMBA protocol is an open standard, on-chip bus specification. It provides
AMBA bus
AMBA (Advanced Microcontroller Bus Architecture) is a bus standard
AMBA bus
The three distinct buses specified within the AMBA bus are:
ASB
ASB - first generation of AMBA system bus used for simple cost-
AMBA bus
The three distinct buses specified within the AMBA bus are:
APB
APB - is used to connect general purpose low speed low-power
peripheral devices.
The bridge is peripheral bus master, while all buses devices (Timer,
UART, PIA, etc) are slaves.
APB is static bus that provides a simple addressing with latched
addresses and control signals for easy interfacing.
AMBA bus
CoreConnect Bus
CoreConnect Bus
CoreConnect is an IBM-developed on-chip bus.
By reusing processor, subsystem and peripheral cores, supplied from
cores, library macros, and custom logic within a SoC as shown in figure.
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CoreConnect Bus
PLB Bus
PLB stands for Processor Local Bus
It is synchronous, multi master, central arbitrated bus that allows
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CoreConnect Bus
OPB Bus
OPB (On-chip Peripheral Bus) - is optimized to connect lower speed,
low throughput peripherals, such as serial and parallel port, UART, etc.
Crucial features of OPB are:
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CoreConnect Bus
DCR Bus:
DCR bus (Device Control Register bus) is a single master bus mainly
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ST Bus
ST Bus interconnect
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ST Bus
ST Bus is an on-chip bus protocol developed by ST Microelectronics.
It represents a set of protocol, interfaces and architectural specifications
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ST Bus
The following protocols are used
Type I (Peripheral protocol)
Type II (Basic Protocol)
Type III (Advanced protocol)
The ST Bus is modular and allows master and slaves of any protocol type and
Wishbone Bus
Wishbone bus architecture was developed by Silicore Corporation.
In August 2002, OpenCores (organization that promotes open IP cores
and distributed.
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Wishbone Bus
The Wishbone defines two types of interfaces, called master and slave.
Master interfaces are IPs which are capable of initiating bus cycles.
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Wishbone Bus
Point-to-point connection- used for direct connection of two participants
that transfer data according to some handshake protocol.
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Wishbone Bus
Shared bus- typical for MPSoCs organized around single system bus
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Wishbone Bus
Crossbar switch interconnection- usually used in MPSoCs when more
than one masters can simultaneously access several different slaves. The
master requests a channel on the switch, once this is established, data is
transferred in a point-to-point manner.
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Conclusion
The benefits of the SoC approaches are numerous like
improvements in system performance,
cost,
size,
power dissipation and
design turnaround time.
Chip integration continues to advance at a fast pace, the desire for efficient
interconnects rapidly increase.
Currently on-chip interconnections networks are mostly implemented using
traditional interconnects like buses.
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Thank You
Any ?s
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