VECTOR NETWORK ANALYSIS

Experiment: De-embedding, Measurements of

FET and BJT transistors in a test fixture
Group 05
Karim A. Eid
Hunbal Babar
Muhammad Zeeshan Khan
Muhammad Saad Ul Hassan

Table of Contents
VECTOR NETWORK ANALYSIS ............................................................................ 1
Experiment: De-embedding, Measurements of FET and BJT transistors
in a test fixture............................................................................................................ 1
Introduction: ..............................................................................................................................3
Measured and Calculated Results: ...........................................................................................4
Measurements of FET: ...........................................................................................................4
Measurements of BJT: ...........................................................................................................5
OPEN and SHORT Configurations: ........................................................................................7
Questions for the Report:..........................................................................................................8
Value of FETs Pinch-off bias Voltage: ..................................................................................8
Input Impedance of the FET and BJT: ...................................................................................8
Input Impedance of the FET and BJT: ...................................................................................8
Test fixture influence on measurement: ..............................................................................9
Parasitic Inductance and Capacitance: .................................................................................9
QUCS model: S parameter for Embedded and De-embedded: ........................................10
Summary: ................................................................................................................................11
References: ...............................................................................................................................11

Introduction:
Integrated RF components that are to be tested are usually embedded in a test fixture,
which provides interface between components pad and RF connectors. Also protection
through mechanical attachment of the device into a solid test board is provided. Embedding
and de-embedding are tools for virtually adding and subtracting networks to or from measured data. In many S-parameter measurements, one would desire to make the measurement with some other setup than what one has. There may be a test fixture required between the normal coaxial calibration planes and the DUT; it may be useful to see the DUT
performance with a certain matching network in place, it may be desired to see what the
subsystem performance would be when the given DUT is inserted, etc. One way of handling
these within the instrument is through embedding and de-embedding.
De-embedding is the act of taking data that is measured in a test fixture and removing the
effects of the fixture so that the data is accurate to reference planes that are more useful,
using vector measurements of known standards. For example, you can de-embed a FET
measurement so that the reference planes are the gate and drain bus bars; this data can be
used in an amplifier design or to create an equivalent circuit model. If your component is
matched to fifty ohms, you don't always need to properly de-embed it to understand its
performance. In most cases you only need to remove attenuation of input and output traces
from the test fixture. This is a scalar version of de-embedding, and you can do this in Excel
or even with a calculator, so long as you have data on fixture losses (over frequency) and
can distribute it to input and output sides. Sometimes the fixture is symmetrical, and you
can split its loss in half to make corrections. In this experiment, we measured the S parameter of the FET and BJT to see the performance and process de-embedding. The model of test
fixture is showed in the figure below.

Figure 1: Model of the test fixture with a DUT (BJT transistor). Series inductors and shunt capacitors
represent the inductance of metal leads and parasitic capacitance, respectively.

Lfb, Lin, Lout are series inductive parasitic elements caused by the connection lines of the
emitter, the base and the collector. L fb is about 10nH when it is approximately 10 mm long.
Cin, Cout, Cfb are shunt capacitive parasitic elements at both ports and in between

them(feedback capacitance).This causes less severe parasitic effect than inductive parasitic
elements. Besides, two different de-embedding structures without the actual DUT is needed
to determine the parasitic elements. They are SHORT configuration and OPEN configuration.
Then we can carry out the de-embedding procedure.

Measured and Calculated Results:

We did calibration of the VNA at the calibration plane, in the logarithmical frequency
band of 500 kHz to 500 MHz using the SOLT calibration standard. Then we set the TX attenuator to 20 db and the power level of the local oscillator to the maximum value, we also
set the power supply current limit using the datasheet of the FET and BJT.

Measurements of FET:
We connected the FET and set the VDS to 5V and observe the performance of the transistor for different values of the reverse voltage VGS (in the range from -6V to 0V). We notice
that as the reverse voltage was increased we notice that the current was also increasing. We
then kept the VGS constant and varied the VDS and we notice also that the current rises for
increase in VDS. We then measured full two-port S-parameters for the FET with the bias VDS =
5V, to set the ID to 7mA we took V GS = -2.0V.

Figure 2: Two-port S-parameters of FET at a fixed bias point

We see from the smith chart that the input and output impedances are capacitive in nature. Notice that S21, S12 are negative because 50 load is used. To have positive in dB of S12,
S21 in practice very high load impedance should be connected.
The de-embedding result is showed in figures below.

Figure 3: Two-port S-parameters of FET at a fixed bias point after de-embedding

Measurements of BJT:
We then took full two port S-parameters for the BJT we set the V CE = 5.0. And to get the
IC 7mA tune voltage of VBE.

Figure 4: Two-port S-parameters of BJT at a fixed bias point

It is seen that the input impedance is capacitive in nature which is consistent with the
characteristics of a BJT transistor at this frequency. We also see V BE increases the S21 also increases and becomes positive. The de-embedding result is showed in figures below.

Figure 5: Two-port S-parameters of BJT at a fixed bias point after de-embedding

OPEN and SHORT Configurations:

We measure the OPEN and SHORT configurations. Set the TX attenuator back to 0 dB.

Figure 6: Two-port S-parameters of OPEN fixture structure

Figure 7: Two-port S-parameters of SHORT fixture structure

Questions for the Report:

Following the questions asked in the manual are answered briefly.

Value of FETs Pinch-off bias Voltage:

Applying reverse bias forms a depletion region that reduces the cross section of the conducting channel, until the channel is completely depleted. The gate voltage where this obtains is the pinch off voltage. The pinch off voltage was around 4.2 V.

Input Impedance of the FET and BJT:

As seen in the smith chart of the FET and BJT the input impedances are capacitive in nature for the FET and BJT transistors. But for the FET transistor the capacitance is more as
compared to the BJT capacitance at the same frequency. This is true because the capacitance in the FET is the capacitance from the gate to the bulk, and the capacitance on the BJT
is the capacitance from the base to the emitter which is small.

Figure 8: Smith Chart S[3,3]BJT and S[1,1]FET

Input Impedance of the FET and BJT:

Transit frequency is defined as the frequency where the current gain from input to output
drops to 1.

Figure 9: Transit frequency of BJT

fT = 4.122MHz, =

= 0.342MHz

Test fixture influence on measurement:

As seen in the smith chart plot of the open measurement from figure 6 we can see that
the open has a capacitive nature, we can understand that the open act like a capacitor because the line is open, and there is a gap between the line and ground. For the short case
figure 7, we see that we have an inductive nature; this could be understood, because it
means the line is directly connected to ground and as such at high frequencies there should
be some parasitic inductance.

Parasitic Inductance and Capacitance:

From the figure value we place markers and the impedance for the inductance is

Figure 10: Parasitic inductance for short test fixture

ZL=2fL = 28.69, L =9.13nH at f= 500MHz

Same process is used for parasitic capacitance. ZC =

1
2

, C=0.10pF

10

QUCS model: S parameter for Embedded and De-embedded:

Qucs model for FET is below same is with BJT but with BJT files as input.

Figure 11: QUCS model for FET

Figure 12: Smith Chart for Embedded (Encircled) and De-embedded FET

11

Figure 13: Smith Chart for Embedded (Encircled) and De-embedded BJT

The port 1 and 2 defines before de-embedding and port 3 and 4 defines after deembedding. So, we can see that before de-embedding there was different impedance value.
After, de-embedding the value reduced to the device original value. The encircled ones are
S [1, 1] and S [2, 2].

Summary:
In this experiment we learned about test fixture and its basics, structure and components. How embedding and de-embedding effects the results. We also calculated fT , fmax.
Simulated a model based on those .s2p files through Qucs tool and discussed the difference between measured and simulated results.

References:
http://en.wikipedia.org/wiki/
http://www.microwaves101.com/encyclopedias/de-embedding-s-parameters