Design and simulation of 32 bit Floating Point ALU using Verilog

Aravinth R Balachandar V and Edwin Gerald A

Department of Electronics and Communication Engineering, BCET, Karaikal, India

Abstract
The Arithmetic Logic Unit is one of the essential component of a computer. It performs
arithmetic operations such as addition, subtraction, multiplication, division and various logical
functions. The Aim of this paper is to simulate an ALU and to analyze the various parameters
such as speed, power and number of logical blocks used by that ALU. The Floating point
numbers in this paper are represented according to the IEEE standard 754. The Arithmetic
operations such a s addition, subtraction, multiplication, division and the logical operations are
realized using Verilog HDL. Xilinx 7.1i software is used for writing the verilog codes and the
simulation is carried out with ModelSim 5.5f simulator.

1. INTRODUCTION
For the efficient way of representing real
numbers the floating point numbers are
used. It is used when there is a need of
representing a number which is very large or
very small but representation of such
numbers are cannot be done without paying
a price for it like as power, speed, accuracy,
ease of implementation and the memory of
the system.
In the various fields of science such as
physics and biology etc. the need of
measuring the dimensions of objects are
essential for analyzing its characteristics. In
physics measuring the distance between
stars or the size of an electron cannot be
done with the range of fixed numbers hence
we are in need of floating point numbers.
The Arithmetic Logic Unit is the basic
building block of a CPU which does various

arithmetic
operations
like
addition,
subtraction, multiplication and division etc.
1.1 Single Precision IEEE 754 Format
All the floating point numbers are composed
by three components:
Sign: it indicates the sign of the number (0
positive and 1 negative)
Mantissa: it sets the value of the number
Exponent: it contains the value of the base
power (biased)
If a Simple Precision format is used the bits
will be divided in that way:
The first bit (31st bit) is set the sign (S) of the
number (0 positive and 1 negative)
Next w bits (from 30th to 23rd bit) represent
the exponent (E)

The rest of the string, t, (from 22nd to 0) is

reserved to save the mantissa.

Figure 1.1 Floating point number format

Standard IEEE 754 specifies formats and
methods in order to operate with floating
point arithmetic. These methods for
computational with floating point numbers
will yield the same result regardless the
processing is done in hardware, software or
a combination for the two or the
implementation.
The standard specifies:
Formats for binary and decimal floating
point data for computation and data

interchange
Different
operations

as

addition,

subtraction,

multiplication

operations
Conversion

between

point formats and the other way around

Different properties to be satisfied when

and

other

integer-floating

Conversion of Decimal to Floating point 32

bit format is explained with an example.
Suppose the decimal number considered is
129.85. Before converting into floating
format this number is converted into binary
value which is 10000001.110111. After
conversion the radix point is moved to the
left such that there will be only one bit
towards the left of the radix point and this
bit must be 1. This bit is known as hidden
bit.
The binary value now can be
represented
as
1.00000011101110000000000.
The
number which is after the radix point is
called the mantissa which is of 23 bits and
the whole number is called significand
which is of 24 bits(including the hidden bit).
Now the number of times the radix point is
shifted (say x) is counted. In above case
there is 7 times shifting of radix point to the
left. This value must be added to 127 to get
the exponent value i.e. original exponent
value is 127 + x. Thus the exponent
becomes 127 + 7 = 134 which is 10000110.
Sign bit i.e. MSB is 0 because number is +
ve. Now the result is assembled into 32 bit
format which is sign, exponent, mantissa:
01000011000000011101110000000000.
2. LITERATURE SURVEY
In recent years, Floating-point numbers are

rounding numbers during arithmetic and

widely adopted in many applications due to

conversions
Floating point exceptions and their

its high dynamic range and good robustness

handling (NaN, or zero).

against quantization errors, capabilities.

Floating-point representation is able to
retain its resolution and accuracy.

1.2 Conversion of Decimal to Floating Point

IEEE specified standard for floating-point

provides

representation is known as IEEE 754

pipelining concept ALU execute multiple

standard. This standard specifies interchange

instructions simultaneously (Suchita Pare et.

and arithmetic formats and methods for

al, 2012) .

binary and decimal floating-point arithmetic

in computer programming environments.

high

performance.

With

3. METHODOLOGY
The entire design is implemented by the

(IEEE 754-2008)
The main objective of implementation of
floating point operation on reconfigurable

following steps in progression.

Conversion of
Number into
representation.

Conversion of the binary integer to its

IEEE754 format.

Pre-normalization of the operands

Performing the selected operation.

Post-normalize the output obtained.

Detecting and handling the exceptions

encountered.

hardware is to utilize less chip area with less

combinational delay (Karan Gumber et.al,
May 2012) which means less latency i.e.
faster speed. A parameterizable floating
point adder and multiplier implemented

the Floating Point

a novel integral

using the software-like language Handel-C,

using the Xilinx XCV1000 FPGA, a five
stages

pipelined

multiplier

achieved

28MFlops (A. Jaenicke et. Al, 2001). The

hardware needed for the parallel 32-bit
multiplier is approximately 3 times that of
serial.
A single precision floating point multiplier
that doesnt support rounding modes can be
implemented using a digit serial multiplier
(L.Louca et. al, 1996). The ALU is a
fundamental building block of the central
processing unit of a computer, and even the
simplest microprocessors contain one for
purposes such as maintaining timers. By
using pipeline with ALU design, ALU

Figure 3.1 Flow diagram of Arithmetic Logic Unit

input exponents. Three extra bits the guard

bit, the round bit, and the sticky bit are
added to both mantissas to increase the
Figure 3.2 Block diagram of adder/subtractor

accuracy

of

the

performed

operation

(addition or subtraction) and to be used in

the rounding process. Sticky bit is the
logical "Or"ing of any bits that are dropped
Figure 3.3 Block diagram of multiplier

during the pre-normalization of operand B.

Post Normalize: The resultant mantissa is
normalized after the leading one is detected
using the LOD method. The resultant

Figure 3.4 Block diagram of divider

exponent is adjusted accordingly.

Unpack: The sign, exponent and mantissa

Rounding:

of both operands are separated. A flag,

rounded using the REN technique. The final

aequalb flag, is set if both inputs are equal.

output is given in IEEE format.

The aequalb flag will be used if the effective

Adder/Subtracter: The effective operation

operation, determined in the adder/subtracter

to be performed is calculated according to

module, was subtraction to set a flag

the signs of operands A & B, the input

indicating a zero output. This prevents

operation and the swap flag. The effective

unnecessary addition/subtraction and pre

operation is performed and the zero flag is

normalization operations from taking place.

updated

Swap: Inputs are swapped if necessary such

subtraction and the aequalb flag is set.

that operand A carries the larger floating

Block Multiplier: Multiplies the two 24 bit

point number and operand B is the smaller

mantissa of operands A and B. the bottle

operand to be pre-normalized. A swap flag is

neck of the design is the 24*24 bit multiplier

set if the operands were swapped to be used

used to calculate the resulting 48 bit

in determining the effective operation in the

mantissa.

adder/subtracter module.

operating speed of the multiplier, the

Pre-normalize: The smaller mantissa, of

proposed design breaks up the 24*24 bit

operand B, is pre-normalized, that is it's

multiplication of operands A and B into nine

shifted by the difference between the two

8*8 bit multiplications where each mantissa

if

The

the

To

resultant

effective

increase

mantissa

operation

the

is

is

maximum

is sliced into three 8-bit slices such that

INPUT B:

A=A2A1A0, B=B2B1B0. Then, B0 is

00000100000001000100001100000011

multiplied in A2, A1 and A0. Each of these

RESULT:

three 8*8 bit multiplications gives a 16 bit

00001000000001100100011101000110

result. The three 16 bit results are properly

manipulated to give a 32 bit result Ro of the
24*8 bits multiplication operation (i.e.
A*B0). In a similar manner B1 and B2 are
multiplied in A2, A1 and A0 to give R1 and
R2. R1 and R2 are properly shifted to be
added to R0 thus giving the 48 bit result
mantissa. The result sign is determined
through a simple XOR operation.
Divider:

First shift left the dividend by 1.

Subtract the divisor. If the carry is 1 do

Figure 4.1 Result of Floating point addition

4.2 Subtraction
INPUT A:
00001000000001100100001100000011

not restore. If carry is 0 i.e. answer is

INPUT B:

negative then restore by adding back to

00000100000001000100001100000011

the divisor.

RESULT:

Place the carry as the LSB of the

00001000000001100011111011000000

intermediate answer.

Do this procedure up to n iterations,

where n is number of bits in the divisor.
Here n is 24 bits for single precision and
53 bit for double precision.

4. SIMULATION RESULTS
4.1 Addition
INPUT A:

00001000000001100100001100000011

Figure 4.2 Result of Floating point subtraction

4.3 Multiplication
INPUT A:
00001000000001100100001100000011
INPUT B:
00000100000001000100001100000011
RESULT:
000011000000000000110101010111110101

Figure 4.4 Result of Floating point division

0001001001000001001

Figure 4.5 FPGA Spartan 6 kit

5. CONCLUSION
Figure 4.3 Result of Floating point Multiplication

Thus the 32 bit Floating point Arithmetic

Logic Unit was designed to perform

4.4 Divider

operations

INPUT A:

multiplication and division . IEEE 754

00001000000001100100001100000011

standard based floating point representation

INPUT B:

is used. The programs are coded in Verilog

00000100000001000100001100000011

HDL.

RESULT:

Modelsim 5.5f and the programming is done

00000100000000000000000000000001

using Xilinx 7.1i.

The

like

addition,

the

simulation

is

subtraction,

done

with

Table5.1: Device Utilization Summary:

Comparison with Booth Algorithm (Radix2) Research India Publications,2013.

Number of Slice Registers

Number of Slice LUTs
Number used as Logic
Number of LUT Flip Flop pairs
used
Number with an unused Flip
Flop
Number with an unused LUT
Number of fully used LUT-FF
pairs
Number of IOs
Number of bonded IOBs

123
304
304
102

[4] Geetanjali and Nishant Tripathi, "VHDL

Implementation of 32-Bit Arithmetic Logic
Unit (ALU), International Journal of

223

Computer Science and

5416
102

Engineering,2012 .
[5] D. Jackuline moni and P. Eben Sophia,
Design of low power and high speed

100
98%

configurable booth multiplier, IEEE, 2011.

[6] Kiseon cho and Minkyu song, Design

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