Professional Documents
Culture Documents
Data Sheet
28/40/44-Pin High-Performance,
Enhanced Flash, USB Microcontrollers
with 12-Bit A/D and nanoWatt Technology
Preliminary
DS39887B
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Linear Active Thermistor, Migratable
Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The
Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the
U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select
Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,
WiperLock and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS39887B-page ii
Preliminary
PIC18F2458/2553/4458/4553
28/40/44-Pin High-Performance, Enhanced Flash, USB
Microcontrollers with 12-Bit A/D and nanoWatt Technology
Universal Serial Bus Features:
Power-Managed Modes:
Run: CPU On, Peripherals On
Idle: CPU Off, Peripherals On
Sleep: CPU Off, Peripherals Off
Idle mode Currents Down to 5.8 A Typical
Sleep mode Currents Down to 0.1 A Typical
Timer1 Oscillator: 1.1 A Typical, 32 kHz, 2V
Watchdog Timer: 2.1 A Typical
Two-Speed Oscillator Start-up
Peripheral Highlights:
Program Memory
Data Memory
12-Bit CCP/ECCP
Flash # Single-Word SRAM EEPROM I/O A/D (ch)
(PWM)
(bytes) Instructions (bytes) (bytes)
PIC18F2458
24K
12288
PIC18F2553
32K
16384
PIC18F4458
24K
12288
PIC18F4553
32K
16384
2048
Master
I2C
Timers
8/16-Bit
1/3
MSSP
SPP
24
10
2/0
No
35
13
1/1
Yes
256
Preliminary
SPI
Comp.
EUSART
DS39887B-page 1
PIC18F2458/2553/4458/4553
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC18F2458
PIC18F2553
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1
VUSB
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)/UOE
RC2/CCP1/P1A
VUSB
RD0/SPP0
RD1/SPP1
Note 1:
DS39887B-page 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC18F4458
PIC18F4553
40-Pin PDIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CCP2(1)/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
VDD
VSS
RD7/SPP7/P1D
RD6/SPP6/P1C
RD5/SPP5/P1B
RD4/SPP4
RC7/RX/DT/SDO
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
Preliminary
PIC18F2458/2553/4458/4553
1
2
3
4
5
6
7
8
9
10
11
PIC18F4458
PIC18F4553
33
32
31
30
29
28
27
26
25
24
23
NC/ICRST(2)/ICVPP(2)
RC0/T1OSO/T13CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
RC0/T1OSO/T13CKI
NC/ICCK(2)/ICPGC(2)
NC/ICDT(2)/ICPGD(2)
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(1)/VPO
12
13
14
15
16
17
18
19
20
21
22
44-Pin TQFP
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/D+/VP
RC4/D-/VM
RD3/SPP3
RD2/SPP2
RD1/SPP1
RD0/SPP0
VUSB
RC2/CCP1/P1A
RC1/T1OSI/CCP2(1)/UOE
NC/ICPORTS(2)
44
43
42
41
40
39
38
37
36
35
34
44-Pin QFN
PIC18F4458
PIC18F4553
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VSS
VDD
VDD
RE2/AN7/OESPP
RE1/AN6/CK2SPP
RE0/AN5/CK1SPP
RA5/AN4/SS/HLVDIN/C2OUT
RA4/T0CKI/C1OUT/RCV
RB3/AN9/CCP2(1)/VPO
NC
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
MCLR/VPP/RE3
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RC7/RX/DT/SDO
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
VSS
VDD
VDD
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
Note
1:
2:
Preliminary
DS39887B-page 3
PIC18F2458/2553/4458/4553
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 12-Bit Analog-to-Digital Converter (A/D) Module ....................................................................................................................... 19
3.0 Special Features of the CPU ...................................................................................................................................................... 29
4.0 Electrical Characteristics ............................................................................................................................................................ 31
5.0 Packaging Information................................................................................................................................................................ 35
Appendix A: Revision History............................................................................................................................................................... 37
Appendix B: Device Differences........................................................................................................................................................... 37
Appendix C: Migration From Mid-Range to Enhanced Devices........................................................................................................... 38
Appendix D: Migration From High-End to Enhanced Devices ............................................................................................................. 38
Index .................................................................................................................................................................................................... 39
The Microchip Web Site ....................................................................................................................................................................... 41
Customer Change Notification Service ................................................................................................................................................ 41
Customer Support ................................................................................................................................................................................ 41
Reader Response ................................................................................................................................................................................ 42
Product Identification System............................................................................................................................................................... 43
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS39887B-page 4
Preliminary
PIC18F2458/2553/4458/4553
1.0
DEVICE OVERVIEW
1.2
PIC18F4458
PIC18F2553
PIC18F4553
Note:
The PIC18F4553 family of devices offers the advantages of all PIC18 microcontrollers namely, high
computational performance at an economical price
with the addition of high-endurance, Enhanced Flash
program memory. In addition to these features, the
PIC18F4553 family introduces design enhancements
that make these microcontrollers a logical choice for
many high-performance, power sensitive applications.
1.1
2.
3.
4.
5.
Special Features
Preliminary
DS39887B-page 5
PIC18F2458/2553/4458/4553
TABLE 1-1:
DEVICE FEATURES
Features
Operating Frequency
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
DC 48 MHz
DC 48 MHz
DC 48 MHz
DC 48 MHz
24576
32768
24576
32768
Program Memory
(Instructions)
12288
16384
12288
16384
2048
2048
2048
2048
256
256
256
256
Interrupt Sources
19
19
20
20
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E)
Ports A, B, C, D, E
Ports A, B, C, D, E
Timers
Capture/Compare/PWM
Modules
Enhanced Capture/
Compare/PWM Modules
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
MSSP,
Enhanced USART
Serial Communications
Universal Serial Bus (USB)
Module
Streaming Parallel Port (SPP)
12-Bit Analog-to-Digital
Converter Module
Comparators
No
No
Yes
Yes
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
Programmable High/
Low-Voltage Detect
Yes
Yes
Yes
Yes
Programmable Brown-out
Reset
Yes
Yes
Yes
Yes
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
75 Instructions;
83 with Extended
Instruction Set
Enabled
Packages
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
40-Pin PDIP
44-Pin QFN
44-Pin TQFP
PIC18F2455
PIC18F2550
PIC18F4455
PIC18F4550
Instruction Set
DS39887B-page 6
Preliminary
PIC18F2458/2553/4458/4553
FIGURE 1-1:
Table Pointer<21>
8
inc/dec logic
PORTA
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
20
Address Latch
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(24/32 Kbytes)
STKPTR
Data Latch
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Data Latch
4
Access
Bank
12
FSR0
FSR1
FSR2
12
PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(3)/VPO
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
inc/dec
logic
Table Latch
Address
Decode
ROM Latch
IR
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
3
(2)
Internal
Oscillator
Block
OSC1
OSC2(2)
T1OSI
INTRC
Oscillator
T1OSO
8 MHz
Oscillator
Single-Supply
Programming
In-Circuit
Debugger
MCLR(1)
VDD, VSS
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
8
8
ALU<8>
8
Brown-out
Reset
Fail-Safe
Clock Monitor
PORTE
Band Gap
Reference
MCLR/VPP/RE3(1)
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
CCP1
CCP2
MSSP
EUSART
ADC
12-Bit
Note 1:
2:
3:
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(3)/UOE
RC2/CCP1
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
BITOP
8
Watchdog
Timer
USB Voltage
Regulator
VUSB
PORTC
8 x 8 Multiply
USB
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
RB3 is the alternate pin for CCP2 multiplexing.
Preliminary
DS39887B-page 7
PIC18F2458/2553/4458/4553
FIGURE 1-2:
Table Pointer<21>
Data Memory
(2 Kbytes)
PCLATU PCLATH
21
20
Address Latch
12
Data Address<12>
31 Level Stack
4
BSR
Address Latch
Program Memory
(24/32 Kbytes)
STKPTR
Data Latch
8
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS/HLVDIN/C2OUT
OSC2/CLKO/RA6
Data Latch
inc/dec logic
PORTA
12
FSR0
FSR1
FSR2
PORTB
RB0/AN12/INT0/FLT0/SDI/SDA
RB1/AN10/INT1/SCK/SCL
RB2/AN8/INT2/VMO
RB3/AN9/CCP2(4)/VPO
RB4/AN11/KBI0/CSSPP
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
4
Access
Bank
12
inc/dec
logic
Table Latch
PORTC
Address
Decode
ROM Latch
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(4)/UOE
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
IR
8
Instruction
Decode &
Control
State Machine
Control Signals
PRODH PRODL
3
VDD, VSS
(2)
OSC1
OSC2(2)
T1OSI
T1OSO
ICPGC(3)
Internal
Oscillator
Block
Power-up
Timer
INTRC
Oscillator
Oscillator
Start-up Timer
8 MHz
Oscillator
Power-on
Reset
Single-Supply
Programming
ICPGD(3)
In-Circuit
Debugger
ICPORTS(3)
MCLR(1)
BITOP
8
RD0/SPP0:RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
ALU<8>
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
ICRST(3)
PORTD
8 x 8 Multiply
PORTE
Band Gap
Reference
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
MCLR/VPP/RE3(1)
USB Voltage
Regulator
VUSB
BOR
HLVD
Data
EEPROM
Timer0
Timer1
Timer2
Timer3
Comparator
ECCP1
CCP2
MSSP
EUSART
ADC
12-Bit
Note 1:
2:
3:
4:
USB
RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.
OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
These pins are only available on 44-pin TQFP packages under certain conditions.
RB3 is the alternate pin for CCP2 multiplexing.
DS39887B-page 8
Preliminary
PIC18F2458/2553/4458/4553
TABLE 1-2:
Pin
Type
Buffer
Type
ST
P
I
ST
I
I
Analog
Analog
CLKO
RA6
I/O
TTL
Pin Name
SPDIP,
SOIC
MCLR/VPP/RE3
MCLR
VPP
RE3
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
10
Description
Preliminary
DS39887B-page 9
PIC18F2458/2553/4458/4553
TABLE 1-2:
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/CVREF
RA2
AN2
VREFCVREF
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI/C1OUT/RCV
RA4
T0CKI
C1OUT
RCV
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
RA6
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
I
ST
ST
TTL
I/O
I
I
I
O
TTL
Analog
TTL
Analog
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
DS39887B-page 10
Preliminary
PIC18F2458/2553/4458/4553
TABLE 1-2:
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
21
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
22
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
23
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
24
RB4/AN11/KBI0
RB4
AN11
KBI0
25
RB5/KBI1/PGM
RB5
KBI1
PGM
26
RB6/KBI2/PGC
RB6
KBI2
PGC
27
RB7/KBI3/PGD
RB7
KBI3
PGD
28
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
PWM Fault input (CCP1 module).
SPI data in.
I2C data I/O.
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I
O
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
I/O
I
I
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
Preliminary
DS39887B-page 11
PIC18F2458/2553/4458/4553
TABLE 1-2:
Pin Name
Pin
Number
SPDIP,
SOIC
Pin
Type
Buffer
Type
Description
11
RC1/T1OSI/CCP2/UOE
RC1
T1OSI
CCP2(2)
UOE
12
RC2/CCP1
RC2
CCP1
13
RC4/D-/VM
RC4
DVM
15
RC5/D+/VP
RC5
D+
VP
16
RC6/TX/CK
RC6
TX
CK
17
RC7/RX/DT/SDO
RC7
RX
DT
SDO
18
RE3
VUSB
14
I/O
O
I
ST
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
I/O
I/O
ST
ST
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
I
I/O
I
TTL
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
I
I/O
O
TTL
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
VSS
8, 19
VDD
20
DS39887B-page 12
Preliminary
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
MCLR/VPP/RE3
MCLR
Pin Number
Pin Buffer
PDIP QFN TQFP Type Type
1
18
18
I
ST
P
I
ST
I
I
Analog
Analog
CLKO
RA6
I/O
TTL
VPP
RE3
OSC1/CLKI
OSC1
CLKI
13
OSC2/CLKO/RA6
OSC2
14
32
33
30
31
Description
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
External clock source input. Always associated with
pin function OSC1. (See OSC2/CLKO pin.)
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO which has 1/4
the frequency of OSC1 and denotes the instruction
cycle rate.
General purpose I/O pin.
Preliminary
DS39887B-page 13
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/VREF-/
CVREF
RA2
AN2
VREFCVREF
RA3/AN3/VREF+
RA3
AN3
VREF+
RA4/T0CKI/C1OUT/
RCV
RA4
T0CKI
C1OUT
RCV
RA5/AN4/SS/
HLVDIN/C2OUT
RA5
AN4
SS
HLVDIN
C2OUT
RA6
19
20
21
22
23
24
19
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
I/O
I
I
O
TTL
Analog
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
Analog comparator reference output.
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
I/O
I
O
I
ST
ST
TTL
I/O
I
I
I
O
TTL
Analog
TTL
Analog
Digital I/O.
Analog input 4.
SPI slave select input.
High/Low-Voltage Detect input.
Comparator 2 output.
20
21
22
23
Digital I/O.
Timer0 external clock input.
Comparator 1 output.
External USB transceiver RCV input.
24
DS39887B-page 14
Preliminary
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/AN12/INT0/
FLT0/SDI/SDA
RB0
AN12
INT0
FLT0
SDI
SDA
33
RB1/AN10/INT1/SCK/
SCL
RB1
AN10
INT1
SCK
SCL
34
RB2/AN8/INT2/VMO
RB2
AN8
INT2
VMO
35
RB3/AN9/CCP2/VPO
RB3
AN9
CCP2(1)
VPO
36
RB4/AN11/KBI0/CSSPP
RB4
AN11
KBI0
CSSPP
37
RB5/KBI1/PGM
RB5
KBI1
PGM
38
RB6/KBI2/PGC
RB6
KBI2
PGC
39
RB7/KBI3/PGD
RB7
KBI3
PGD
40
10
11
12
14
15
16
17
8
I/O
I
I
I
I
I/O
TTL
Analog
ST
ST
ST
ST
Digital I/O.
Analog input 12.
External interrupt 0.
Enhanced PWM Fault input (ECCP1 module).
SPI data in.
I2C data I/O.
I/O
I
I
I/O
I/O
TTL
Analog
ST
ST
ST
Digital I/O.
Analog input 10.
External interrupt 1.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
I/O
I
I
O
TTL
Analog
ST
Digital I/O.
Analog input 8.
External interrupt 2.
External USB transceiver VMO output.
I/O
I
I/O
O
TTL
Analog
ST
Digital I/O.
Analog input 9.
Capture 2 input/Compare 2 output/PWM 2 output.
External USB transceiver VPO output.
I/O
I
I
O
TTL
Analog
TTL
Digital I/O.
Analog input 11.
Interrupt-on-change pin.
SPP chip select control output.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
I/O
I
I/O
TTL
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
10
11
14
15
16
17
Preliminary
DS39887B-page 15
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTC is a bidirectional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
15
RC1/T1OSI/CCP2/
UOE
RC1
T1OSI
CCP2(2)
UOE
16
RC2/CCP1/P1A
RC2
CCP1
P1A
17
RC4/D-/VM
RC4
DVM
23
RC5/D+/VP
RC5
D+
VP
24
RC6/TX/CK
RC6
TX
CK
25
RC7/RX/DT/SDO
RC7
RX
DT
SDO
26
34
35
36
42
43
44
32
I/O
O
I
ST
ST
I/O
I
I/O
O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture 2 input/Compare 2 output/PWM2 output.
External USB transceiver OE output.
I/O
I/O
O
ST
ST
TTL
Digital I/O.
Capture 1 input/Compare 1 output/PWM1 output.
Enhanced CCP1 PWM output, channel A.
I
I/O
I
TTL
TTL
Digital input.
USB differential minus line (input/output).
External USB transceiver VM input.
I
I/O
I
TTL
TTL
Digital input.
USB differential plus line (input/output).
External USB transceiver VP input.
I/O
O
I/O
ST
ST
Digital I/O.
EUSART asynchronous transmit.
EUSART synchronous clock (see RX/DT).
I/O
I
I/O
O
ST
ST
ST
Digital I/O.
EUSART asynchronous receive.
EUSART synchronous data (see TX/CK).
SPI data out.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
35
36
42
43
44
DS39887B-page 16
Preliminary
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTD is a bidirectional I/O port or a Streaming
Parallel Port (SPP). PORTD can be software
programmed for internal weak pull-ups on all inputs.
These pins have TTL input buffers when the SPP
module is enabled.
RD0/SPP0
RD0
SPP0
19
RD1/SPP1
RD1
SPP1
20
RD2/SPP2
RD2
SPP2
21
RD3/SPP3
RD3
SPP3
22
RD4/SPP4
RD4
SPP4
27
RD5/SPP5/P1B
RD5
SPP5
P1B
28
RD6/SPP6/P1C
RD6
SPP6
P1C
29
RD7/SPP7/P1D
RD7
SPP7
P1D
30
38
39
40
41
38
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel B.
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel C.
I/O
I/O
O
ST
TTL
Digital I/O.
Streaming Parallel Port data.
ECCP1 PWM output, channel D.
39
40
41
Preliminary
DS39887B-page 17
PIC18F2458/2553/4458/4553
TABLE 1-3:
Pin Name
Pin Number
Pin Buffer
Type
Type
PDIP QFN TQFP
Description
PORTE is a bidirectional I/O port.
RE0/AN5/CK1SPP
RE0
AN5
CK1SPP
RE1/AN6/CK2SPP
RE1
AN6
CK2SPP
RE2/AN7/OESPP
RE2
AN7
OESPP
10
27
I/O
I
O
ST
Analog
Digital I/O.
Analog input 5.
SPP clock 1 output.
I/O
I
O
ST
Analog
Digital I/O.
Analog input 6.
SPP clock 2 output.
I/O
I
O
ST
Analog
Digital I/O.
Analog input 7.
SPP output enable output.
26
27
11, 32 7, 8, 7, 28
28, 29
I/O
I/O
ST
ST
I/O
I/O
ST
ST
I
P
VSS
12,
31
VUSB
26
25
6, 30, 6, 29
31
RE3
VDD
25
18
37
37
NC/ICCK/ICPGC(3)
ICCK
ICPGC
NC/ICDT/ICPGD(3)
ICDT
ICPGD
NC/ICRST/ICVPP(3)
ICRST
ICVPP
NC/ICPORTS(3)
ICPORTS
34
NC
13
No Connect.
12
13
33
DS39887B-page 18
Preliminary
PIC18F2458/2553/4458/4553
2.0
12-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
REGISTER 2-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-2
bit 1
bit 0
Note 1:
2:
x = Bit is unknown
Preliminary
DS39887B-page 19
PIC18F2458/2553/4458/4553
REGISTER 2-2:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W(1)
R/W(1)
R/W(1)
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
PCFG3:
PCFG0
AN5(2)
AN4
AN3
AN2
AN1
AN0
bit 3-0
AN7(2)
AN8
bit 4
AN9
AN10
bit 5
AN11
Unimplemented: Read as 0
AN12
bit 7-6
0000(1)
0001
0010
0011
0100
0101
0110
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
A
D
0111(1)
1000
1001
1010
1011
1100
1101
1110
1111
A = Analog input
Note 1:
2:
x = Bit is unknown
D = Digital I/O
The Reset value of the PCFG bits depends on the value of the PBADEN Configuration bit. When
PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
AN5 through AN7 are available only on 40-pin and 44-pin devices.
DS39887B-page 20
Preliminary
PIC18F2458/2553/4458/4553
REGISTER 2-3:
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5-3
bit 2-0
Note 1:
x = Bit is unknown
If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
Preliminary
DS39887B-page 21
PIC18F2458/2553/4458/4553
The analog reference voltage is software selectable to
either the devices positive and negative supply voltage
(VDD and VSS), or the voltage level on the RA3/AN3/
VREF+ and RA2/AN2/VREF-/CVREF pins.
FIGURE 2-1:
VAIN
(Input Voltage)
0011
0010
0001
VCFG1:VCFG0
0000
VDD
Reference
Voltage
VREF+
X0
X1
1X
VREF-
0X
AN12
AN11
AN10
AN9
AN8
AN7(1)
AN6(1)
AN5(1)
AN4
AN3
AN2
AN1
AN0
VSS
Note 1:
DS39887B-page 22
Preliminary
PIC18F2458/2553/4458/4553
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
6.
7.
FIGURE 2-2:
FIGURE 2-3:
FFEh
003h
002h
001h
4095 LSB
4095.5 LSB
4094 LSB
4094.5 LSB
3 LSB
2 LSB
000h
2.5 LSB
3.
4.
FFFh
0.5 LSB
2.
1.
1 LSB
5.
1.5 LSB
Rs
VAIN
Sampling
Switch
VT = 0.6V
ANx
RIC 1k
CPIN
5 pF
VT = 0.6V
SS
RSS
CHOLD = 25 pF
ILEAKAGE
100 nA
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Sampling Switch
SS
= Sample/Hold Capacitance (from DAC)
CHOLD
RSS
= Sampling Switch Resistance
Preliminary
VDD
6V
5V
4V
3V
2V
1
2 3
4
Sampling Switch (k)
DS39887B-page 23
PIC18F2458/2553/4458/4553
2.1
CHOLD
Rs
Conversion Error
VDD
Temperature
=
=
=
=
25 pF
2.5 k
1/2 LSb
3V Rss = 4 k
85C (system max.)
ACQUISITION TIME
TAMP + TC + TCOFF
EQUATION 2-2:
VHOLD
or
TC
EQUATION 2-1:
TACQ
EQUATION 2-3:
TACQ
TAMP + TC + TCOFF
TAMP
0.2 s
TCOFF
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 s.
TC
TACQ
DS39887B-page 24
Preliminary
PIC18F2458/2553/4458/4553
2.2
2.3
Manual
acquisition
is
selected
when
ACQT2:ACQT0 = 000. When the GO/DONE bit is set,
sampling is stopped and a conversion begins. The user
is responsible for ensuring the required acquisition time
has passed between selecting the desired input
channel and setting the GO/DONE bit. This option is
also the default Reset state of the ACQT2:ACQT0 bits
and is compatible with devices that do not offer
programmable acquisition times.
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal RC Oscillator
TABLE 2-1:
Note 1:
2:
Operation
ADCS2:ADCS0
Maximum FOSC
2 TOSC
000
2.50 MHz
4 TOSC
100
5.00 MHz
8 TOSC
001
10.00 MHz
16 TOSC
101
20.00 MHz
32 TOSC
010
40.00 MHz
64 TOSC
RC(1)
110
48.00 MHz
x11
1.00 MHz(2)
Preliminary
DS39887B-page 25
PIC18F2458/2553/4458/4553
2.4
Operation in Power-Managed
Modes
2.5
DS39887B-page 26
Preliminary
2: Analog levels on any pin defined as a digital input may cause the digital input buffer
to consume current out of the devices
specification limits.
3: The PBADEN bit in Configuration
Register 3H configures PORTB pins to
reset as analog or digital pins by controlling how the PCFG3:PCFG0 bits in
ADCON1 are reset.
PIC18F2458/2553/4458/4553
2.6
A/D Conversions
Note:
2.7
FIGURE 2-4:
Discharge
TCY TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
b11
b10
b9
b8
b7
b6
b3
b4
b5
b2
b1
b0
Conversion starts
Discharge
(typically 200 ns)
FIGURE 2-5:
TAD Cycles
TACQT Cycles
1
Automatic
Acquisition
Time
2
b11
3
b10
4
b9
5
b8
6
b7
7
b6
8
b5
9
b4
10
b3
11
b2
12
b1
13
b0
TAD1
Discharge
(typically
200 ns)
Conversion starts
(Holding capacitor is disconnected)
Preliminary
DS39887B-page 27
PIC18F2458/2553/4458/4553
2.8
TABLE 2-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
(4)
INTCON
GIE/GIEH PEIE/GIEL
PIR1
SPPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
(4)
PIE1
SPPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
(4)
IPR1
SPPIP(1)
ADIP
RCIP
TXIP
SSPIP
CCP1IP
TMR2IP
TMR1IP
(4)
PIR2
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF
TMR3IF
CCP2IF
(4)
PIE2
OSCFIE
CMIE
USBIE
EEIE
BCLIE
HLVDIE
TMR3IE
CCP2IE
(4)
IPR2
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP
TMR3IP
CCP2IP
(4)
ADRESH
(4)
ADRESL
(4)
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
19
ADCON1
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
20
ADCON2
ADFM
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0
21
PORTA
RA6(2)
RA5
RA4
RA3
RA2
RA1
RA0
(4)
TRISA
PORTB
RB7
RB5
RB4
RB3
RB2
(4)
RB1
RB0
(4)
TRISB
(4)
LATB
(4)
PORTE(1)
RDPU
RE3(3)
RE2(1)
RE1(1)
RE0(1)
(4)
TRISE
TRISE2
TRISE1
TRISE0
(4)
LATE(1)
(1)
(4)
Legend: = unimplemented, read as 0. Shaded cells are not used for A/D conversion.
Note 1: These registers and/or bits are not implemented on 28-pin devices and are read as 0.
2: RA6 and its associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as 0.
3: RE3 port bit is available only as an input pin when the MCLRE Configuration bit is 0.
4: For these Reset values, see the PIC18F2455/2550/4455/4550 Data Sheet.
DS39887B-page 28
Preliminary
PIC18F2458/2553/4458/4553
3.0
Note:
3.1
Device ID Registers
TABLE 3-1:
DEVICE IDs
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx(1)
3FFFFFh
DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
xxxx xxxx(1)
Legend:
Note 1:
x = unknown, u = unchanged
See Register 3-1 and Register 3-2 for DEVID values. DEVID registers are read-only and cannot be programmed by the
user.
File Name
Preliminary
DS39887B-page 29
PIC18F2458/2553/4458/4553
REGISTER 3-1:
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
bit 7-5
bit 4-0
REGISTER 3-2:
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
bit 7
bit 0
Legend:
R = Read-only bit
P = Programmable bit
DS39887B-page 30
DEV10:DEV3
(DEVID2<7:0>)
DEV2:DEV0
(DEVID1<7:5>)
Device
0010 1010
011
PIC18F2458
0010 1010
010
PIC18F2553
0010 1010
001
PIC18F4458
0010 1010
000
PIC18F4553
Preliminary
PIC18F2458/2553/4458/4553
4.0
ELECTRICAL CHARACTERISTICS
Preliminary
DS39887B-page 31
PIC18F2458/2553/4458/4553
FIGURE 4-1:
6.0V
5.5V
Voltage
5.0V
PIC18F2458/2553/4458/4553
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
48 MHz
Frequency
FIGURE 4-2:
6.0V
5.5V
Voltage
5.0V
PIC18LF2458/2553/4458/4553
4.5V
4.2V
4.0V
3.5V
3.0V
2.5V
2.0V
40 MHz
4 MHz
48 MHz
Frequency
For 2.0V VDD < 4.2V: FMAX = (16.36 MHz/V) (VDDAPPMIN 2.0V) + 4 MHz
For 4.2V VDD: FMAX = 48 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC device in the application.
DS39887B-page 32
Preliminary
PIC18F2458/2553/4458/4553
TABLE 4-1:
Param
No.
Sym
A01
NR
Resolution
A03
EIL
A04
A06
A07
EDL
EOFF
EGN
A10
A20
Min
Typ
Max
Units
Conditions
12
bit
VREF 3.0V
VDD = 3.0V VREF 3.0V
2.0
LSB
2.0
LSB
VDD = 5.0V
+1.5/-1.0
LSB
+1.5/-1.0
LSB
VDD = 5.0V
LSB
LSB
VDD = 5.0V
1.25
LSB
2.00
LSB
VDD = 5.0V
Monotonicity
Guaranteed(1)
VDD VSS
A21
VSS + 3.0V
VDD + 0.3V
A22
VSS 0.3V
VDD 3.0V
A25
VAIN
VREFL
VREFH
A30
ZAIN
Recommended
Impedance of Analog
Voltage Source
2.5
A50
IREF
5
150
A
A
Note 1:
2:
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source.
VREFL current is from the RA2/AN2/VREF-/CVREF pin or VSS, whichever is selected as the VREFL source.
Preliminary
DS39887B-page 33
PIC18F2458/2553/4458/4553
FIGURE 4-3:
BSF ADCON0, GO
(Note 2)
131
Q4
A/D CLK
130
(1)
132
11
A/D DATA
10
...
...
NEW_DATA
OLD_DATA
ADRES
TCY
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note
1:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2:
Param
Symbol
No.
130
TAD
Min
Max
Units
PIC18FXXXX
0.8
12.5(1)
PIC18LFXXXX
1.4
25.0(1)
VDD = 3.0V;
TOSC based, VREF full range
PIC18FXXXX
A/D RC mode
VDD = 3.0V; A/D RC mode
131
TCNV
Conversion Time
(not including acquisition time)(2)
13
14
TAD
132
TACQ
Acquisition Time(3)
1.4
135
TSWC
(Note 4)
137
TDIS
Discharge Time
0.2
PIC18LFXXXX
Note 1:
2:
3:
4:
Conditions
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the New input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.
On the following cycle of the device clock.
DS39887B-page 34
Preliminary
PIC18F2458/2553/4458/4553
5.0
PACKAGING INFORMATION
Preliminary
DS39887B-page 35
PIC18F2458/2553/4458/4553
NOTES:
DS39887B-page 36
Preliminary
PIC18F2458/2553/4458/4553
APPENDIX A:
REVISION HISTORY
APPENDIX B:
DEVICE
DIFFERENCES
TABLE B-1:
DEVICE DIFFERENCES
Features
PIC18F2458
PIC18F2553
PIC18F4458
PIC18F4553
24576
32768
24576
32768
12288
16384
12288
16384
19
19
20
20
Interrupt Sources
I/O Ports
Ports A, B, C, (E)
Ports A, B, C, (E)
Capture/Compare/PWM Modules
Ports A, B, C, D, E Ports A, B, C, D, E
1
Enhanced Capture/Compare/
PWM Modules
No
No
Yes
Yes
10 Input Channels
10 Input Channels
13 Input Channels
13 Input Channels
28-Pin SPDIP
28-Pin SOIC
28-Pin SPDIP
28-Pin SOIC
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
40-Pin PDIP
44-Pin TQFP
44-Pin QFN
Packages
Preliminary
DS39887B-page 37
PIC18F2458/2553/4458/4553
APPENDIX C:
MIGRATION FROM
MID-RANGE TO
ENHANCED DEVICES
APPENDIX D:
MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
DS39887B-page 38
Preliminary
PIC18F2458/2553/4458/4553
INDEX
A
A/D ..................................................................................... 19
A/D Converter Interrupt, Configuring ......................... 23
Acquisition Requirements .......................................... 24
ADCON0 Register ...................................................... 19
ADCON1 Register ...................................................... 19
ADCON2 Register ...................................................... 19
ADRESH Register ................................................ 19, 22
ADRESL Register ...................................................... 19
Analog Port Pins, Configuring .................................... 26
Associated Registers ................................................. 28
Calculating the Minimum Required
Acquisition Time ................................................ 24
Configuring the Module .............................................. 23
Conversion Clock (TAD) ............................................. 25
Conversion Status (GO/DONE Bit) ............................ 22
Conversions ............................................................... 27
Converter Characteristics .......................................... 33
Discharge ................................................................... 27
Operation in Power-Managed Modes ........................ 26
Selecting and Configuring Acquisition Time .............. 25
Special Event Trigger (CCP) ...................................... 28
Use of the CCP2 Trigger ............................................ 28
Absolute Maximum Ratings ............................................... 31
ADCON0 Register .............................................................. 19
GO/DONE Bit ............................................................. 22
ADCON1 Register .............................................................. 19
ADCON2 Register .............................................................. 19
ADRESH Register .............................................................. 19
ADRESL Register ........................................................ 19, 22
Analog-to-Digital Converter. See A/D.
B
Block Diagrams
A/D ............................................................................. 22
Analog Input Model .................................................... 23
PIC18F2458/2553 ........................................................ 7
PIC18F4458/4553 ........................................................ 8
C
Compare (CCP Module)
Special Event Trigger ................................................. 28
Configuration Bits ............................................................... 29
Customer Change Notification Service .............................. 41
Customer Notification Service ............................................ 41
Customer Support .............................................................. 41
D
Device Differences ............................................................. 37
Device ID Registers ........................................................... 29
Device Overview .................................................................. 5
Other Special Features ................................................ 5
E
Electrical Characteristics .................................................... 31
Equations
A/D Acquisition Time .................................................. 24
A/D Minimum Charging Time ..................................... 24
Errata ................................................................................... 4
P
Packaging Information ....................................................... 35
Pin Functions
MCLR/VPP/RE3 ........................................................... 9
MCLR/VPP/RE3 ......................................................... 13
NC/ICCK/ICPGC ....................................................... 18
NC/ICDT/ICPGD ........................................................ 18
NC/ICPORTS ............................................................ 18
NC/ICRST/ICVPP ....................................................... 18
OSC1/CLKI ............................................................ 9, 13
OSC2/CLKO/RA6 .................................................. 9, 13
RA0/AN0 .............................................................. 10, 14
RA1/AN1 .............................................................. 10, 14
RA2/AN2/VREF-/CVREF ....................................... 10, 14
RA3/AN3/VREF+ .................................................. 10, 14
RA4/T0CKI/C1OUT/RCV ..................................... 10, 14
RA5/AN4/SS/HLVDIN/C2OUT ............................ 10, 14
RB0/AN12/INT0/FLT0/SDI/SDA .......................... 11, 15
RB1/AN10/INT1/SCK/SCL .................................. 11, 15
RB2/AN8/INT2/VMO ............................................ 11, 15
RB3/AN9/CCP2/VPO .......................................... 11, 15
RB4/AN11/KBI0 ......................................................... 11
RB4/AN11/KBI0/CSSPP ............................................ 15
RB5/KBI1/PGM .................................................... 11, 15
RB6/KBI2/PGC .................................................... 11, 15
RB7/KBI3/PGD .................................................... 11, 15
RC0/T1OSO/T13CKI ........................................... 12, 16
RC1/T1OSI/CCP2/UOE ....................................... 12, 16
RC2/CCP1 ................................................................. 12
RC2/CCP1/P1A ......................................................... 16
RC4/D-/VM .......................................................... 12, 16
RC5/D+/VP .......................................................... 12, 16
RC6/TX/CK .......................................................... 12, 16
RC7/RX/DT/SDO ................................................. 12, 16
RD0/SPP0 ................................................................. 17
RD1/SPP1 ................................................................. 17
RD2/SPP2 ................................................................. 17
RD3/SPP3 ................................................................. 17
RD4/SPP4 ................................................................. 17
RD5/SPP5/P1B ......................................................... 17
RD6/SPP6/P1C ......................................................... 17
RD7/SPP7/P1D ......................................................... 17
RE0/AN5/CK1SPP .................................................... 18
RE1/AN6/CK2SPP .................................................... 18
RE2/AN7/OESPP ...................................................... 18
VDD ...................................................................... 12, 18
VSS ...................................................................... 12, 18
VUSB .................................................................... 12, 18
Pinout I/O Descriptions
PIC18F2458/2553 ....................................................... 9
PIC18F4458/4553 ..................................................... 13
Power-Managed Modes
and A/D Operation ..................................................... 26
Preliminary
DS39887B-page 39
PIC18F2458/2553/4458/4553
R
Timing Diagrams
A/D Conversion .......................................................... 34
Timing Diagrams and Specifications
A/D Conversion Requirements .................................. 34
W
WWW Address .................................................................. 41
WWW, On-Line Support ...................................................... 4
S
Special Features of the CPU .............................................. 29
DS39887B-page 40
Preliminary
PIC18F2458/2553/4458/4553
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
Preliminary
DS39887B-page 41
PIC18F2458/2553/4458/4553
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Application (optional):
Would you like a reply?
Device: PIC18F2458/2553/4458/4553
Questions:
1. What are the best features of this document?
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4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS39887B-page 42
Preliminary
PIC18F2458/2553/4458/4553
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device
PIC18F2458/2553(1), PIC18F4458/4553(1),
PIC18F2458/2553T(2), PIC18F4458/4553T(2);
VDD range 4.2V to 5.5V
PIC18LF2458/2553(1), PIC18LF4458/4553(1),
PIC18LF2458/2553T(2), PIC18LF4458/4553T(2);
VDD range 2.0V to 5.5V
Temperature Range
I
E
=
=
Package
PT
SO
SP
P
ML
=
=
=
=
=
Pattern
c)
Note 1:
2:
Preliminary
DS39887B-page 43
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
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Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
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Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Fax: 43-7242-2244-393
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
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Tel: 33-1-69-53-63-20
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Tel: 81-45-471- 6166
Fax: 81-45-471-6122
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
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Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 774-760-0087
Fax: 774-760-0088
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Fax: 82-53-744-4302
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Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
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Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Fax: 86-532-8502-7205
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Tel: 65-6334-8870
Fax: 65-6334-8850
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Tel: 86-24-2334-2829
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Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
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Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
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Tel: 86-27-5980-5300
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Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
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Fax: 31-416-690340
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Tel: 34-91-708-08-90
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Tel: 44-118-921-5869
Fax: 44-118-921-5820
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Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
06/25/07
DS39887B-page 44
Preliminary