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Amplifier Distortion
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Amplifier Distortion
From the previous tutorials we learnt that for a signal amplifier to operate correctly without any distortion to
the output signal, it requires some form of DC Bias on its Base or Gate terminal so that it can amplify the
input signal over its entire cycle with the bias "Q-point" set as near to the middle of the load line as
possible. This then gave us a "Class-A" type amplification configuration with the most common
arrangement being the "Common Emitter" for Bipolar transistors and the "Common Source" for unipolar
FET transistors.
We also learnt that the Power, Voltage or Current Gain, (amplification) provided by the amplifier is the ratio
of the peak output value to its peak input value (Output Input). However, if we incorrectly design our
amplifier circuit and set the biasing Q-point at the wrong position on the load line or apply too large an
input signal to the amplifier, the resultant output signal may not be an exact reproduction of the original
input signal waveform. In other words the amplifier will suffer from distortion. Consider the common emitter
amplifier circuit below.
Common Emitter Amplifier
Distortion of the output signal waveform may take place because:

1. Amplification may not be taking place over the whole signal cycle due to incorrect biasing.
2. The input signal may be too large, causing the amplifier to be limited by the supply voltage.
3. The amplification may not be linear over the entire frequency range of inputs.
This means then that during the amplification process of the signal waveform, some form of Amplifier
Distortion has occurred.
Amplifiers are basically designed to amplify small voltage input signals into much larger output signals and
this means that the output signal is constantly changing by some factor or valu, called gain, multiplied by
the input signal for all input frequencies. We saw previously that this multiplication factor is called the
Beta, value of the transistor.
Common emitter or even common source type transistor circuits work fine for small AC input signals but
suffer from one major disadvantage, the bias Q-point of a bipolar amplifier depends on the same Beta
value which may vary from transistors of the same type, ie. the Q-point for one transistor is not necessarily
the same as the Q-point for another transistor of the same type due to the inherent manufacturing
tolerances. If this occurs the amplifier may not be linear and Amplitude Distortion will result but careful
choice of the transistor and biasing components can minimise the effect of amplifier distortion.
Amplitude Distortion
Amplitude distortion occurs when the peak values of the frequency waveform are attenuated causing
distortion due to a shift in the Q-point and amplification may not take place over the whole signal cycle.
This non-linearity of the output waveform is shown below.
Amplitude Distortion due to Incorrect Biasing
If the bias is correct the output waveform should look like that of the input waveform only bigger,
(amplified). If there is insufficient bias the output waveform will look like the one on the right with the
negative part of the output waveform "cut-off". If there is too much bias the output waveform will look like
the one on the left with the positive part "cut-off".

When the bias voltage is too small, during the negative part of the cycle the transistor does not conduct
fully so the output is set by the supply voltage. When the bias is too great the positive part of the cycle
saturates the transistor and the output drops almost to zero.
Even with the correct biasing voltage level set, it is still possible for the output waveform to become
distorted due to a large input signal being amplified by the circuits gain. The output voltage signal
becomes clipped in both the positive and negative parts of the waveform an no longer resembles a sine
wave, even when the bias is correct. This type of amplitude distortion is called Clipping and is the result
of "Over-driving" the input of the amplifier.
When the input amplitude becomes too large, the clipping becomes substantial and forces the output
waveform signal to exceed the power supply voltage rails with the peak (+ve half) and the trough (-ve half)
parts of the waveform signal becoming flattened or "Clipped-off". To avoid this the maximum value of the
input signal must be limited to a level that will prevent this clipping effect as shown above.
Amplitude Distortion due to Clipping
Amplitude Distortion greatly reduces the efficiency of an amplifier circuit. These "flat tops" of the
distorted output waveform either due to incorrect biasing or over driving the input do not contribute
anything to the strength of the output signal at the desired frequency. Having said all that, some well
known guitarist and rock bands actually prefer that their distinctive sound is highly distorted or "overdriven"
by heavily clipping the output waveform to both the +ve and -ve power supply rails. Also, excessive
amounts of clipping can also produce an output which resembles a "square wave" shape which can then
be used in electronic or digital circuits.
We have seen that with a DC signal the level of gain of the amplifier can vary with signal amplitude, but as
well as Amplitude Distortion, other types of distortion can occur with AC signals in amplifier circuits, such
as Frequency Distortion and Phase Distortion.
Frequency Distortion
Frequency Distortion occurs in a transistor amplifier when the level of amplification varies with
frequency. Many of the input signals that a practical amplifier will amplify consist of the required signal
waveform called the "Fundamental Frequency" plus a number of different frequencies called "Harmonics"
superimposed onto it. Normally, the amplitude of these harmonics are a fraction of the fundamental
amplitude and therefore have very little or no effect on the output waveform. However, the output
waveform can become distorted if these harmonic frequencies increase in amplitude with regards to the
fundamental frequency. For example, consider the waveform below:
Frequency Distortion due to Harmonics
In the example above, the input waveform consists a the fundamental frequency plus a second harmonic
signal. The resultant output waveform is shown on the right hand side. The frequency distortion occurs
when the fundamental frequency combines with the second harmonic to distort the output signal.
Harmonics are therefore multiples of the fundamental frequency and in our simple example a second
harmonic was used. Therefore, the frequency of the harmonic is 2 times the fundamental, 2 x or 2.
Then a third harmonic would be3, a fourth, 4, and so on. Frequency distortion due to harmonics is
always a possibility in amplifier circuits containing reactive elements such as capacitance or inductance.
Phase Distortion
Phase Distortion or Delay Distortion occurs in a non-linear transistor amplifier when there is a time
delay between the input signal and its appearance at the output. If we call the phase change between the
input and the output zero at the fundamental frequency, the resultant phase angle delay will be the
difference between the harmonic and the fundamental. This time delay will depend on the construction of
the amplifier and will increase progressively with frequency within the bandwidth of the amplifier. For
example, consider the waveform below:
Phase Distortion due to Delay
Any practical amplifier will have a combination of both "Frequency" and "Phase" distortion together with
amplitude distortion but in most applications such as in audio amplifiers or power amplifiers, unless the
distortion is excessive or severe it will not generally affect the operation of the system.
In the next tutorial about Amplifiers we will look at the Class A Amplifier. Class A amplifiers are the
most common type of amplifier output stage making them ideal for use in audio power amplifiers.
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Basic Electronics Tutorials by Wayne Storr. Last
Miller Capacitance Effects and Cin Analysis

The Miller effect is the apparent modification of capacitance effects by a
factor of the voltage gain between the capacitor terminals. In Figure 1, the
signal Vin will appear at Vo , VGS , Vin , AGD = -gmZL , larger and inverted. The
signal Vin will also appear as Vs , AGSVin and in phase with the input (AGS is
the source follower gain from gate to source).
AGS: RS / RS + 1/gm
The circuit obviously has Gain from the input (gate) to drain and from the
input (gate) to source. The Miller effect must be expected to cause the
capacitors CGD and CGS to have effects, do to the gain across their terminals,
that is modified by the gain.
Figure 1:
Figure 2:
To simplify the analysis, examine the Miller effect relative to CGD by

examining a grounded source circuit (Figure 2). For this circuit, the input
capacitance will be CGS plus CGD as modified by the Miller effect. Examine the
equivalent circuit of Figure 2, shown in Figure 3.
Figure 3:
Analyze the circuit for Zin which, as shown, will result in the "Z" of the total
capacitance Cin. From this it will be possible to determine the Miller Effect on
CGD.
Zin = Vin / iin iin + iGD - iGS = 0 iGS = Vin / (1/jCGS)
iGS = jCGSVin
iGD = (Vo - Vin) / (1/jCGD)

iGD = (Vo - Vin)( jCGD)
Vo = AVin, {where A = -gmZL}
iGD = (AVin - Vin) jCGD iGD = Vin(A - 1) jCGD
iGS = Vin(jCGS)
iin = iGS - iGD iin = Vin(CGS + CGD(1 - A)) j
So: Zin = Vin / iin = Vin / Vin(CGS + CGD(1 - A)) j
However, Zin is also the reactance (impedance) of Cin, the total input
capacitance made up of CGS and CGD modified by the Miller effect.
Zin = 1 / jC = 1 / (CGS + CGD(1 - A)) j
Cin = CGS + CGD(1 - A)
for the grounded source amp (A = -gmZL)
In the amp with an unbypassed source resistor: Cin = CGS(1 - AGS) + CGD(1 AGD)
Common-mode rejection ratio

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The common-mode rejection ratio (CMRR) of a differential amplifier (or other device)
is the tendency of the device to reject the input signals common to both input leads. A
high CMRR is important in applications where the signal of interest is represented by
a small voltage fluctuation superimposed on a (possibly large) voltage offset, or when
relevant information is contained in the voltage difference between two signals. (An
example is audio transmission over balanced lines.)
Contents
[hide]
1 Theory
2 Example: operational amplifiers
3 See also
4 External links
Theory [edit]
Ideally, a differential amplifier takes the voltages,
and
on its two inputs and
produces an output voltage

, where
is the differential gain.
However, the output of a real differential amplifier is better described as
where
is the common-mode gain, which is typically much smaller than the

differential gain.
The CMRR is defined as the ratio of the powers of the differential gain over the
common-mode gain, measured in positive decibels (thus using the 20 log rule):
As differential gain should exceed common-mode gain, this will be a positive number,
and the higher the better.
The CMRR is a very important specification, as it indicates how much of the commonmode signal will appear in your measurement. The value of the CMRR often depends
on signal frequency as well, and must be specified as a function thereof.
It is often important in reducing noise on transmission lines. For example, when
measuring the resistance of a thermocouple in a noisy environment, the noise from the
environment appears as an offset on both input leads, making it a common-mode
voltage signal. The CMRR of the measurement instrument determines the attenuation
applied to the offset or noise.
Example: operational amplifiers [edit]
Typical instrumentation amplifier implementation, designed to have a high CMRR.
An operational amplifier (op-amp) has two inputs, V+ and V-, and an open-loop gain G. In
the ideal case, the output of an ideal op-amp behaves according to the equation
This equation represents an infinite CMRR: if both inputs fluctuate by the same
amount (while maintaining a constant difference V+ - V-), this change will have no
bearing on the output. In real applications, this is not always the case: the lower the
CMRR, the larger the effect on the output signal, following the general equation
Where VCM represents the common-mode voltage at the inputs, or (V+ + V-)/2.
The 741, a common op-amp chip, has a CMRR of 90 dB, which is reasonable in most
cases. A value of 70 dB may be adequate for applications which are insensitive to the
effects on amplifier output;some high-end devices may use op-amps with a CMRR of
120 dB or more.
So for example, an op-amp with 90dB CMRR operating with 10V of common-mode
will have an output error of 316uV.


Contents
[hide]
1 Theory
3 See also
4 External links
Theory [edit]
and

, where
where

differential gain.

120 dB or more.


Contents
[hide]
1 Theory
3 See also
4 External links
Theory [edit]
and

, where
where
differential gain.

120 dB or more.
The Common Source JFET Amplifier
So far we have looked at the bipolar type transistor amplifier and especially the common emitter
amplifier, but small signal amplifiers can also be made using Field Effect Transistors or FET's for
short. These devices have the advantage over bipolar transistors of having an extremely high input
impedance along with a low noise output making them ideal for use in amplifier circuits that have very
small input signals.
The design of an amplifier circuit based around a junction field effect transistor or "JFET", (N-channel
FET for this tutorial) or even a metal oxide silicon FET or "MOSFET" is exactly the same principle as
that for the bipolar transistor circuit used for a Class A amplifier circuit we looked at in the previous
tutorial.
Firstly, a suitable quiescent point or "Q-point" needs to be found for the correct biasing of the JFET
amplifier circuit with single amplifier configurations of Common-source (CS), Common-drain (CD) or
Source-follower (SF) and the Common-gate (CG) available for most FET devices. These three JFET
amplifier configurations correspond to the common-emitter, emitter-follower and the common-base
configurations using bipolar transistors. In this tutorial about FET amplifiers we will look at the popular
Common Source JFET Amplifier as this is the most widely used JFET amplifier design.
Consider the Common Source JFET Amplifier circuit configuration below.
Common Source JFET Amplifier
The amplifier circuit consists of an N-channel JFET, but the device could also be an equivalent Nchannel depletion-mode MOSFET as the circuit diagram would be the same just a change in the FET,
connected in a common source configuration. The JFET gate voltage Vg is biased through the potential
divider network set up by resistors R1 and R2 and is biased to operate within its saturation region which
is equivalent to the active region of the bipolar junction transistor. Unlike a bipolar transistor circuit, the
junction FET takes virtually no input gate current allowing the gate to be treated as an open circuit. Then
no input characteristics curves are required. We can compare the JFET to the bipolar junction transistor
(BJT) in the following table.
JFET to BJT Comparison
JFET
BJT
Gate, (G)
Base, (B)
Drain, (D)
Collector, (C)
Source, (S)
Emitter, (E)
Gate Supply, (VG)
Base Supply, (VB)
Drain Supply, (VDD)
Collector Supply, (VCC)
Drain Current, (iD)
Collector Current, (iC)
Since the N-Channel JFET is a depletion mode device and is normally "ON", a negative gate voltage
with respect to the source is required to modulate or control the drain current. This negative voltage can
be provided by biasing from a separate power supply voltage or by a self biasing arrangement as long
as a steady current flows through the JFET even when there is no input signal present and Vg
maintains a reverse bias of the gate-source pn junction. In this example the biasing is provided from a
potential divider network allowing the input signal to produce a voltage fall at the gate as well as voltage
rise at the gate with a sinusoidal signal. Any suitable pair of resistor values in the correct proportions
would produce the correct biasing voltage so the DC gate biasing voltage Vg is given as:
Note that this equation only determines the ratio of the resistors R1and R2, but in order to take
advantage of the very high input impedance of the JFET as well as reducing the power dissipation within
the circuit, we need to make these resistor values as high as possible, with values in the order of 1 to
10M being common.
The input signal, (Vin) of the common source JFET amplifier is applied between the Gate terminal and
the zero volts rail, (0v). With a constant value of gate voltageVg applied the JFET operates within its
"Ohmic region" acting like a linear resistive device. The drain circuit contains the load resistor, Rd. The
output voltage, Vout is developed across this load resistance. The efficiency of the common source
JFET amplifier can be improved by the addition of a resistor, Rs included in the source lead with the
same drain current flowing through this resistor. Resistor, Rs is also used to set the JFET amplifiers "Qpoint".
When the JFET is switched fully "ON" a voltage drop equal to Rs x Idis developed across this resistor
raising the potential of the source terminal above 0v or ground level. This voltage drop across Rs due to
the drain current provides the necessary reverse biasing condition across the gate resistor, R2
effectively generating negative feedback. In order to keep the gate-source junction reverse biased, the
source voltage, Vs needs to be higher than the gate voltage, Vg. This source voltage is therefore given
as:
Then the Drain current, Id is also equal to the Source current, Is as "No Current" enters the Gate
terminal and this can be given as:
This potential divider biasing circuit improves the stability of the common source JFET amplifier circuit
when being fed from a single DC supply compared to that of a fixed voltage biasing circuit. Both resistor,
Rs and the source by-pass capacitor, Cs serve basically the same function as the emitter resistor and
capacitor in the common emitter bipolar transistor amplifier circuit, namely to provide good stability and
prevent a reduction in the loss of the voltage gain. However, the price paid for a stabilized quiescent
gate voltage is that more of the supply voltage is dropped across Rs.
The the value in farads of the source by-pass capacitor is generally fairly high above 100uF and will be
polarized. This gives the capacitor an impedance value much smaller, less than 10% of the
transconductance, gm (the transfer coefficient representing gain) value of the device. At high
frequencies the by-pass capacitor acts essentially as a short-circuit and the source will be effectively
connected directly to ground.
The basic circuit and characteristics of a Common Source JFET Amplifier are very similar to that of
the common emitter amplifier. A DC load line is constructed by joining the two points relating to the drain
current, Id and the supply voltage, Vddremembering that when Id = 0: ( Vdd = Vds ) and whenVds =
0: ( Id = Vdd/RL ). The load line is therefore the intersection of the curves at the Q-point as follows.
Common Source JFET Amplifier Characteristics Curves
As with the common emitter bipolar circuit, the DC load line for the common source JFET amplifier
produces a straight line equation whose gradient is given as: -1/(Rd + Rs) and that it crosses the
vertical Id axis at point A equal to Vdd/(Rd + Rs). The other end of the load line crosses the horizontal
axis at point B which is equal to the supply voltage, Vdd. The actual position of the Q-point on the DC
load line is generally positioned at the mid centre point of the load line (for class-A operation) and is
determined by the mean value of Vg which is biased negatively as the JFET is a depletion-mode
device. Like the bipolar common emitter amplifier the output of the Common Source JFET Amplifier is
180o out of phase with the input signal.
One of the main disadvantages of using Depletion-mode JFET is that they need to be negatively biased.
Should this bias fail for any reason the gate-source voltage may rise and become positive causing an
increase in drain current resulting in failure of the drain voltage, Vd. Also the high channel resistance,
Rds(on) of the junction FET, coupled with high quiescent steady state drain current makes these
devices run hot so additional heatsink is required. However, most of the problems associated with using
JFET's can be greatly reduced by using enhancement-mode MOSFET devices instead.
MOSFETsor Metal Oxide Semiconductor FET's have much higher input impedances and low channel
resistances compared to the equivalent JFET. Also the biasing arrangements for MOSFETs are different
and unless we bias them positively for N-channel devices and negatively for P-channel devices no drain
current will flow, then we have in effect a fail safe transistor.
JFET Amplifier Current and Power Gains

We said previously that the input current, Ig of a common source JFET amplifier is very small because
of the extremely high gate impedance, Rg. A common source JFET amplifier therefore has a very good
ratio between its input and output impedances and for any amount of output current, Io the JFET
amplifier will have very high current gain Ai. Because of this common source JFET amplifiers are
extremely valuable as impedance matching circuits or are used as voltage amplifiers. Likewise, because
power = current voltage, and output voltages are usually several millivolts or even volts, the power
gain, Ap is also very high.
In the next tutorial we will look at how the incorrect biasing of the transistor amplifier can cause
Distortion to the output signal in the form of amplitude distortion due to clipping and as well as the
effect of phase and frequency distortion.

tutorial.
JFET
BJT
Gate, (G)
Base, (B)
Drain, (D)
Collector, (C)
Source, (S)
Emitter, (E)
Gate Supply, (VG)
Base Supply, (VB)
Drain Supply, (VDD)
Drain Current, (iD)
10M being common.
as:


tutorial.
JFET
BJT
Gate, (G)
Base, (B)
Drain, (D)
Collector, (C)
Source, (S)
Emitter, (E)
Gate Supply, (VG)
Base Supply, (VB)
Drain Supply, (VDD)
Drain Current, (iD)
10M being common.
as:

Current mirror

A current mirror is a circuit designed to copy a current through one active device by
controlling the current in another active device of a circuit, keeping the output current
constant regardless of loading. The current being 'copied' can be, and sometimes is, a
varying signal current. Conceptually, an ideal current mirror is simply an ideal
inverting current amplifier that reverses the current direction as well or it is a currentcontrolled current source (CCCS). The current mirror is used to provide bias currents and
active loads to circuits.
Contents
[hide]
1 Mirror characteristics
2 Practical approximations
3 Circuit realizations of current mirrors
o 3.1 Basic idea
o 3.2 Basic BJT current mirror
3.2.1 Output resistance
3.2.2 Compliance voltage
3.2.3 Extensions and complications
o 3.3 Basic MOSFET current mirror
3.3.3 Extensions and reservations
o 3.4 Feedback assisted current mirror
o 3.5 Other current mirrors
4 Notes
5 See also
6 References
7 External links
Mirror characteristics [edit]

There are three main specifications that characterize a current mirror. The first is the
transfer ratio (in the case of a current amplifier) or the output current magnitude (in
the case of a constant current source CCS). The second is its AC output resistance,
which determines how much the output current varies with the voltage applied to the
mirror. The third specification is the minimum voltage drop across the output part of
the mirror necessary to make it work properly. This minimum voltage is dictated by
the need to keep the output transistor of the mirror in active mode. The range of
voltages where the mirror works is called the compliance range and the voltage
marking the boundary between good and bad behavior is called the compliance
voltage. There are also a number of secondary performance issues with mirrors, for
example, temperature stability.
Practical approximations [edit]

For small-signal analysis the current mirror can be approximated by its equivalent
Norton impedance .
In large-signal hand analysis, a current mirror is usually and simply approximated by
an ideal current source. However, an ideal current source is unrealistic in several
respects:
it has infinite AC impedance, while a practical mirror has finite impedance
it provides the same current regardless of voltage, that is, there are no
compliance range requirements
it has no frequency limitations, while a real mirror has limitations due to the
parasitic capacitances of the transistors
the ideal source has no sensitivity to real-world effects like noise, powersupply voltage variations and component tolerances.
Circuit realizations of current mirrors [edit]

Basic idea [edit]
A bipolar transistor can be used as the simplest current-to-current converter but its
transfer ratio would highly depend on temperature variations, tolerances, etc. To
eliminate these undesired disturbances, a current mirror is composed of two cascaded
current-to-voltage and voltage-to-current converters placed at the same conditions
and having reverse characteristics. It is not obligatory for them to be linear; the only
requirement is their characteristics to be mirrorlike (for example, in the BJT current
mirror below, they are logarithmic and exponential). Usually, two identical converters
are used but the characteristic of the first one is reversed by applying a negative
feedback. Thus a current mirror consists of two cascaded equal converters (the first reversed and the second - direct).
Figure 1: A current mirror implemented with npn bipolar transistors using a resistor to
set the reference current IREF; VCC = supply voltage
Basic BJT current mirror [edit]

If a voltage is applied to the BJT base-emitter junction as an input quantity and the
collector current is taken as an output quantity, the transistor will act as an
exponential voltage-to-current converter. By applying a negative feedback (simply
joining the base and collector) the transistor can be "reversed" and it will begin acting
as the opposite logarithmic current-to-voltage converter; now it will adjust the
"output" base-emitter voltage so as to pass the applied "input" collector current.
The simplest bipolar current mirror (shown in Figure 1) implements this idea. It
consists of two cascaded transistor stages acting accordingly as a reversed and direct
voltage-to-current converters. Transistor Q1 is connected to ground. Its collector-base
voltage is zero as shown. Consequently, the voltage drop across Q1 is VBE, that is, this
voltage is set by the diode law and Q1 is said to be diode connected. (See also EbersMoll model.) It is important to have Q1 in the circuit instead of a simple diode, because
Q1 sets VBE for transistor Q2. If Q1 and Q2 are matched, that is, have substantially the
same device properties, and if the mirror output voltage is chosen so the collectorbase voltage of Q2 is also zero, then the VBE-value set by Q1 results in an emitter
current in the matched Q2 that is the same as the emitter current in Q1. Because Q1 and
Q2 are matched, their 0-values also agree, making the mirror output current the same
as the collector current of Q1. The current delivered by the mirror for arbitrary
collector-base reverse bias VCB of the output transistor is given by (see bipolar transistor):
,
where IS = reverse saturation current or scale current, VT = thermal voltage and VA = Early
voltage. This current is related to the reference current IREF when the output transistor
VCB = 0 V by:
as found using Kirchhoff's current law at the collector node of Q1:
The reference current supplies the collector current to Q1 and the base currents to both
transistors when both transistors have zero base-collector bias, the two base
currents are equal, IB1=IB2=IB.
Parameter 0 is the transistor -value for VCB = 0 V.
Output resistance [edit]

If VCB is greater than zero in output transistor Q2, the collector current in Q2 will be
somewhat larger than for Q1 due to the Early effect. In other words, the mirror has a
finite output (or Norton) resistance given by the rO of the output transistor, namely
(see Early effect):
,
where VA = Early voltage and VCB = collector-to-base bias.
Compliance voltage [edit]

To keep the output transistor active, VCB 0 V. That means the lowest output voltage
that results in correct mirror behavior, the compliance voltage, is VOUT = VCV = VBE
under bias conditions with the output transistor at the output current level IC and with
VCB = 0 V or, inverting the I-V relation above:
where VT = thermal voltage and IS = reverse saturation current or scale current.
Extensions and complications [edit]

When Q2 has VCB > 0 V, the transistors no longer are matched. In particular, their values differ due to the Early effect, with
where VA is the Early voltage and 0 = transistor for VCB = 0 V. Besides the difference
due to the Early effect, the transistor -values will differ because the 0-values depend
on current, and the two transistors now carry different currents (see Gummel-Poon
model).
Further, Q2 may get substantially hotter than Q1 due to the associated higher power
dissipation. To maintain matching, the temperature of the transistors must be nearly
the same. In integrated circuits and transistor arrays where both transistors are on the
same die, this is easy to achieve. But if the two transistors are widely separated, the
precision of the current mirror is compromised.
Additional matched transistors can be connected to the same base and will supply the
same collector current. In other words, the right half of the circuit can be duplicated
several times with various resistor values replacing R2 on each. Note, however, that
each additional right-half transistor "steals" a bit of collector current from Q1 due to
the non-zero base currents of the right-half transistors. This will result in a small
reduction in the programmed current.
An example of a mirror with emitter degeneration to increase mirror resistance is
found in two-port networks.
For the simple mirror shown in the diagram, typical values of
match of 1% or better.
will yield a current
Figure 2: An n-channel MOSFET current mirror with a resistor to set the reference
current IREF; VDD is the supply voltage
Basic MOSFET current mirror [edit]

The basic current mirror can also be implemented using MOSFET transistors, as
shown in Figure 2. Transistor M1 is operating in the saturation or active mode, and so is
M2. In this setup, the output current IOUT is directly related to IREF, as discussed next.
The drain current of a MOSFET ID is a function of both the gate-source voltage and
the drain-to-gate voltage of the MOSFET given by ID = f (VGS, VDG), a relationship
derived from the functionality of the MOSFET device. In the case of transistor M1 of
the mirror, ID = IREF. Reference current IREF is a known current, and can be provided by
a resistor as shown, or by a "threshold-referenced" or "self-biased" current source to
ensure that it is constant, independent of voltage supply variations.[1]
Using VDG=0 for transistor M1, the drain current in M1 is ID = f (VGS,VDG=0), so we
find: f (VGS, 0) = IREF, implicitly determining the value of VGS. Thus IREF sets the value
of VGS. The circuit in the diagram forces the same VGS to apply to transistor M2. If M2
is also biased with zero VDG and provided transistors M1 and M2 have good matching
of their properties, such as channel length, width, threshold voltage etc., the
relationship IOUT = f (VGS,VDG=0 ) applies, thus setting IOUT = IREF; that is, the output
current is the same as the reference current when VDG=0 for the output transistor, and
both transistors are matched.
The drain-to-source voltage can be expressed as VDS=VDG +VGS. With this substitution,
the Shichman-Hodges model provides an approximate form for function f (VGS,VDG):[2]
where,
is a technology related constant associated with the transistor, W/L is the
width to length ratio of the transistor, VGS is the gate-source voltage, Vth is the
threshold voltage, is the channel length modulation constant, and VDS is the drain source
voltage.

Because of channel-length modulation, the mirror has a finite output (or Norton)
resistance given by the ro of the output transistor, namely (see channel length modulation):
,
where = channel-length modulation parameter and VDS = drain-to-source bias.

To keep the output transistor resistance high, VDG 0 V.[nb 1] (see Baker).[3] That means
the lowest output voltage that results in correct mirror behavior, the compliance
voltage, is VOUT = VCV = VGS for the output transistor at the output current level with
VDG = 0 V, or using the inverse of the f-function, f1:
.
For Shichman-Hodges model, f -1 is approximately a square-root function.
Extensions and reservations [edit]

A useful feature of this mirror is the linear dependence of f upon device width W, a
proportionality approximately satisfied even for models more accurate than the
Shichman-Hodges model. Thus, by adjusting the ratio of widths of the two transistors,
multiples of the reference current can be generated.
It must be recognized that the Shichman-Hodges model[4] is accurate only for rather
dated[when?] technology, although it often is used simply for convenience even today.
Any quantitative design based upon new[when?] technology uses computer models for
the devices that account for the changed current-voltage characteristics. Among the
differences that must be accounted for in an accurate design is the failure of the square
law in Vgs for voltage dependence and the very poor modeling of Vds drain voltage
dependence provided by Vds. Another failure of the equations that proves very
significant is the inaccurate dependence upon the channel length L. A significant
source of L-dependence stems from , as noted by Gray and Meyer, who also note
that usually must be taken from experimental data.[5]
Feedback assisted current mirror [edit]
Figure 3: Gain-boosted current mirror with op amp feedback to increase output

resistance
MOSFET version of gain-boosted current mirror; M1 and M2 are in active mode,

while M3 and M4 are in Ohmic mode, and act like resistors. The operational amplifier
provides feedback that maintains a high output resistance.
Figure 3 shows a mirror using negative feedback to increase output resistance. Because
of the op amp, these circuits are sometimes called gain-boosted current mirrors.
Because they have relatively low compliance voltages, they also are called wideswing current mirrors. A variety of circuits based upon this idea are in use,[6][7][8]
particularly for MOSFET mirrors because MOSFETs have rather low intrinsic output
resistance values. A MOSFET version of Figure 3 is shown in Figure 4 where
MOSFETs M3 and M4 operate in Ohmic mode to play the same role as emitter resistors
RE in Figure 3, and MOSFETs M1 and M2 operate in active mode in the same roles as
mirror transistors Q1 and Q2 in Figure 3. An explanation follows of how the circuit in
Figure 3 works.
The operational amplifier is fed the difference in voltages V1 - V2 at the top of the two
emitter-leg resistors of value RE. This difference is amplified by the op amp and fed to
the base of output transistor Q2. If the collector base reverse bias on Q2 is increased by
increasing the applied voltage VA, the current in Q2 increases, increasing V2 and
decreasing the difference V1 - V2 entering the op amp. Consequently, the base voltage
of Q2 is decreased, and VBE of Q2 decreases, counteracting the increase in output
current.
If the op amp gain Av is large, only a very small difference V1 - V2 is sufficient to
generate the needed base voltage VB for Q2, namely
Consequently, the currents in the two leg resistors are held nearly the same, and the
output current of the mirror is very nearly the same as the collector current IC1 in Q1,
which in turn is set by the reference current as
where 1 for transistor Q1 and 2 for Q2 differ due to the Early effect if the reverse bias
across the collector-base of Q2 is non-zero.
Figure 5: Small-signal circuit to determine output resistance of mirror; transistor Q2 is

replaced with its hybrid-pi model; a test current IX at the output generates a voltage VX,
and the output resistance is Rout = VX / IX.

An idealized treatment of output resistance is given in the footnote.[nb 2] A small-signal
analysis for an op amp with finite gain Av but otherwise ideal is based upon Figure 5
(, rO and r refer to Q2). To arrive at Figure 5, notice that the positive input of the op
amp in Figure 3 is at AC ground, so the voltage input to the op amp is simply the AC
emitter voltage Ve applied to its negative input, resulting in a voltage output of Av Ve.
Using Ohm's law across the input resistance r determines the small-signal base current
Ib as:
Combining this result with Ohm's law for RE, Ve can be eliminated, to find:[nb 3]
Kirchhoff's voltage law
from the test source IX to the ground of RE provides:
Substituting for Ib and collecting terms the output resistance Rout is found to be:
For a large gain Av >> r / RE the maximum output resistance obtained with this
circuit is
a substantial improvement over the basic mirror where Rout = rO.

The small-signal analysis of the MOSFET circuit of Figure 4 is obtained from the
bipolar analysis by setting = gm r in the formula for Rout and then letting r .
The result is
This time, RE is the resistance of the source-leg MOSFETs M3, M4. Unlike Figure 3,
however, as Av is increased (holding RE fixed in value), Rout continues to increase, and
does not approach a limiting value at large Av.

For Figure 3, a large op amp gain achieves the maximum Rout with only a small RE. A
low value for RE means V2 also is small, allowing a low compliance voltage for this
mirror, only a voltage V2 larger than the compliance voltage of the simple bipolar
mirror. For this reason this type of mirror also is called a wide-swing current mirror,
because it allows the output voltage to swing low compared to other types of mirror
that achieve a large Rout only at the expense of large compliance voltages.
With the MOSFET circuit of Figure 4, like the circuit in Figure 3, the larger the op
amp gain Av, the smaller RE can be made at a given Rout, and the lower the compliance
voltage of the mirror.
Other current mirrors [edit]

There are many sophisticated current mirrors that have higher output resistances than the
basic mirror (more closely approach an ideal mirror with current output independent
of output voltage) and produce currents less sensitive to temperature and device
parameter variations and to circuit voltage fluctuations. These multi-transistor mirror
circuits are used both with bipolar and MOS transistors. These circuits include:
the Widlar current source

the Wilson current source
the Cascoded current sources
Notes [edit]
1. ^ Keeping the output resistance high means more than keeping the MOSFET in
active mode, because the output resistance of real MOSFETs only begins to increase
on entry into the active region, then rising to become close to maximum value only
when VDG 0 V.
2. ^ An idealized version of the argument in the text, valid for infinite op amp gain, is as
follows. If the op amp is replaced by a nullor, voltage V2 = V1, so the currents in the
leg resistors are held at the same value. That means the emitter currents of the
transistors are the same. If the VCB of Q2 increases, so does the output transistor
because of the Early effect: = 0 ( 1 + VCB / VA ). Consequently the base current to
Q2 given by IB = IE / ( + 1) decreases and the output current Iout = IE / (1 + 1 / )
increases slightly because increases slightly. Doing the math,
where the transistor output resistance is given by r O = ( VA + VCB ) / Iout. That is, the
ideal mirror resistance for the circuit using an ideal op amp nullor is Rout = ( + 1 ) rO,
in agreement with the value given later in the text when the gain .
3. ^ Notice that as Av , Ve 0 and Ib IX.
Differential amplifier
Differential amplifier symbol

The inverting and non-inverting inputs are distinguished by "" and "+" symbols
(respectively) placed in the amplifier triangle. Vs+ and Vs are the power supply
voltages; they are often omitted from the diagram for simplicity, but of course must be
present in the actual circuit.
A differential amplifier is a type of electronic amplifier that amplifies the difference
between two voltages but does not amplify the particular voltages.
Contents
[hide]
1 Theory
2 Long-tailed pair
2.1 Historical background

2.2 Configurations
2.2.1 Differential output
2.2.2 Single-ended output
o 2.3 Operation
2.3.1 Biasing
2.3.2 Common mode
2.3.3 Differential mode
2.3.3.1 Single-ended input
o 2.4 Improvements
2.4.1 Emitter constant current source
2.4.2 Collector current mirror
o 2.5 Interfacing considerations
2.5.1 Floating input source
2.5.2 Input/output impedance
2.5.3 Input/output range
3 Other differential amplifiers
4 Applications
5 Footnotes
6 See also
7 References
8 External links
o
o
Theory [edit]
Many electronic devices use differential amplifiers internally. The output of an ideal
differential amplifier is given by:
Where
and
are the input voltages and
In practice, however, the gain is not quite equal for the two inputs. This means, for
instance, that if
and
are equal, the output will not be zero, as it would be in the
ideal case. A more realistic expression for the output of a differential amplifier thus
includes a second term.
is called the common-mode gain of the amplifier.

As differential amplifiers are often used to null out noise or bias-voltages that appear
at both inputs, a low common-mode gain is usually desired.
The common-mode rejection ratio (CMRR), usually defined as the ratio between
differential-mode gain and common-mode gain, indicates the ability of the amplifier
to accurately cancel voltages that are common to both inputs. The common-mode
rejection ratio is defined as:
In a perfectly symmetrical differential amplifier,

is zero and the CMRR is infinite.
Note that a differential amplifier is a more general form of amplifier than one with a
single input; by grounding one input of a differential amplifier, a single-ended
amplifier results.
Long-tailed pair [edit]

Historical background [edit]
The long-tailed pair was originally implemented using a pair of vacuum tubes. The
circuit works the same way for all three-terminal devices with current gain. The longtail resistor circuit bias points are largely determined by Ohm's Law and less so by
active component characteristics.
The long-tailed pair was developed from earlier knowledge of push-pull circuit
techniques and measurement bridges.[1] The earliest circuit that is truly recognizable as
a long-tailed pair in its conventional form is given by Matthews (1934)[2] and the same
circuit form appears in a patent submitted by Alan Blumlein in 1936.[3] By the end of the
1930s the topology was well established and had been described by various authors
including Offner (1937),[4] Schmitt (1937)[5] and Toennies (1938) and It was particularly
used for detection and measurement of physiological impulses.[6]
The long-tailed pair was very successfully used in early British computing, most
notably the Pilot ACE Model and descendants,[nb 1] Wilkes' EDSAC, and probably others
designed by people who worked with Blumlein or his peers. The long-tailed pair has
many attributes as a switch: largely immune to tube (transistor) variations (of great
importance when machines contained 1,000 or more tubes), high gain, gain stability,
high input impedance, medium/low output impedance, good clipper (with not-toolong tail), non-inverting (EDSAC contained no inverters!) and large output voltage
swings. One disadvantage is that the output voltage swing (typically 1020 V) was
imposed upon a high DC voltage (200 V or so), requiring care in signal coupling,
usually some form of wide-band DC coupling. Many computers of this time tried to
avoid this problem by using only AC-coupled pulse logic, which made them very
large and overly complex (ENIAC: 18,000 tubes for a 20 digit calculator) or unreliable.
DC-coupled circuitry became the norm after the first generation of vacuum tube
computers.
Configurations [edit]
A differential (long-tailed,[nb 2] emitter-coupled) pair amplifier consists of two
amplifying stages with common (emitter, source or cathode) degeneration.
Differential output [edit]
Figure 2: A classic long-tailed pair

With two inputs and two outputs, this forms a differential amplifier stage (Fig. 2). The
two bases (or grids or gates) are inputs which are differentially amplified (subtracted
and multiplied) by the pair; they can be fed with a differential (balanced) input signal,
or one input could be grounded to form a phase splitter circuit. An amplifier with
differential output can drive floating load or another stage with differential input.
Single-ended output [edit]

If the differential output is not desired, then only one output can be used (taken from
just one of the collectors (or anodes or drains), disregarding the other output without a
collector inductor; this configuration is referred to as single-ended output. The gain is
half that of the stage with differential output. To avoid sacrificing gain, a differential
to single-ended converter can be utilized. This is often implemented as a current
mirror (Fig. 3).
Operation [edit]
To explain the circuit operation, four particular modes are isolated below although, in
practice, some of them act simultaneously and their effects are superimposed.
Biasing [edit]
In contrast with classic amplifying stages that are biased from the side of the base
(and so they are highly -dependent), the differential pair is directly biased from the
side of the emitters by sinking/injecting the total quiescent current. The series
negative feedback (the emitter degeneration) makes the transistors act as voltage
stabilizers; it forces them to adjust their VBE voltages (base currents) to pass the
quiescent current through their collector-emitter junctions.[nb 3] So, due to the negative
feedback, the quiescent current depends slightly on the transistor's .
The biasing base currents needed to evoke the quiescent collector currents usually
come from the ground, pass through the input sources and enter the bases. So, the
sources have to be galvanic (DC) to ensure paths for the biasing currents and low
resistive enough to not create significant voltage drops across them. Otherwise,
additional DC elements should be connected between the bases and the ground (or the
positive power supply).
Common mode [edit]

At common mode (the two input voltages change in the same directions), the two
voltage (emitter) followers cooperate with each other working together on the
common high-resistive emitter load (the "long tail"). They all together increase or
decrease the voltage of the common emitter point (figuratively speaking, they together
"pull up" or "pull down" it so that it moves). In addition, the dynamic load "helps"
them by changing its instant ohmic resistance in the same direction as the input
voltages (it increases when the voltage increases and vice versa.) thus keeping up
constant total resistance between the two supply rails. There is a full (100%) negative
feedback; the two input base voltages and the emitter voltage change simultaneously
while the collector currents and the total current do not change. As a result, the output
collector voltages do not change as well.
Differential mode [edit]

Normal. At differential mode (the two input voltages change in opposite directions),
the two voltage (emitter) followers oppose each other - while one of them tries to
increase the voltage of the common emitter point, the other tries to decrease it
(figuratively speaking, one of them "pulls up" the common point while the other
"pulls down" it so that it stays immovable) and v.v. So, the common point does not
change its voltage; it behaves like a virtual ground with a magnitude determined by the
common-mode input voltages. The high-resistive emitter element does not play any
role since it is shunted by the other low-resistive emitter follower. There is no
negative feedback since the emitter voltage does not change at all when the input base
voltages change. he common quiescent current vigorously steers between the two
transistors and the output collector voltages vigorously change. The two transistors
mutually ground their emitters; so, although they are common-collector stages, they
actually act as common-emitter stages with maximum gain. Bias stability and
independence from variations in device parameters can be improved by negative
feedback introduced via cathode/emitter resistors with relatively small resistances.
Overdriven. If the input differential voltage changes significantly (more than about a
hundred millivolts), the base-emitter junction of the transistor driven by the lower
input voltage becomes backward biased and its collector voltage reaches the positive
supply rail. The other transistor (driven by the higher input voltage) saturates and its
collector voltage begins following the input one. This mode is used in differential
switches and ECL gates.
Breakdown. If the input voltage continues increasing and exceeds the base-emitter
breakdown voltage, the base-emitter junction of the transistor driven by the lower input
voltage breaks down. If the input sources are low resistive, an unlimited current will
flow directly through the "diode bridge" between the two input sources and will
damage them.
At common mode, the emitter voltage follows the input voltage variations; there is a
full negative feedback and the gain is minimum. At differential mode, the emitter
voltage is fixed (equal to the instant common input voltage); there is no negative
feedback and the gain is maximum.
Single-ended input [edit]

The differential pair can be used as an amplifier with a single-ended input if one of
the inputs is grounded or fixed to a reference voltage (usually, the other collector is
used as a single-ended output) This arrangement can be thought as of cascaded
common-collector and common-base stages or as a buffered common-base stage.[nb 4]
The emitter-coupled amplifier is compensated for temperature drifts, VBE is cancelled,
and the Miller effect and transistor saturation are avoided. That is why it is used to form
emitter-coupled amplifiers (avoiding Miller effect), phase splitter circuits (obtaining two
inverse voltages), ECL gates and switches (avoiding transistor saturation), etc.
Improvements [edit]
Emitter constant current source [edit]
Figure 3: An improved long-tailed pair with current-mirror load and constant-current

biasing
The quiescent current has to be constant to ensure constant collector voltages at
common mode. This requirement is not so important in the case of a differential
output since the two collector voltages will vary simultaneously but their difference
(the output voltage) will not vary; only the output range will decrease. But in the case
of a single-ended output, it is extremely important to keep a constant current since the
output collector voltage will vary. Thus the higher the resistance of the current source
, the lower
is, and the better the CMRR. The constant current needed can be
produced by connecting an element (resistor) with very high resistance between the
shared emitter node and the supply rail (negative for NPN and positive for PNP
transistors) but this will require high supply voltage. That is why, in more
sophisticated designs, an element with high differential (dynamic) resistance
approximating a constant current source/sink is substituted for the long tail (Fig. 3). It is
usually implemented by a current mirror because of its high compliance voltage (small
voltage drop across the output transistor).
The same arrangement is widely used in cascode circuits as well. It can be generalized
by an equivalent circuit consisting of a constant current source loaded by two
connected in parallel voltage sources with equal voltages. The current source
determines the common current flowing through the voltage sources while the voltage
sources fix the voltage across the current source. The emitter current source is usually
implemented as a common-emitter transistor stage with constant base voltage driving
with current the two common-base transistor stages. So, this arrangement can be
considered as a cascode consisting of cascaded common-emitter and common-base
stages.
Collector current mirror [edit]

The collector resistors can be replaced by a current mirror, whose output part acts as
an active load (Fig. 3). Thus the differential collector current signal is converted to a
single ended voltage signal without the intrinsic 50% losses and the gain is extremely
increased. This is achieved by copying the input collector current from the right to the
left side where the magnitudes of the two input signals add. For this purpose, the input
of the current mirror is connected to the right output and the output of the current
mirror is connected to the left output of the differential amplifier.
The current mirror inverts the right collector current and tries to pass it through the
left transistor that produces the left collector current. In the middle point between the
two left transistors, the two signal currents (current changes) are subtracted. In this
case (differential input signal), they are equal and opposite. Thus, the difference is
twice the individual signal currents (I - (-I) = 2I) and the differential to single
ended conversion is completed without gain losses.
Interfacing considerations [edit]
Floating input source [edit]

It is possible to connect a floating source between the two bases, but it is necessary to
ensure paths for the biasing base currents. In the case of galvanic source, only one
resistor has to be connected between one of the bases and the ground. The biasing
current will enter directly this base and indirectly (through the input source) the other
one. If the source is capacitive, two resistors have to be connected between the two
bases and the ground to ensure different paths for the base currents.
Input/output impedance [edit]

The input impedance of the differential pair highly depends on the input mode. At
common mode, the two parts behave as common-collector stages with high emitter
loads; so, the input impedances are extremely high. At differential mode, they behave
as common-emitter stages with grounded emitters; so, the input impedances are low.
The output impedance of the differential pair is high (especially for the improved
differential pair from Fig. 3).
Input/output range [edit]

The common-mode input voltage can vary between the two supply rails but cannot
closely reach them since some voltage drops (minimum 1 volt) have to remain across
the output transistors of the two current mirrors.
Other differential amplifiers [edit]
Figure 4: Op-amp differential amplifier

An operational amplifier, or op-amp, is a differential amplifier with very high
differential-mode gain, very high input impedances, and a low output impedance. By
applying negative feedback, an op-amp differential amplifier (Fig. 4) with predictable
and stable gain can be built.[nb 5] Some kinds of differential amplifier usually include
several simpler differential amplifiers. For example, an instrumentation amplifier, a fully
differential amplifier, an instrument amplifier, or an isolation amplifier are often built from
several op-amps.
Applications [edit]
Differential amplifiers are found in many circuits that utilize series negative feedback
(op-amp follower, non-inverting amplifier, etc.), where one input is used for the input
signal, the other for the feedback signal (usually implemented by operational amplifiers).
For comparison, the old-fashioned inverting single-ended op-amps from the early
1940s could realize only parallel negative feedback by connecting additional resistor
networks (an op-amp inverting amplifier is the most popular example). A common
application is for the control of motors or servos, as well as for signal amplification
applications. In discrete electronics, a common arrangement for implementing a
differential amplifier is the long-tailed pair, which is also usually found as the
differential element in most op-amp integrated circuits. A long-tailed pair can be used as
an analog multiplier with the differential voltage as one input and the biasing current
as another.
A differential amplifier is used as the input stage emitter coupled logic gates and as
switch. When used as a switch, the "left" base/grid is used as signal input and the
"right" base/grid is grounded; output is taken from the right collector/plate. When the
input is zero or negative, the output is close to zero (but can be not saturated); when
the input is positive, the output is most-positive, dynamic operation being the same as
the amplifier use described above.
Footnotes [edit]
1.
2.
3.
4.
5.
^ Details of the long-tailed pair circuitry used in early computing can be

found in "Alan Turing's Automatic Computing Engine" (Oxford University Press,
2005, ISBN 0-19-856593-3) in Part IV, 'ELECTRONICS'
^ Long-tail is a figurative name of high resistance that represents the high
emitter resistance at common mode with a common long tail with a proportional
length (at differential mode this tail shortens up to zero). If additional emitter resistors
with small resistances are included between the emitters and the common node (to
introduce a small negative feedback at differential mode), they can be figuratively
represented by short tails.
^ It is interesting fact that the negative feedback as though has reversed the
transistor behavior - the collector current has become an input quantity while the base
current serves as an output one.
^ More generally, this arrangement can be considered as two interacting
voltage followers with negative feedback: the output part of the differential pair acts
as a voltage follower with constant input voltage (a voltage stabilizer) producing
constant output voltage; the input part acts as a voltage follower with varying input
voltage trying to change the steady output voltage of the stabilizer. The stabilizer
reacts to this intervention by changing its output quantity (current, respectively
voltage) that serves as a circuit output.
^ It seems strange that, in this arrangement, a high-gain differential amplifier
(op-amp) is used as a component to build a low-gain differential amplifier like a highgain inverting amplifier (op-amp) serves as a component in a low-gain inverting
amplifier; but just this paradox of negative feedback amplifiers impeded Harold
Black in obtaining his patent.
This is a current mirror, a device that uses the current in one half of the circuit to control
the current flow in the other half. The current is the same in both halves. The switch
on the left changes the current flow in the left half, which is mirrored in the right half.
The switch on the right causes the resistor to be bypassed, but the current mirror
ensures that the flow of current does not change.
Q1's emitter-base junction acts like a diode. The current through it is set by the
resistor network below it. Wiring the base to the collector ensures that the base current
can flow, so the transistor can stay in the active mode. Since Q1's base is wired to
Q2's, they are at the same voltage, so Q2's emitter-base junction must have the same
amount of current flowing through it. (It acts like a diode, so the current is determined
by the voltage across it.)
Both halves of the circuit have nearly the same current flowing through them. The
only difference is that the base currents from Q1 and Q2 flow through the left half,
and not the right half. We use high-beta transistors in this circuit to make these base
currents as small as possible.
Miller effect

In electronics, the Miller effect accounts for the increase in the equivalent input
capacitance of an inverting voltage amplifier due to amplification of the effect of
capacitance between the input and output terminals. The virtually increased input
capacitance due to the Miller effect is given by
where
is the gain of the amplifier and C is the feedback capacitance.
Although the term Miller effect normally refers to capacitance, any impedance
connected between the input and another node exhibiting gain can modify the
amplifier input impedance via this effect. These properties of the Miller effect are
generalized in the Miller theorem.
Contents
[hide]
1 History
2 Derivation
3 Effects
o 3.1 Mitigation
4 Impact on frequency response
o 4.1 Miller approximation
5 References and notes
6 See also
History [edit]
The Miller effect was named after John Milton Miller.[1] When Miller published his work
in 1920, he was working on vacuum tube triodes; however, the same theory applies to
more modern devices such as bipolar and MOS transistors.
Derivation [edit]
An ideal voltage inverting amplifier with an impedance connecting output to input.

Consider an ideal inverting voltage amplifier of gain
with an impedance
connected between its input and output nodes. The output voltage is therefore
. Assuming that the amplifier input draws no current, all of the input
current flows through , and is therefore given by
.
The input impedance of the circuit is
If Z represents a capacitor with impedance

is
, the resulting input impedance
Thus the effective or Miller capacitance CM is the physical C multiplied by the factor
.[2]
Effects [edit]
As most amplifiers are inverting (
as defined above is positive), the effective
capacitance at their inputs is increased due to the Miller effect. This can reduce the
bandwidth of the amplifier, restricting its range of operation to lower frequencies. The
tiny junction and stray capacitances between the base and collector terminals of a
Darlington transistor, for example, may be drastically increased by the Miller effects due
to its high gain, lowering the high frequency response of the device.
It is also important to note that the Miller capacitance is the capacitance seen looking
into the input. If looking for all of the RC time constants (poles) it is important to include
as well the capacitance seen by the output. The capacitance on the output is often
neglected since it sees
and amplifier outputs are typically low
impedance. However if the amplifier has a high impedance output, such as if a gain
stage is also the output stage, then this RC can have a significant impact on the
performance of the amplifier. This is when pole splitting techniques are used.
The Miller effect may also be exploited to synthesize larger capacitors from smaller
ones. One such example is in the stabilization of feedback amplifiers, where the required
capacitance may be too large to practically include in the circuit. This may be
particularly important in the design of integrated circuit, where capacitors can consume
significant area, increasing costs.
Mitigation [edit]
The Miller effect may be undesired in many cases, and approaches may be sought to
lower its impact. Several such techniques are used in the design of amplifiers.
A current buffer stage may be added at the output to lower the gain
between the
input and output terminals of the amplifier (though not necessarily the overall gain).
For example, a common base may be used as a current buffer at the output of a common
emitter stage, forming a cascode. This will typically reduce the Miller effect and
increase the bandwidth of the amplifier.
Alternatively, a voltage buffer may be used before the amplifier input, reducing the
effective source impedance seen by the input terminals. This lowers the
time
constant of the circuit and typically increases the bandwidth.
Impact on frequency response [edit]
Figure 2: Amplifier with feedback capacitor CC.

Figure 2A shows an example of Figure 1 where the impedance coupling the input to
the output is the coupling capacitor CC. A Thvenin voltage source VA drives the circuit
with Thvenin resistance RA. The output impedance of the amplifier is considered low
enough that the relationship Vo= AvVi is presumed to hold. At the output ZL serves as
the load. (The load is irrelevant to this discussion: it just provides a path for the
current to leave the circuit.) In Figure 2A, the coupling capacitor delivers a current
jCC(Vi Vo) to the output node.
Figure 2B shows a circuit electrically identical to Figure 2A using Miller's theorem.
The coupling capacitor is replaced on the input side of the circuit by the Miller
capacitance CM, which draws the same current from the driver as the coupling
capacitor in Figure 2A. Therefore, the driver sees exactly the same loading in both
circuits. On the output side, a capacitor CMo = (1 + 1/Av)CC draws the same current
from the output as does the coupling capacitor in Figure 2A.
In order that the Miller capacitance draw the same current in Figure 2B as the
coupling capacitor in Figure 2A, the Miller transformation is used to relate CM to CC.
In this example, this transformation is equivalent to setting the currents equal, that is
or, rearranging this equation
This result is the same as CM of the Derivation Section.

The present example with Av frequency independent shows the implications of the
Miller effect, and therefore of CC, upon the frequency response of this circuit, and is
typical of the impact of the Miller effect (see, for example, common source). If CC = 0 F,
the output voltage of the circuit is simply Av vA, independent of frequency. However,
when CC is not zero, Figure 2B shows the large Miller capacitance appears at the input
of the circuit. The voltage output of the circuit now becomes
and rolls off with frequency once frequency is high enough that CMRA 1. It is a
low-pass filter. In analog amplifiers this curtailment of frequency response is a major
implication of the Miller effect. In this example, the frequency 3dB such that 3dB
CMRA = 1 marks the end of the low-frequency response region and sets the bandwidth or
cutoff frequency of the amplifier.
It is important to notice that the effect of CM upon the amplifier bandwidth is greatly
reduced for low impedance drivers (CM RA is small if RA is small). Consequently, one
way to minimize the Miller effect upon bandwidth is to use a low-impedance driver,
for example, by interposing a voltage follower stage between the driver and the
amplifier, which reduces the apparent driver impedance seen by the amplifier.
The output voltage of this simple circuit is always Av vi. However, real amplifiers have
output resistance. If the amplifier output resistance is included in the analysis, the
output voltage exhibits a more complex frequency response and the impact of the
frequency-dependent current source on the output side must be taken into account.[3]
Ordinarily these effects show up only at frequencies much higher than the roll-off due
to the Miller capacitance, so the analysis presented here is adequate to determine the
useful frequency range of an amplifier dominated by the Miller effect.
Miller approximation [edit]

This example also assumes Av is frequency independent, but more generally there is
frequency dependence of the amplifier contained implicitly in Av. Such frequency
dependence of Av also makes the Miller capacitance frequency dependent, so
interpretation of CM as a capacitance becomes more difficult. However, ordinarily any
frequency dependence of Av arises only at frequencies much higher than the roll-off
with frequency caused by the Miller effect, so for frequencies up to the Miller-effect
roll-off of the gain, Av is accurately approximated by its low-frequency value.
Determination of CM using Av at low frequencies is the so-called Miller
approximation.[2] With the Miller approximation, CM becomes frequency
independent, and its interpretation as a capacitance at low frequencies is secure.
The Phase Shift Network

This circuit uses the property of RC filters to cause a phase shift, and by using
multiple filters, a feedback circuit with exactly 180 phase shift can be
produced. When used with a common emitter amplifier, which also has a phase
shift of 180 between base and collector, the filters produce positive feedback
to cause oscillation to take place. The RC network commonly used is that of a
high pass filter, (Fig. 3.1.1) which produces a phase shift of between 0 and
90 depending on the frequency of the signal used, although low pass filters
can also be used.
Fig. 3.1.2 Three Cascaded High Pass Filters

If a number of identical filters are used in cascade, with the output of one filter
feeding the input of the next, as shown in Fig. 3.1.2 a total phase shift of
exactly 180 will be produced at one particular frequency. Usually three filters
are used with each filter producing a phase shift of 60 at the required
frequency.
As any single high pass filter can produce a phase change of up to 90, it
would seem that, in theory, only two such networks, would be needed.
However, using two filters with each producing a 90phase shift would mean
that, as the phase graph in Fig. 3.1.1 shows, the phase response curve is quite
flat at and above 90, so any drift in frequency would have little effect on the
180 phase shift produced. This would mean that if the frequency of the
oscillator changes, due to a change in temperature for example, there would be
hardly any change in the amount of phase shift, so frequency stability would be
poor. It can be seen from Fig. 3.1.1 that at 60 or 45 the phase response
curve is much steeper, and so with three filters producing 60 each, or four
filters providing 45 each, to make up the required 180, frequency stability will
be much better.
Using multiple filters in this way does create other problems however. The
frequency of oscillation can be worked out by a fairly simple formula,
Fig. 3.1.3 Loading Effect

But because this formula is based on calculations for individual filters, it does
not fully take into account the effect of connecting the filters in cascade, which
causes of one filter to be 'loaded' by the input impedance of the next, as shown
in Fig.3.1.3, where the input impedance of filter 2, made up of the reactance
(XC) of C2 and the resistance of R2 effectively changes the value of the output
resistor of filter 1 (R1) as they are effectively connected in parallel with it.
Changing the output impedance of the filters in this way causes the frequency
at which the filter produces the required phase shift to change, so altering the
oscillator frequency. The more filters that are cascaded the worse the effect
becomes, also making it more complex to accurately calculate the frequency of
the phase shift oscillator.
In addition to the loading effect caused by the cascaded filters, the input
impedance of the amplifier also contributes to the overall loading on the phase
shift network. This loading caused by the amplifier can be minimised however,
by ensuring that the amplifier has as high an input impedance as possible, for
example using an op-amp instead of a BJT amplifier.
Due to the loading effect caused by the use of multiple filters and the added
complexity of an additional filter, the four-filter 45 phase shift model is seldom
used, even though using four filters does give slightly better frequency stability.
Also the poor frequency stability of the two-filter model makes the three-filter
oscillator the most usual choice.
RC Phase Shift Oscillator Using a Bipolar Transistor
Fig. 3.1.4 BJT Phase Shift Oscillator

The circuit shown in Fig. 3.1.4 uses three high pass filters (C3/R4, C2/R3 and
C1/R2) to produce 180 phase shift. A sine wave of approximately 3Vpp with
minimum distortion is produced across the load resistor R5. The frequency of
oscillation is given by:
In several tested practical examples of this circuit, the actual frequency

produced was within 7% of the calculated value.
The basic BJT phase shift oscillator is a useful as a source of low frequency
sine waves but does have a number of drawbacks:
There can be quite a wide difference between the calculated frequency value
and the actual frequency produced.
The waveform amplitude is generally not well stabilised so a good wave shape
is not guaranteed without additional circuitry.
They are difficult to design in variable frequency form as this would involve
ganging together either 3 variable capacitors or 3 large variable resistors, and
such components are not readily available.
Buffered Phase Shift Oscillator
Fig. 3.1.5 Op Amp Buffered Phase Shift Oscillator

An improvement on the standard BJT version of the phase shift oscillator is
obtained by using op amp buffers to reduce the loading on the phase shift filter
circuits.
The circuit shown in Fig. 3.1.5, based on a design in the excellent Op Amps
for Everyone Design Reference from Texas Instruments, uses one section
(IC1a) of a quad Op Amp package for an amplifier with a gain of just over 8 (R2
R1) to replace the 1/8 losses in the three filters.
IC1 b and c provide non-inverting buffers (each with a gain of 1) so that the
filters R3/C1 and R4/C2 are loaded only by the extremely high impedance of
the op amp input. While the output of the circuit could be taken from the
junction of R5/C3, this point has a high impedance and is therefore not able to
drive any low impedance load.
Fig. 3.1.6 Comparison of 60 Frequencies in

High & Low Pass Filters
However the fourth section of the quad op amp (IC1d), is not required as part
of the oscillator, and can therefore be used as a no extra cost output buffer
amplifier, providing a low impedance output. This enables the oscillator to
easily drive other circuits or such devices as a small loudspeaker.
Notice that this design uses low pass, rather than the high pass filters that are
common in BJT phase shift oscillator designs.
Because the 60 phase shift point in a low pass filter occurs at a different
frequency to that in a high pass filter (see Fig. 3.1.6) the frequency of
oscillation is higher, around 2.76kHz with low pass filters compared with about
690Hz when high pass filters are used. Fig. 3.1.6 also shows that the gain of
an individual filter (high or low pass) is -6dB, which is equivalent to 0.5 in
voltage gain, which (being less than 1) is a loss. Therefore the three low pass
filters in Fig. 3.1.5 will contribute a total loss of 0.5 x 0.5 x 0.5 = 0.125 or 1/8th,
meaning that for a closed loop gain of 1 the amplifier will need a gain of 8.
To make sure the oscillator starts up however, a slightly higher gain is needed,
so the gain of IC1a is set by R1 and R2 as 1M/120k = 8.33. This is
considerably lower than the gain of 29 required for the BJT version in Fig.3.1.4.
In Fig. 3.1.5 there is virtually no loading of the filter circuits, due to the
presence of the op amp buffers. Because the frequency of oscillation of the
buffered amplifier shown in Fig. 5 is higher than that in Fig.3.1.4, due to its use
of low pass filters, the frequency of oscillation for Fig. 3.1.4 and Fig. 3.1.5 must
be calculated differently.
Although both oscillators use the same values for R and C (10K & 10nF), the
BJT version shown in Fig. 3.1.4 has its frequency is calculated as:
However, because the op amp version in Fig. 3.1.5 uses low pass filters, a
change in formula is needed:
Fig. 3.1.7 Buffered Phase Shift

Oscillator on Breadboard
The loading effect, or lack of it can also affect the frequency, changing the
actual frequency of a practical phase shift oscillator from the calculated value,
theoretically by as much as 25% in BJT circuits.
However, when the two oscillators described here were tested, the error
between the calculated and actual frequency in both cases was less than 7%;
within the error range expected due to component tolerances, this is another
problem that is greater with phase shift oscillators than LC oscillators, due to
the increased number of components (three RC pairs controlling the frequency
instead of just one LC pair in LC oscillators).

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Amplifier Distortion

Common Emitter Amplifier

Distortion of the output signal waveform may take place because:

Amplitude Distortion due to Incorrect Biasing

the one on the left with the positive part "cut-off".

Amplitude Distortion due to Clipping

as Frequency Distortion and Phase Distortion.

Frequency Distortion due to Harmonics

example, consider the waveform below:

Phase Distortion due to Delay

Basic Electronics Tutorials by Wayne Storr. Last

Miller Capacitance Effects and Cin Analysis

To simplify the analysis, examine the Miller effect relative to CGD by

iGD = (Vo - Vin) / (1/jCGD)

Common-mode rejection ratio

Jump to: navigation, search

on its two inputs and

produces an output voltage

is the common-mode gain, which is typically much smaller than the

Example: operational amplifiers [edit]

Typical instrumentation amplifier implementation, designed to have a high CMRR.

Common-mode rejection ratio

Jump to: navigation, search

Ideally, a differential amplifier takes the voltages,

on its two inputs and

produces an output voltage

is the common-mode gain, which is typically much smaller than the

Example: operational amplifiers [edit]

Typical instrumentation amplifier implementation, designed to have a high CMRR.

Common-mode rejection ratio

Jump to: navigation, search

on its two inputs and

produces an output voltage

is the common-mode gain, which is typically much smaller than the

Example: operational amplifiers [edit]

Typical instrumentation amplifier implementation, designed to have a high CMRR.

Common Source JFET Amplifier

JFET to BJT Comparison

Gate Supply, (VG)

Base Supply, (VB)

Drain Supply, (VDD)

Collector Supply, (VCC)

Drain Current, (iD)

Collector Current, (iC)

JFET Amplifier Current and Power Gains

The Common Source JFET Amplifier

Common Source JFET Amplifier

JFET to BJT Comparison

Gate Supply, (VG)

Base Supply, (VB)

Drain Supply, (VDD)

Collector Supply, (VCC)

Drain Current, (iD)

Collector Current, (iC)

JFET Amplifier Current and Power Gains

The Common Source JFET Amplifier

Common Source JFET Amplifier

JFET to BJT Comparison

Gate Supply, (VG)

Base Supply, (VB)

Drain Supply, (VDD)

Collector Supply, (VCC)

Drain Current, (iD)