2011 International Symposium on Electronic System Design

Delay Testable Enhanced Scan Flip-Flop: DFT for

High Fault Coverage
Vivek Shrivastava Member IEEE,
Department of Electrical Engineering,
School of Engineering,
Gautam Buddha University, Greater Noida, India
E-mail: shvivek@gbu.ac.in

Ashok Kumar Suhag,

Department of Electrical Engineering,
School of Engineering,
Gautam Buddha University, Greater Noida, India
E-mail: ashok@gbu.ac.in,

AbstractThe Scan based testing is used for delay testing in

high coverage delay testing solutions to detect such

defective parts are urgently hunted by the industry.
Scan-based delay testing, which can significantly enhance
the controllability and observability of internal signals in
SOCs and appears as most promising approach for the
delay testing of large SOCs. Scan based architectures
provide an effective way to test for delay faults with good
fault coverage. Scan-based structural delay testing not only
helps in detection of faults but also diagnosis these and
thats why it is a most famous approach for delay fault
testing. Structural scan based delay testing is being carried
out as a low expenditure replacement for functional timing
tests. Scan test includes the use of two test vectors <V1,
V2> through the scan chain mechanism. The first vector V1,
which is used to initialize the internal values of logic to
circuit under test (CUT), is first scanned into the scan chain
by using the slow scan clock. After that the second vector
V2 is used to launch transitions at the inputs of the
combinational component of the circuit. These transitions
transmit to the output of the logic block and then captured
back in the scan chain by a high-speed capture clock pulse,
equivalent to a suitable launch to capture window which
reflects the required frequency for operation. Lastly the
captured response in the scan chain is scanned out of the
CUT and matched with the correct test response. Due to
structural limitations of scan cannot permits all <V1, V2>
combinations which can be applied through scan delay test.
By the mechanism through which vector V2 is generated
according to that scan delay tests are classified as Launchon-Shift (LoS) [1, 2], or Launch-on-Capture (LoC) [3, 4].
For the Launch-on-Shift test, the V2 vector is restricted to a
one-bit shift from V1. For the Launch-on-Capture test, V2 is
the response of the CUT to vector V1. Due to these
restrictions on vector V2 usually limits the transition delay
fault (TDF) [5] coverage which can be achieved using scan
delay tests. For obtaining the very high TDF coverage is
needed for detection of small delay defects which requires
higher flexibility in choosing vector V2 and this flexibility
is provided by enhanced scan chain based testing.
The rest of paper is organized as follows. In section III
we reviewed the enhanced scan based transition delay testing

sequential circuits and in general it is implemented by using

launch-on-capture (LoC) delay tests. Launch-on-shift (LoS)
delay tests are usually more efficient to obtain high fault
coverage with appreciably lesser number of test vectors, but it
requires a fast scan enable, which is not supported by majority
of designs. The architecture of scan design limits the two
pattern delay tests that can be applied to circuit under test
which results in degradation of delay test coverage. The use of
enhanced scan flip-flops can improve this problem by
facilitating arbitrary delay test vector pairs, at the cost of high
area overhead and also requires fast hold signal. This paper
presents a new enhanced scan methodology implemented with
the slow hold signal. Experimental results on ISCAS89
benchmark circuit shows improvement in TDF fault coverage
for this methodology.

Keywords-enhanced scan; transition delay test; fault coverage

I.

INTRODUCTION

elay defects are major source of timing related failures

which is emerging as a severe issue in nanometer regime.

The main sources of timing defects can consist of resistive
opens and shorts, via voids, and gate oxide failures. These
defects are all commonly identified in aggressively scaled
technologies. Moreover, many small delay defects that are
not traced by traditional test flows can become larger with
the time under the operational stress which may lead to
infant failure. Conventional stuck-at tests are unable to
verify the functionality of manufactured ICs due to the
inability of stuck-at fault model to assess the circuit timing.
Conventional functional at-speed tests bear intolerable test
development costs, especially when the size of the design is
in the millions of gates. In addition to that in SOC (Systemon-Chip) designs, limited access of internal cores for test
makes at-speed functional tests unfeasible and burn-in stress
testing to screen out these defects is usually costly, low cost

978-0-7695-4570-7/11 $26.00 2011 IEEE

DOI 10.1109/ISED.2011.25

129

which facilitates arbitrary vector V2. In section IV new delay

testable enhanced scan flip-flop is discussed. We discussed
the experimental results for ISCAS89 benchmark circuits
using our DTESFF approach in section V and section VI
concludes the paper.
II.

ENHANCED SCAN BASED TRANSITION DELAY TESTING

The enhanced scan method was launched to deal with the

issue of low delay test coverage by eliminating the
limitations on the V2 vector and it facilitates arbitrary <V1,
V2> combinations for high coverage delay testing. In general
enhanced scan schemes, one extra redundant flip flop is
attached with each of the functional flip flops in the design
which doubles the size of the scan chain, as shown in Figure
1. The V1 and V2 vectors can now be concurrently scanned
in and loaded into the scan chain, in a random fashion. At the
initial phase of the test, bits of the V1 vector are located in
the functional flip flops, while bits of the V2 vector located
in the respective redundant flip-flop followed by each
functional flip-flop. Delay test is implemented in the LoS
(launch-on-shift) mode, with the bits in the redundant flipflops, which can now be chosen at random without any
constraints, forming V2.
The cost of doubling all the flip-flops in the design may
be very high, a number of alternate enhanced scan
techniques have been recommended to save some extra
hardware costs. In one of design uses an extra hold latch
(with an extra control signal) at the output of each scan flipflop. The thought behind is to hold the V1 initialization
pattern in these latches while a random vector V2 is being
shifted inside the scan chain [6]. Once the V2 vector is
shifted inside, test may be launched by the deactivation of
hold control signal to make the latches transparent, therefore
switching the inputs to the combinational logic from V1 to
V2. An obvious drawback of the alternate enhanced scan
design is the additional delays introduced on the signal paths
and the another disadvantage in the case of enhanced scan
design is similar to the problem that exists in Skew-load
testing that is of fast scan enable signal, here we need fast
hold signal to hold the data in latch and then transfer it to the
circuit. [7].
The graphical waveform shown in figure 2 explains the
timing associated to hold the vector V2. Hold signal is kept
high when V1 is shifted from scan flip-flop to hold latch and
kept low when V2 is inserted in the scan chain to hold the
vector V1. After insertion of test vectors hold control logic
makes the latch transparent to conduct the test, so there is a
requirement of fast hold signal to load the test vectors.
This requires that accomplishment of hold signal for
delay testing be routed as a timing critical signal similar to
clock signal but this is very expensive and not supported in
enhance scan design. Thats why delay testing mostly makes
use of LoC testing which has low test coverage.

Figure1.Classical Enhanced Scan with alternating regular and scan Flipflops[23].

V1

V2

Clock

Hold Signal

Figure 2. Waveform for Hold signal during delay test

However recent interest in achieving high delay test

coverage from scan based tests has revived interest in such
schemes [11 15]. There has been a large number of
investigations to create alternative delay fault testing
strategies with reduced DFT overhead and acceptable
coverage [20 - 23]. However, these techniques are either not
as efficient as enhanced scan method with respect to fault
coverage or required number of test patterns, or they
complicate the test generation/application considerably.
Most promising is enhanced scan approach that offer a
strategy for high TDF fault coverage at the cost of the area
overhead. In this paper we present a new Delay Testable

130

control signal only goes low after the clock goes high,
forcing the AND gate output low. Thus, while the hold
control signal switches asynchronously from high to low at
the end of the scan shift cycle, which loads V1 into the hold
latch, the actual timed control signal sent to the hold latch by
the hold alignment block switches synchronously after the
next active clock edge.

Enhanced Scan Flip-flop (DTESFF) that supports LoC test

without the need of fast hold signal. DTESFF requires only
extra AOI gate beyond the traditional enhanced scan flipflop.
III.

DELAY TESTABLE ENHANCED SCAN FLIP-FLOP

V1

The basic structure of our Delay Testable Enhanced Scan

Flip-flop (DTESFF) is shown in figure 3. It has equivalent
pin outs compared to enhanced scan flip-flop thats why it is
fully compatible from a design perspective.

Clock

As shown below in figure 3 hold alignment logic can be

realized using only a single AOI gate. This simple hold
alignment logic translates the incoming slow hold signal into
a properly timed signal that makes the hold latch transition in
a timely manner during the holding and propagating the
vectors to support the enhanced scan design. As in Figure 4
that a high hold signal directly forces the (timed) control
input of the hold latch to be high through the OR gate,
consistent with the scan shift mode. This is shown in the
timing diagram given in figure 4.
D I/P

Slow Hold Signal

AOI Gate Controlled Hold Signal

Figure 4. Timing Diagram of Delay Testable Enhanced Scan Flip-flop

(DTESFF) using Slow Hold signal

This result in an additional shift operation in the hold

latch, which launches the vector V2 and after that response is
checked precisely as required for an Enhanced scan test.

0
Scan I/P

D- Flip-flop

V2

Hold Latch

Scan enable
Clock

IV.

RESULT AND DISCUSSION

Hold Signal

In order to study the effectiveness DTESFF

methodology, we developed a simulation based ATPG
program to generate transition delay fault (TDF) test patterns
to evaluate the effectiveness of the proposed designs on the
ISCAS89 benchmark circuits, First of all the scan flip-flops
are replaced by DTESFF in the scan chains. For test
generation, a netlist for the DTESFF circuits was generated
by replacing SFFs with DTESFFs in the netlist of the
equivalent full SFF scan circuit generated by the Synopsys
DFT Compiler tool. Scan based TDF tests were generated
for DTESFF designs for the LoC test modes shown in Table
1 using Synopsys TetraMax tools. To generate tests in the
LoC mode for our DTESFF design, the ATPG was run for
LoC test generation.
The delay testable enhanced scan flip-flop design of
Figure 3 support LoC testing with improved TDF coverage
along with the slow hold signal. The DTESFF design
provides high transition delay fault coverage approaching
98.91% for ISCAS89 benchmark circuits at the cost of high
area overhead.

Figure 3. Delay Testable Enhanced Scan flipflop (DTESFF)

During the first part of the scan-in cycle, both the hold and
the timed hold latch control signals are high. Notice,
however, that when the hold is switched low (to logic 0),
the AOI controlled hold latch signal does not respond
immediately; instead it remains latched high while the clock
is low.
From Figure 4 it can be seen that this is because of
feedback from this initial high value, along with the high
inverted clock signal, generates a high (logic 1) at the AND
gate output, which propagates through the OR gate, keeping
the OR output latched high. This high timed hold latch

131

TABLE I.

SIMULATION RESULTS ON ISCAS 89 BENCHMARK CIRCUITS

expensive, loosely comparable in cost to an extra clock

signal. In this paper we implement the enhanced scan design
with the slow hold signal by adding a minimal amount of
logic (AOI gate) in each hold latch to align to the clock edge
that is a low cost solution. Our design is much effective
when compared in terms of fault coverage. High TDF
coverage approximately 98.91% is achieved on the ISCAS89
benchmark circuits.

Transition Delay Fault Coverage (in %)

Circuits

99.72%
98.91%
100%
99.35%
98.81%
98.54%
98.29%
98.24%
99.03%
99.38%
98.54%
98.67%
98.87%
98.70%
99.62%
98.21%
98.57%
99.14%
98.67%
99.38%
99.24%
99.14%
98.23%
98.82%
98.13%
99.53%

S208
S298
S344
S349
S382
S386
S400
S420
S444
S510
S526
S526n
S641

S713
S820
S832
S953
S1196
S1238
S1423
S1488
S1494
S5378
S9234
S13207
S15850

It can be therefore concluded that the DTESFF based designfor-test methodology offers a promising and cost effective
solution to achieving high TDF coverage in a scan based
delay testing environment at the cost of high area overhead.
This can make it viable to use low cost partial enhanced scan
along with the slow hold signal designs discussed in this
paper, particularly in applications where low area overhead
requirement is essential at the cost of fault coverage. Optimal
selection of DTESFF in partial enhance scan design for
significant delay test coverage with lower area overhead
remains an open question and is the subject of our ongoing
research.
VI.
[1]

[2]
[3]
[4]

[5]

V.

CONCLUSION
[6]

The difficulty of applying good quality functional timing

tests to system on chips has significantly enhanced the
understanding in scan-based delay testing. Majority of
designs recognize the scan enable as a slow speed global
control signal, and can therefore only employ launch-oncapture (LoC) delay tests. LoC delay test display relatively
modest delay fault coverage. Launch-on shift (LoS) tests are
generally more effective, achieving higher fault coverage
with significantly fewer test vectors, but require a fast scan
enable.
The architectural limitations of traditional scan restrict
the two pattern delay tests that can be applied to a design,
resulting in degraded delay test coverage. The use of
enhanced scan flip-flops can alleviate this problem by
supporting arbitrary delay test vector pairs, but at very high
area overhead. Traditional enhanced scan designs operate in
the LoS mode and therefore require control signals capable
of switching at operational clock speeds to ensure proper test
timing. Implementing high speed control signals is very

[7]

[8]

[9]

[10]

[11]

[12]

132

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