SPEAKER 1: In the last lecture, we looked at the

digital abstraction.
And we showed that this digital abstraction gave us
tremendous noise immunity over analog signal processing.
In the digital domain, we focused on two
values, 0 one 1.
And all our signals were comprised of just these two
digital values.
In this sequence today, we will look at what's inside a
digital gate, although you could go ahead and use the
digital gate abstraction without really
knowing what's inside.
And that's kind of the beauty of digital abstraction.
As EE and EECS engineers, someone has to go and build
those gates.
And so let's take a look and see what's inside those gates.
The reading for the section is chapter six of the textbook.
Let's start with a quick review.
So we looked at the digital abstraction.
And in this abstraction, we digitized values
into two, 0 and 1.
We also established the static discipline.
And this discipline, we all agreed that digital devices
would meet certain voltage thresholds.
And provided all of these devices met voltage
thresholds, it's like speaking a common language.
They could all talk to each other.
So in terms of the global context of things, recall that
we had our EECS playground.
So here is our EECS playground.
And within that playground, you have some region, which is
comprised of linear circuits.
And all of the circuits are within EECS.
So some region was linear circuits, and then we said
that there was this other region inside that we called
digital land.
And within that, we agreed to focus on just two values, 0's
and 1's, signals that comprised of
those highs and lows.
Now, within digital land, we can have sets of devices that
follow a static discipline.
So if a set of devices follow static discipline 1, then you
could think of all of those devices as being present
inside this region of the playground
within our digital domain.
And as long as all the devices within this group followed a
common set of voltage thresholds, then they would
all be able to talk to each other.
Now, a different manufacturer might go and choose a
different static discipline, static discipline 2, and a
completely different set of voltage thresholds.
So for example, for a 0, they might pick 5 volts, while in a
different part of the playground, a manufacturer
might pick a 0 to be 0 volts.
Now, both are OK, just that the two may not be able to
talk to each other.
So as long as devices within a family followed a convention,
or the static discipline, they would all be able to talk to
each other.
So in the static discipline, we have a set of voltage

thresholds.
So for example, if I have a sender, and the sender needs
to send a set of values to a receiver, then we expect the
sender to follow a rigid set of values.
So for a 1, a sender would have to send
values VOH or above.
And for a 0, the sender would have to send values
at the VOL or below.
Now, similarly on the receive side, the receiver would have
to interpret the values VIH and above as a logical 1, and
similarly, values VIL as a logical 0.
And notice that the difference between VOH and VIH
corresponded to the 1 noise margin.
So the voltage from VOH could [? droop ?] down to VIH, and
the receiver would still interpret that as a logical 1.
Now, the region between VIL and VIH is an illegal region,
and we call that the forbidden.
And it's illegal for signals to stay in there for long
periods of times, and the signals need to transition
very, very quickly as they go through the forbidden region.
So with the static discipline, I may have some gate, say, for
example, a NAND gate.
And so the outputs of the NAND gate would have to
satisfy VOH and VOL.
And similarly, on the receive side, I may have some kind of
an inverter.
And the input of the inverter would have to satisfy the
input voltage constraints.
So there again, the outputs satisfy output voltage
thresholds, and inputs would have to satisfy the input
voltage thresholds.
So these thresholds really are a specification on how we must
design our digital gates.
Continuing with the review, we looked at the combinational
gate abstraction.
And in this abstraction, we introduced
certain sets of devices.
For example, this is a NAND gate.
And in these devices are gates.
The outputs must be functions of the input alone.
So at any given point in time, I can look at the output and
uniquely determine its value by looking at the inputs at
that instant in time.
Now, this will be distinguished from other
devices such as memory devices, in which values can
be stored inside the devices.
And at any given point in time, the inputs alone do not
reflect what the output looks like.
Second, these gates must satisfy the static discipline.
So we also talked about the truth tables.
And so here is a truth table for a NAND gate.
And the truth table enumerates all of the outputs for a given
set of inputs.
So for example, if my inputs are 0, 0, the output is a 1,
and so on and so forth.
And for a NAND gate, the output is 0 when the inputs
are both 1's.
We also defined digital circuits.
And we took a set of combinational gates and
connected them with ideal wires, and

we got digital circuits.

So here is a digital circuit with three gates.
We have a NAND gate, we have an inverter, and we have
another NAND gate.
Analyzing digital circuits is pretty straightforward.
So for example, if you look at the output at this point, it
is A anded with B. And there is an inversion happening.
And similarly, for the output of the inverter, it is C bar,
because there's an inversion happening.
And then we can write down D as A do B bar.
and that is anded with C bar.
And then we take the whole thing and we put a inversion
on top of the whole thing.
So here is the three-gate digital circuit.
And I've written down the output for you.
So a lot of digital design is done with gates or higher
abstractions that are even more abstract than gates.
So if you look at a microprocessor such as a
Nehalem class chip from Intel, that, believe it or not, has
on the order of a billion gates.
OK, a lot of gates in today's design.
So it's close to a billion gates.
And they're all multicore chip, a design that CSAIL at
MIT, built by graduate and undergraduate students here,
had about three million gates.
And then if you look at the 64-core Tile processor, that
has on the order of a half billion gates.
So notice that, in these digital designs, we very
routinely bandy about numbers in the orders of billions.
We design circuits containing billions of gates.
And the reason all of these gates can function correctly
is because of the key noise immunity property, that as I
connect a bunch of these gates together, each gate is
cleaning up the input.
If I get VIH and if I have some gate, if I get VIH here
and, say, a VOL level value from some other sender
somewhere else, then incumbent upon me that if I produce a 1,
I have to produce a VOH.
And if I produce a 0, I have to produce a VOL.
And notice that VOH had tougher standards than VIH,
and VOL has tougher standards than-I'm sorry, I should have said this was VIL.
VOL has tougher standards than VIL, which I interpret as a 0.
And so VOL is the tougher output that I have to produce.
And so notice that there was a clean-up of the signals being
performed each time the signal was processed, and that really
gave it noise immunity when I have billions of circuits and
billions of gates in a system.