1.

Given the partial NMOS ROM decoder shown, having address inputs A2, A1, and A0
(A0 is LSB), identify the
decoder output (select line)
Y.
1. Y = Y0
2. Y = Y2
3. Y = Y3
4. Y = Y4
5. Y = Y5

2. Given the partial NMOS EPROM encoder shown, where Y is some select line, determine
the values of the output data lines D2D1D0
when Y = 1.
1. D2=0 D1=0 D0=0
2. D2=1 D1=0 D0=1
3. D2=1 D1=1 D0=0
4. D2=0 D1=1 D0=0
5. D2=0 D1=0 D0=1

3. Indicate the dots required to be connected (1 to 8) to implement a NOR function using the
PLD AND array shown below:
1. Dots at 3, 8
2. Dots at 2, 4, 7, 8
3. Dots at 2, 4 (only)
4. Dots at 5, 7, 1, 2
5. Dots at 5, 7 (only)

4. In general, the NEXT STATE of a sequential logic circuit is determined by the

1. MEMORY ELEMENTS
2. INPUT LOGIC BLOCK
3. OUTPUT LOGIC BLOCK
4. INPUTS only
5. OUTPUTS only

5. If a sequential circuit possesses N memory elements (binary cells or flip flops), what is
the maximum number of states could it have?
1. N
2. N^2
3. 2N
4. 2^N
5. None of these

6. Which of the following statements concerning the basic latch circuit is FALSE?
1. A latch circuit may be constructed with NOR Gates.
2. A latch is a synchronous sequential logic circuit.
3. The Q and Q' outputs of a latch can, under certain input conditions, be equal.
4. The latch is utilized in all flip-flop circuits.
5. Allowable modes of operations of the latch include the SET, RESET and NO
CHANGE modes.

7. Which of the following modifications to the sequential logic circuit (SLC) block diagram
would most likely lead to non-sequential behavior?
1. INPUT lines are disconnected, but the CLOCK line is not affected.

2. The INPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS

inputs and outputs are interfaced directly.
3. The OUTPUT LOGIC BLOCK is removed so that the MEMORY ELEMENTS
outputs are directly connected to the SLC OUTPUTLINES.
4. The feedback path between the MEMORY ELEMENTS and the INPUT LOGIC
BLOCK is opened.
5. No modification stated above would lead to nonsequential behavior.

8. In general, the PRESENT STATE of a sequential logic circuit is determined by the

1. MEMORY ELEMENTS
2. INPUT LOGIC BLOCK
3. OUTPUT LOGIC BLOCK
4. INPUTS only
5. OUTPUTS only

1. The sequential logic circuit shown represents most closely the basic
architecture of a:
1. Data-latch register
2. Ripple counter
3. Synchronous counter
4. Shift register

5. Up/Down counter

2. What are the contents of the shift register shown below (assumed initially
cleared) after the input sequence SI = 101111 is applied? (Assume 6 clock
pulses are used).
1. 0011
2. 0010
3. 1111
4. 1011
5. 1101

3. Suppose that Q1 = 0 and Q2 = 1 is the initial state of the two JK flip-flop

circuit shown. What is the state of the circuit after applying two complete
clock pulses?
1. Q1=0 Q2=0
2. Q1=0 Q2=1
3. Q1=1 Q2=0
4. Q1=1 Q2=1

4. Which of the waveforms shown below can be generated by the output QB of

the synchronous counter shown? (QA is least significant)

CLOCK _-__-__-__-__-__-__-__-__-__-__-__-__-__-__-__-__-_
QB1 __---------_________---------_________---------____
QB2 __---___---___---___---___---___---___---___---___QB3 __------------____________------------____________QB4 __------______------______------______------______QB5 __------------------------________________________-

1. QB1

2. QB2
3. QB3
4. QB4
5. QB5
5. Suppose that Q1 = 1 and Q2 = 0 is the initial state of the two JK flip-flop
circuit shown. What is the state of the circuit after applying two complete
clock pulses?
1. Q1=0 Q2=0
2. Q1=0 Q2=1
3. Q1=1 Q2=0
4. Q1=1 Q2=1

6. Which of the following represent the corrrect transient states which exist
between the two ripple counter states shown below?
(0011)
|
V
(????) transient state #1
|
V
(????) transient state #2
|
V
(0100)

1. 0001 0010
2. 0000 0010
3. 0110 0101
4. 0010 0000
5. 1000 1001
7. If QDQCQBQA = 1011 initially, what are the contents of the shift register
below after the input sequence SI = 01 is applied? (Assume 2 clock pulses are
used.)

1. 1101
2. 1001
3. 0110
4. 1110
5. 0100
8. How many transient states does a 4-bit ripple counter transit through
between count = 7 and count = 8?
1. one
2. two
3. three
4. four
5. five
9. A binary ripple counter is connected as shown (QA is least significant). Which
of the following state sequences does the counter naturally progress through?
(ignore transient states)
1. 0 to 15
2. 0 to 9
3. 0 to 6
4. 0 to 4
5. 0 to 1