Vlsi Verilog - Fir Filter Design Using Verilog

2/26/2015
VlsiVerilog:FIRFILTERDESIGNUSINGVERILOG
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FIRFILTERDESIGNUSINGVERILOG
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Verilogcode
FIRfiltersareiswidelyusedindifferentapplicationssuchas
biomedical,communicationandcontrolduetoitseasilyimplementation,stabilityandbestperformance.Itssimplicitymakesit
attractiveformanyapplicationswhereitisneedtominimizecomputationalrequirements.
Like
335peoplelikeVerilogcode.
Filtersplayanimportantroleforremovalofunwantedsignalornoisefromoriginalinputsignalbyremovingtheselected
frequenciesfromincomingsignal.Theybecamemuchpopularduetotheincreaseofthedigitalsignalprocessing.
ComparisonbetweenFIRandIIRFilters
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The non recursive (FIR) and recursive (IIR) filters have different characteristics for numbers of applications. The non
recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table 2.1
belowshowsthecomparisonbetweenFIRandIIRfilters.
IIR
MoreEfficient
FIR
LessEfficient
AnalogEquivalent
NoAnalogEquivalent
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VERILOGCODEFORFIRFILTER
//mainmoduleFIR
modulefilterfir(clk,rst,x,dataout)
input[7:0]x
inputclk,rst
output[9:0]dataout
wire[7:0]d1,d2,d3
wire[7:0]m1,m2,m3,m4,m5
wire[7:0]d11,d12,d13,d14
parameterh0=3'b101
parameterh1=3'b100
parameterh2=3'b011
parameterh3=3'b010
parameterh4=3'b001
assignm1=x>>h0
dffu2(clk,rst,x,d11)
assignm2=d11>>h1
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FIRFILTER
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VERILOG
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assignd1=m1+m2
dffu4(clk,rst,d11,d12)
assignm3=d12>>h2
assignd2=d1+m3
assignm4=d13>>h3
assignd3=d2+m4
assignm5=d14>>h4
assigndataout=d3+m5
endmodule
moduledff(clk,rst,d,q)//submoduledflipflop
inputclk,rst
input[7:0]d
output[7:0]q
reg[7:0]q
always@(posedgeclk)
begin
if(rst==1)
begin
q=0
end
else
begin
q=d
end
end
endmodule
PostedbyVlsiVerilogat22:54
Labels:FIRFILTERVERILOGCODE
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22comments:
dejwidw 29January2014at05:17
anytbfiletosimulatethis?
Reply
Replies
VlsiVerilog
29January2014at05:20
ItsasimpleTB.justsettheclockfirst.Initiallymakeresethighandthenmakeitlow.Atthesameinstantwhenreset
islowloadXvalue
Couldyouwriteitdown?ItismyfirsttimeIuseverilog)
pls,itwillhelpmealot
VlsiVerilog
29January2014at08:43
`timescale1ns/1ps
////////////////////////////////////////////////////////////////////////////////
//Company:
//Engineer:
//
//CreateDate:22:07:0001/29/2014
//DesignName:filterfir
//ModuleName:D:/fft/floating_mul/tst.v
2/5
2/26/2015
//ProjectName:floating_mul
//TargetDevice:
//Toolversions:
//Description:
//
//VerilogTestFixturecreatedbyISEformodule:filterfir
//
//Dependencies:
//
//Revision:
//Revision0.01FileCreated
//AdditionalComments:
//
////////////////////////////////////////////////////////////////////////////////
moduletst
//Inputs
regclk
regrst
reg[7:0]x
//Outputs
wire[9:0]dataout
//InstantiatetheUnitUnderTest(UUT)
filterfiruut(
.clk(clk),
.rst(rst),
.x(x),
.dataout(dataout)
)
initialbegin
//InitializeInputs
clk=0
rst=0
x=0
#100
rst=1
#100
rst=0
x=8'd5
#100
x=8'd10
#100
x=8'd12
#100
x=8'd15
#100
x=8'd16
#100
end
alwaysbegin#50clk=~clkend
endmodule
Reply
SanjayGoyal 9February2014at21:28
HelloSir.ThankyouforwritingtheFIRFiltercodeaswellastestbench.Whythedataoutis10bitwhiletheinputdataxis8bit
only.andwhataboutImpulseresponseofthesystem(h),howitwillbedeterminedandonwhichparametrsitwillldepend??
Reply
Replies
VlsiVerilog
10February2014at06:06
Hello.youcanchangethesizeofuri/paswellaso/p.hereihaveconsidered10bittakingintoconsideringthefact
that the sum can me a maximum of 1024 or below. And here we have defined the "h" as predefined constants
(weight).IsuggestyoutoworkonFIRfilterdesignonmatlabandcomparetheresultswiththexilinx.
Reply
3/5
2/26/2015
harish 14March2014at10:41
sirmymtechprojectistoimplementlowcostfirfilterusingfaithfullytruncatedmultiplierusingveriloginFPGAKIT
pleasecanyougivemesugestionsforthisproject..
Thanksregards
harish
Reply
Replies
Anonymous 5January2015at23:58
Harsh,iamdoingtheprojectthatyoudidin2014.ineedthestepstoimplementthedesign.canyouhelpme...Deepu
Reply
harish 14March2014at10:56
howwecanfindoutvariousspecificationsofFIRFILTERlikebandwidth,PassBandStopBandandhowwecanobservethe
frequencyresponseinXILINXISEtoolplshelpme....
Reply
Replies
varunkumar 19May2014at05:16
take a workspace from simulink model and attach the audio file to it...it will show the sampling freq of ur
signal.furtherucancalculatepb,cutoff
Anonymous 9January2015at01:20
type"fdtool"inmatlab
Reply
Dee 25March2014at00:48
SircanupleaseexplainhowanFIRfiltercanbeimplementedusingMACunitwhichwasdevelopedusingVedicMathematics.
Thankyou
Reply
DavidPhoon 23April2014at22:43
do you know of any iir verilog source code that I can view. had a look at myHDL but couldn't seem to get those examples
running
Reply
VinayTeja 25September2014at09:20
howtorunthiscode........??howtoverifythisasFIRfilter.......??
i'musingverilogforthe1sttimesoplshelpme..........
Reply
VinayTeja 25September2014at21:59
canuexplainhowitworks....i'mnewtoveriloghelpme..
Reply
NiteshLulla 24October2014at03:48
Thiscommenthasbeenremovedbytheauthor.
Reply
NiteshLulla 24October2014at03:52
Whysreyourightshifting'x'.Itistobemultipliedthereright?
Reply
NagarajuBathula 3November2014at20:52
SircanupleaseexplainhowanFIRfiltercanbeimplementedusingMACunitwhichwasdevelopedusingVedicMathematics.
Thankyou
4/5
2/26/2015
Reply
NagarajuBathula 3November2014at20:54
sircouldyoupleasesendmeCOMPLETECODEOF32BITMACUNITWITHAREA/POWER/TIMINGrelatedcodes
Reply
Anonymous 14November2014at01:40
ThanksalotfortheFIRcode.sircouldyoupleaseprovidethecodeforgaussianfilter
Reply
Zeby 1January2015at02:05
Hii,Cananyoneprovidemethe2DFIRfiltercodeinverilogtoobtainLL,LH,HL,HHsubbands.Theinputisanimageofsize
256x256
Reply
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