Very Low-Voltage Operation Capability of CMOS Ring Oscillators and Logic Gates

Sasan Naseh, Mehdi Kazemeini and M. Jamal Deen

McMasterUniversity, nasehs@mcmaster.ca, kazem@mcmaster.ca, jamal@mcmaster.ca

Abstract: The operation of a CMOS ring oscillator with

supply voltage values as low as ~80 mV are experimentally
investigated. The low-voltage operation of the ring oscillator based on a single inverter, is analyzed. The use of body
voltage of MOS transistors as a means for controlling the
frequency of oscillation of CMOS ring oscillators are demonstrated. The feasibility of very low-voltage operation of
logic CMOS gates such as NAND gate is confirmed with
simulation.

Keywords: Low-voltage, low-power CMOS, subthreshold, ring oscillator, VCO, substrate biasing.
1. INTRODUCTION
With the continual decrease in the dimensions of the microelectronics components, it has become possible to fabricate
integrated circuits with an increasingly larger number of
circuit building blocks. The reduction of the device dimensions also means that the speed of operation of circuits is
increased.
However, at the same time, the power consumption also
increases and new methods should be devised to reduce the
dissipated power. One solution is the decrease of power
supply voltage.
This paper presents the results of a study of the effects of
supply voltage variation on CMOS digital circuits. It is
organized as follows. In the next section the ring oscillator
circuit which was used in this work and the measurement
procedures are described. The measurement results are presented and analyzed in section 3. The result of simulation
of low-voltage operation of a 3-input NAND gate is presented in section 4. Finally in section 5 the conclusions are
given.

2. CIRCUIT DESCRIPTION AND

MEASUREMENT
The schematic of the ring-oscillator used in this work is
shown in Figure 1 (a). It is fabricated in a 0.18 m CMOS
technology and has 501 identical inverters which are connected together in series in a loop. The schematic of each
inverter is shown in Figure 1 (b). The body contacts of all
PMOSFETs in the loop are connected together and unlike
usual practice are not connected to the highest potential
VDD. This makes it possible to apply a biasing different
than VDD to the body of PMOSFETs. Similarly, body of all
NMOSFETs in the loop are connected together and left
available so that a biasing different than ground can be
applied to them. The drawn length of gates of both P and
V DD
BP
CL
BN
GND

3 STAGE
BUFFER

501 STAGES
RING OSCILLATOR
(a)

VDD

VDD
Vbp
Vin

Vout
Vbn
Gnd

(b)

Vin

Vbp
Vbn

Vout

Gnd

Figure 1. Circuits used for (a) ring-oscillator and (b)

schematic of a ring oscillator.

The choice of 501 as number of stages of the ring oscillator

was determined by simulation so that for VDD=1.8 V, the
oscillation frequency is about 32 MHz, which is low
enough so that non-expensive low-frequency packages
could be used for chip packaging. The capacitance CL
shown in Figure 1 (a) is not a real capacitor and only represents the capacitive load seen at the output of each inverter
which is comprised of the drain-substrate junction capacitance of the P and NMOSFETs in each stage, input capacitance of the next stage and the routing capacitance between
the two stages. A 3-stage buffer was connected to the oscillator output through which the output signal was measured.
The 3 stages of the buffer were made of the parallel connection of 3, 9 and 27 of the same inverters as those of the
ring oscillator, respectively. The photograph of the ring
oscillator is shown in Figure 2.
To measure the oscillation frequency of the ring oscillator a
Tektronix oscilloscope was used. To determine the current
drawn from power supply by the ring oscillator a 10
resistor was placed between VDD node of the ring oscillator
and positive pole of the power supply and the voltage
across the resistor was measured with a Keithley digital
voltmeter. A HP4145B Semiconductor Parameter Analyzer
was used to measure the VTC of a single inverter.

3. RESULTS AND DISCUSSIONS

Variations of the oscillation frequency of the ring oscillator
versus supply voltage VDD, while body of both P and N
transistors in the ring oscillator connected to their sources
are shown in Figure 3. It was observed that oscillation was
maintained for VDD values down to about 80 mV, far below
the threshold voltage of the transistors. The ability of the
circuit to oscillate down to such a low supply voltage may
be surprising, but as will be shown in the next subsections,
operation of the circuit at such low voltages can be analyzed in almost the same way as that of its operation for
supply voltages above threshold voltages. To our knowledge the operation of a digital CMOS circuit with such low
level of supply voltage has not been reported before or analyzed adequately [1].

100 m

3-stage buffer

501 inverters
in the loop

Figure 2. Photo of the ring-oscillator.

108
fosc (Hz)

NMOSFETs are 0.18 m. The gate width of NMOSFETs

was arbitrarily chosen 10 times its length, 1.8 m. The gate
width of PMOSFET was determined by simulation to be
6.1 m which would cause each inverter to have a symmetric Vin-Vout characteristics (voltage transfer characteristics,
VTC) for VDD=1.8 V. The gate oxide thickness tox is 40 .
The threshold voltage Vth0 of the P and N transistors when
their source and body are at the same potential are -0.45 V
and 0.48 V, respectively.

106
104
102
1

0.5

1
1.5
VDD (V)

Figure 3. Measured variation of oscillation frequency

versus supply voltage.

3.1 Subthreshold VTC of an inverter

The measured VTC of a single inverter identical to those of
the ring oscillator are shown in Figure 4 for different values
of supply voltage VDD. It is seen that VTCs at different values of VDD are qualitatively very similar to each other. To
analyze the VTC of an inverter at low values of VDD, the
same approach as that used for higher VDD [2] can be used.
In this approach, the inverter circuit of Figure 1 (b) is
solved graphically by plotting the Id-Vds characteristics of
both N and P transistor on the same graph and considering
that the following relations between the gate-source voltage, Vgsn and Vgsp, and the drain-source voltage, Vdsn and
Vdsp, of the of N and PMOSFET hold:
V gsn = V in

(1)

V gsp = V DD V in

(2)

V DD = V dsn V dsp

(3)

V out = V dsn

(4)

independent of Vds for higher values of Vds. These two

region of operation of a MOSFET at subthreshold, qualitatively are similar to linear and saturation region of operation of a MOSFET at strong inversion. The difference
between the Id-Vds characteristics of a MOSFET at subthreshold and strong inversion is that in subthreshold operation, the value of Vds at which the transition from linear to
saturation region occurs is independent of the gate-source
voltage Vgs.

Vout (V)

1.5
VDD =1 V

1.0

VDD =0.5 V
=0.4 V
=0.3 V
=0.2 V
=0.1 V

0.5
0

0.5

The crossing point of each of the Id-Vds curves of N and

PMOSFET in Figure 5 which are associated with the same
Vin according to equations (1) and (2), provide one point in
the VTC of the inverter. Six of such points are shown with
solid circles in Figure 5. By examining the Figure 5 it is
seen that presence of a saturation region in Id-Vds characteristics of N and PMOSFET lead to a sharp transition
region from high to low voltages in VTC of the inverter. As
supply voltage VDD is reduced, the saturation region in IdVds of transistors gradually disappear which causes the
high-to-low transition in VTC becomes smooth. The results
of measurement of VTC shown in Figure 4 also show that
for VDD=100 mV the high-to-low transition is smoother
than those with a higher values of VDD.

1.5

Vin (V)
Figure 4. Measured voltage transfer characteristics
(VTC) of a single inverter for different values of VDD.

Idd (pA)

1000

100
Vgsn=50 mV,
75 mV,
94 mV,
100 mV,
125 mV,
150 mV.

10

With the above analysis of the VTC of an inverter, it can be

seen that regardless of the value of power supply VDD and
the region of operation of transistors, as long as the inverter
has a distinct inverting characteristics, the circuit will oscillate. Decrease of VDD to very low values and smoothening
of high-to-low transition in VTC of inverters can be interpreted as drop in the voltage gain of each inverter. If the
total loop gain in the ring oscillator becomes smaller than
1, one of the Barkhausens condition for oscillation [4] is
violated and circuit stops oscillating.

1
0

50

100

150

200

Vout (mV)
Figure 5. Analysis of operation of an inverter for low
values of power supply. The values of the gate-source
voltage Vgsn are used as parameter.

An example of applying this method for the case of

VDD=0.2 V is shown in Figure 5. The solid lines are the IdVds characteristics of NMOSFET for different values of
Vgsn, and the dashed lines are Id-Vds of PMOSFETs for the
different values of Vgsp. These data are obtained using simulation of single N and PMOSFET identical to those in the
inverters with BSIM3 models which model the subthreshold operation well. Since the Vgs of both transistors are less
than threshold voltage, both transistors operate in the subthreshold region of operation where the Id-Vds relation is
given by [3]:

Id = I0 e

( V gs V th ) ( nV T )

(1 e

V ds V T

(5)

In equation (5), VT=kT/q (26 mV at room temperature) is

the thermal voltage, and I0 and n are constants. As seen
from equation (5) and also illustrated in Figure 5, for a constant value of Vgs, the transistor current Id is a strong function of Vds for low values of Vds and becomes almost

3.2 Effect of VDD on oscillation frequency of a ring

oscillator
One important aspect of the operation of the circuit which
is affected by changing supply voltage VDD is its speed, as
implied by change of the frequency of the oscillation
shown in Figure 3. The model shown in Figure 6 can be
used to study how the propagation delay in the circuit is
affected by supply voltage. During the low-to-high transition at the output, the NMOSFET is considered open and
load capacitance CL is charged by PMOSFET, as shown in
Figure 6 (a). During the high-to-low transition at the output, the PMOSFET is open and the load capacitance CL is
discharged through NMOSFET.
In strong inversion for values of Vgs>Vth, the drain current
Id (which is also the current charging and discharging the
CL) is described by the following well-known relations [5]:
I d = K ( V gs V th )

(6)

V ds
I d = 2K V gs V th -------- V ds

(7)

which equations (6) and (7) are for saturation and linear
region of operation of a MOSFET, respectively. During the
high-to-low and low-to-high transition of the output, Vgs
can be replaced by VDD and 0, respectively. Therefore it
can be seen that increase of VDD does increase charge and
discharge of CL proportional to the square of VDD, which
in turn decrease the propagation time of the inverter.
For values of VDD where transistors operate in subthreshold region, equation (5) describe the charge and discharge
of the CL. Again by replacing Vgs with VDD, it is seen that
the charge and discharge current of CL is an exponential
function of VDD. Therefore the increase in VDD does
decrease the propagation time of the inverter. Using the
above analysis, the effect of VDD on the oscillation frequency shown in Figure 3 can be explained readily. The
frequency of oscillation is a function of propagation delay
in the inverters as [1]:
1
f o = --------------------------------------N ( PHL + PLH )

V th = V th0 + (

2 F V bs

2 F )

(9)

in which Vth0 is the threshold voltage with no body bias,

is the body effect coefficient of transistor, F is the Fermi
level in the bulk of the device and Vbs is the body-source
voltage. By changing the body potential of the device, the
threshold voltage, and therefore the charge and discharge
current of CL are changed. As a result, the propagation
delay and therefore, the oscillation frequency is changed.
This effect has been experimentally verified on the ring
oscillator under test in this work and the measurement
results are shown in Figure 7 and Figure 8. In these measurements, the body biasing when the source-body diodes
of the transistors were forward biased were kept low
enough not to turn the diodes on and therefore prevent the

(8)

VDD

fosc (MHz)

30

in which PHL and PLH are high-to-low and low-to-high

propagation delay of one inverter, respectively and N is
number of inverters.
VDD

current of CL, which consequently affect the propagation

delay of the inverters. The threshold voltage of a MOSFET
can be changed by applying a potential to the body of transistor different from its source potential. The threshold
voltage of a MOSFET is [5]:

20
10

VDD=1.8 V

VDD=1.4 V

VDD=1 V

0
-1.5 -1

CL

CL

-0.5 0
0.5
Vbs (V)

Figure 7. Measured oscillation frequency as a function

of body biasing.

10+1
(b)

Figure 6. The circuit model used for explaining the

propagation delay for: (a) the low-to-high transition and
(b) the high-to-low transition of the output voltage.

3.3 Transistors Body voltage as a mean for frequency

control
Based on the timing analysis performed in the last section,
use of the body voltage of transistors in the ring oscillator
is raised as a possibility for controlling the oscillation frequency of the ring oscillator. By inspecting the relations
(5), (6) and (7), it can be seen that changing the threshold
voltage of the transistor will affect the charge and discharge

fosc (MHz)

(a)

10-1

VDD=0.6 V

10-3
10-5

VDD=0.2 V

10-7
-1.5 -1

-0.5 0
0.5
Vbs (V)

Figure 8. Oscillation frequency as a function of body

biasing.

flow of any significant current through them.

VDD=200 mV

In this measurement, the body-source voltage of N and

PMOSFETs are equal:
(10)

It should be mentioned that body voltage also affects the

low frequency noise of the MOSFETs [6]. This noise is
believed to have important effect on the spectrum of the
oscillator, and therefore it is possible to improve the phase
noise by applying proper potential to the body of transistors, as discussed elsewhere [7].
It was also observed that frequency of oscillation increases
with temperature when power supply is very low and it
decreases for large values of power supply. The reason is
that when transistors operate in subthreshold region their
current increase with temperature and in strong inversion
they decrease as temperature increases. This affects the
propagation delay of the inverters and therefore the oscillation frequency of the ring oscillator.

4. LOW VOLTAGE OPERATION OF CMOS

LOGIC GATES
The results of the study of the low-voltage operation of the
CMOS ring oscillator in the last section suggest the possibility of the low-voltage operation of other CMOS gates.
To verify this possibility, the DC characteristics of a 3input CMOS NAND gate shown in Figure 9 is simulated.
The models used for the transistors were BSIM3. The result
of simulation is shown in Figure 10 and clearly shows that
even for VDD=200 mV this logic gate has a sharp high-tolow transition. It is underlined that the channel length used
for the devices in this simulation are chosen long. This
indicates that the logic gates fabricated with technologies
with a relatively long channel length also should have the
capability of operation at low supply voltage. This is not
unexpected as in the analysis of operation of inverter carried out in the previous sections, only the fundamental
characteristics of MOSFETs was used and did not take into
account any of the MOSFET properties peculiar to shortchannel devices.
With a decrease of supply voltage, the speed of operation
of the logic gates also decreases, as discussed in previous
section. This decrease in speed can be compensated to
some extent by forward biasing the source-body of the
transistors. The limit to this forward biasing voltage is the
turn-on voltage of the source-body p-n junctions in order to
keep the current flowing through this junction negligible.

VA

VB=VC=200 mV

PMOSTs: W=6.1 m, L=1 m

NMOSTs: W=1.8 m, L=1 m

VB

VC

Vout

VA
VB
VC

Figure 9. The transistor level of the 3-input NAND gate

used for low-voltage operation simulation.

250
Vout (mV)

V bsn = V bsp

200
150
100
50
0
0

50

100

150

200 250

VA (mV)
Figure 10. DC characteristics of the NAND gate shown
in Figure 9.

5. CONCLUSION
The low voltage operation of a CMOS ring oscillator and
simple CMOS logic gates circuit were investigated by
experiment and simulation. It was shown both by measurement and analysis that an inverter, the simplest CMOS
logic gate, can operate with very low supply voltages VDD
far below the threshold voltage of the transistors. The
mechanism of operation of an inverter at this voltage range
is essentially the same as that in the strong inversion region
of operation. As long as VDD is large enough so that in the
Id-Vds characteristics of the MOSFETs of the inverter two
regions of linear (i. e., drain current is a strong function of
Vds) and saturation region (i. e., drain current is almost
constant and independent of Vds) can be distinguished, the
inverter works properly. At very low supply voltages (~
100 mV) the voltage transfer characteristics (VTC) of the
inverter start to deteriorate.
Operation of a CMOS ring oscillator at low VDD values
was studied. Oscillation frequency decreases with decreasing VDD due to increase in the propagation delay of the

inverters. It was shown that body bias of MOSFETs can be

used to change the propagation delay and therefore, the
oscillation frequency of the ring oscillator.
Based on the observations on the low voltage operation of
the inverter and the ring oscillator, it was speculated that
CMOS logic gates also should be able to operate at low
supply voltages. This was verified with simulation of the
DC characteristics of a 3-input CMOS NAND gate. Lowering the supply voltage reduces the speed of operation of the
gate as well. This drop in speed can be partially compensated by placing a forward bias between source-body of the
transistors. Therefore the available CMOS technologies
without any change in their process can be used for very
low power digital applications where frequency of operation does not need to be very high. An example of the low
power and low frequency operating condition is the digital
signal processing portion of a complete system on a single
chip which are used in some biomedical devices.

Acknowledgements
We are thankful to the Canadian Microelectronics Corporation (CMC) for arranging the fabrication of the test chips.
The research was supported in parts by grants from the
Natural Sciences and Engineering Research Council
(NSERC) of Canada and Micronet, a federal network center of excellence in Microelectronics.

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