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Jean-Pierre Colinge
Tyndall National Institute, University College Cork
Lee Maltings, Cork, Ireland
AbstractThis paper describes the physics and basic
properties of junctionless transistors. These FETs are less
subject to short-channel effects than devices with junctions,
including excellent subthreshold slope and DIBL.
Keywords-MOSFET, SOI,
transistor, multigate transistor
I.
accumulation,
nanowire
INTRODUCTION
Bias
VGS>Vpo
VGS<VFB
VDS<VDSat1
VGS>Vpo
VGS<VFB
VDS>VDSat1
1
1
VGS>VFB
VDS<VDSat2
1
2
VGS>VFB
VDS<VDSat1
VDS>VDSat2
1
1
2
Drain current
VGS>VFB
VDS>VDSat1
1
2
Symbol
Vpo0
Vpo
Weff
S
VDSat1
Value
Linear pinch-off voltage at VD=0V
Pinch-off voltage Vpo = Vpo0 - VDS
DIBL coefficient
Channel perimeter
Neutral (non-depleted) cross section of the
channel; S=Smin when the surface is inverted
and S=Smax when the surface is accumulated
Drain saturation voltage for the neutral bulk
channel
VDSat2
Figure 1: Conduction mechanisms in A:
accumulation-mode and C: junctionless FETs.
inversion-mode;
B:
Leffacc,
Leffb
acc, b
Wf =20 nm
200
Wf =40 nm
NW
Wf =190 nm
-1 -1
Subthreshold slope
DIBL
ION
ION/IOFF
III.
50
NW / planar
[1]
planar
3.0
2.0
1.5
1.0
0.0
0
0.0
0.2
0.4
0.6
Wf =20 nm
2.5
0.8
0.5
1.0
VG-VTH (V)
1.0
1.2
BEYOND SILICON
REFERENCES
Wf
100
Junctionless
92 mV/decade
78 mV/V
1000 A/m
5106
Wf =10 m
150
Inversion mode
75 mV/decade
10 mV/V
1000 A/m
5106
1.4
VG-VTH (V)
Figure 2: Effective electron mobility vs. gate voltage overdrive extracted
for planar and nanowire JLTs with different fin widths. Inset shows this
mobility improvement factor in a NW device with Wf=20 nm over the
planar device. Tsi=10nm and EOT=1.2nm.
B. Short-channel effects
In an IM FET the source and drain have some overlap with
the gate, and the lateral extension of the S/D depletion
charges in the channel region are causing short-channel
effects such as DIBL and degraded subthreshold slope.
These are absent in a JLT.