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3, MARCH 2006
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I. INTRODUCTION
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006
required operating value at given PVT and frequency is presented along with the detail algorithm to compensate the PVT
variations. The methodology for compensating the impact of
operational and parameter fluctuations on CMOS circuit performance is discussed in Section II. The implementation of the
fully digital self-adjusting minimum supply system and analysis
of measured results from fabricated test chips are described in
Section III and Section IV, respectively.
II. METHODOLOGY FOR COMPENSATING THE IMPACT
OF OPERATIONAL AND PARAMETER FLUCTUATIONS
A. Yield Improvement by Adjusting Supply Voltage
While the operating frequency limits allowable propagation
delay, this delay strongly depends on intrinsic process parameters, supply voltage, and junction temperature. The propagation
delay in a MOSFET is proportional to the product of the active
resistance of the MOSFET and load capacitance as in (1)
(1)
where
is the velocity saturation term,
is the process
is the supply voltage,
is
transconductance parameter,
the threshold voltage,
is the drain capacitance,
is the
is the interconnect capacitance.
gate capacitance, and
In deep-submicrometer circuit design, variations due to the
process variation cause differences in transistor and interconnect characteristics across a single die. They, in turn, impact
the performance of circuits since they generate deviations in
MOSFET drive current, resulting in propagation delay distributions of the critical path across a chip. Furthermore, the distribution of process parameters expands from die to die within
a wafer as well as a lot. After fabrication, operating variations
such as power supply voltage, and across-chip temperature also
affect the propagation delay. By combining both operational
and process induced variations, the propagation delay fluctuates
from 18% to 32% [10]. The yield of CMOS logic circuits satisfying a specific performance requirement is significantly influenced by the magnitude of critical path delay deviations due to
both operational and intrinsic parameter fluctuations.
Process parameters and operating junction temperature are
not controllable, but supply voltage is. Therefore, if the supply
voltage can be adjusted to guarantee the same propagation delay
regardless of the other operating conditions, various simulations
are not needed to assure proper functionality. Instead, only one
case, the worst case simulation with small margin is needed to
guarantee proper operation after fabrication. If a design is fabricated at the best process corner and is operating at low temperature, it needs less than 3/4 of the minimum supply voltage
required to operate at the worst case [10]. This results in power
savings by reducing supply voltage with regard to process and
temperature. Moreover, the distribution of the variations can be
moved to the desirable position by increasing supply voltage as
shown in Fig. 1 [10]. On the other hand, by dynamically adjusting the supply voltage, the individual die is adjusted to the
Fig. 1. n
(T
) due to an increase in
KANG et al.: A HIGH-EFFICIENCY FULLY DIGITAL SYNCHRONOUS BUCK CONVERTER POWER DELIVERY SYSTEM
Fig. 2. Function of supply voltage for a 0.13- process delay transfer characteristic at the best (bottom line), typical (middle line), and the worst (top line)
cases.
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Fig. 3. Supply voltage level shift (55 mV, top wave) due to variations of load
current change between 50 and 250 mA.
To provide an error signal for a PID control loop, prior approaches require a reference source (constant voltage [11] or
fixed frequency [3]) that occupies space reserved for a design
and consumes power. Since the reference is implemented as
an analog- or mixed-signal circuit, it is difficult to implement
a fully digital AVS controller. Moreover, the pitfall of the reference based supply voltage schemes [3], [4], and [11] with regard to only a given frequency, is that its supply voltage is usually not the minimum voltage in which a chip operates properly.
The reason is that the propagation delay strongly varies in response to PVT as in (1) while a frequency determines an allowable propagation delay. In other words, if a chip is fabricated
at the best process corner and operates at low temperature, its
minimum supply voltage is only 3/4 of the minimum voltage to
guarantee the proper function at the worst case. The minimum
power consumption at the best case is about half of the worst
case due to the quadratic dependency of power. Therefore, the
adaptive-power supply system considers PVT and load conditions as well as operating frequency.
The presented AVS requires some additional restrictive considerations compared to prior AVS implementations due to both
delay and parameter variations. First, higher digital-to-analog
converter (DAC) resolution is needed since AVS is prone to be
in a limit-cycling mode. If the ADC has a 6-bit resolution at
3.3 V, the worst case step voltage is about 50 mV. If DAC has
7 bits, its resolution at 3.6 V is about 28 mV and may avoid
limit-cycling. However, the step voltage is about 26.5 mV at the
best case as shown in Fig. 2. This results in limit-cycling since
7-bit DAC resolution at the worst case is less than that of 6-bit
ADC at the best case. Therefore, 8-bit DAC resolution is needed
to prevent limit-cycling from occurring. The DACs higher resolution than the ADC often results in multiple DAC values in the
ADC. When a high to low transition occurs with a frequency
change, the highest DAC voltage level equal to the ADC level
may be a settling point. Alternatively, during low to high, the
lowest level may be acquired.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006
Fig. 5. Block diagram of all digital self-adjusting minimum power supply system.
KANG et al.: A HIGH-EFFICIENCY FULLY DIGITAL SYNCHRONOUS BUCK CONVERTER POWER DELIVERY SYSTEM
233
The voltage adjuster consists of an error compensator, a frequency compensator, a process, voltage, and temperature compensator, and a control block as shown in Fig. 8. The major
role of the voltage adjuster is to compensate a supply voltage
error at a given frequency from the measurement of the slacktime detector and to provide a desirable constant voltage level
against variations of frequency as well as PVT. In addition, for
high-speed and low-overshoot/undershoot start-up, it controls
soft-start operation.
1) Error Compensator: The role of the error compensator
as in (2), and to generate a
is to detect the voltage error,
proportionally compensated value. It receives the propagation
delay word TX(27:12) from the slacktime detector and detects
the position of one and zero pair of taps as shown in Fig. 9.
The compensator converts the propagation delay position to an
error voltage by comparing it to the reference delay position
along with supply voltage under worst case conditions. In turn,
it generates a proportionally compensated propagation delay
word ECW(5:0) that represents a reference value at a default
frequency plus a compensated error value.
2) Frequency Compensator: The frequency compensator
adjusts the duty cycle of the PWM pulse based on the desired
supply voltage at a given frequency. The first subtractor, SUB1,
in Fig. 10 generates a difference between the frequency information, FI(5:0), and the internal reference voltage level,
RFI(5:0). The difference implies the desirable voltage variation
in response to a given frequency. The up/down counter (CNT)
receives the difference and counts up or down at the load signal
(LOAD) until the output of the counter is equal to the difference.
This prevents the supply level and frequency variation from
abruptly changing and reduces ringing. The second subtractor,
SUB2, receives the proportionally compensated propagation
delay word ECW(5-0) from the error compensator and the
shift-lefted counter number for the subtrahend, and generates a
frequency compensated propagation delay word FCW1(5-0).
The compensated error-step from the delayline is the same as
the resolution of the delayline (6 bits). However, the resolution
of the DAC is higher than that of the ADC, and the error step also
has a higher resolution. To increase the control resolution, the
proportionally compensated error-value should be scaled close
to the resolution of the DAC. The third subtractor, SUB3, provides a reference supply voltage word FCW2(5:0) at a given
frequency FI(5:0). The one-bit higher resolution compensated
word FCW(7:1) is generated by adding the frequency compensated word to the reference supply voltage word. However, a
7-bit DAC for a 6-bit ADC is insufficient to avoid limit-cycling
(Section II). Therefore, dither logic generates a least significant bit (LSB) of the frequency compensated word FCW(0).
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006
Fig. 8. Block diagram of voltage adjuster against variations of frequency and PVT.
KANG et al.: A HIGH-EFFICIENCY FULLY DIGITAL SYNCHRONOUS BUCK CONVERTER POWER DELIVERY SYSTEM
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006
Fig. 13. Block diagram of clock generator and a timing diagram of clocks.
KANG et al.: A HIGH-EFFICIENCY FULLY DIGITAL SYNCHRONOUS BUCK CONVERTER POWER DELIVERY SYSTEM
237
Fig. 18. Measured output voltage with tap value and supply voltage at the best
(bottom lines), and the worst (middle lines) cases at room temperature. The top
dashed line is the ideal case at the worst condition.
E. LC Filter Construction
Fig. 16. Block diagram of PWM modulator.
where
is the ripple voltage,
is the input voltage, is
,
is the switching frequency, and
the duty ratio of
is a product of inductance and capacitance. For example,
V,
V,
kHz, and
mV,
.
then required
The next consideration is the minimum oscillation (damped
natural) frequency in (4)
(4)
D. DPWM Driver
The single loop design eliminates most of the analog circuit
including references, ramp generators, and ADC comparators,
normally associated with analog synchronous buck converters.
A driver chip less than 1 mm on a side can easily be develbump chip
oped and placed in a low-cost SOT23-5 or a
package. A 0.5- m power CMOS process serves as an excellent
choice for the driver for supplies less than 5.5 V, which is the
case in virtually all cell phones today. Additional features such
as over and under voltage protection, thermal shutdown, and
dead time (nonoverlapping phase) generation can be included.
The driver can generate an arbitrarily large current (1 A) without
significantly impacting stability and efficiency. Also, the driver
chip can be directly driven at low voltage since level shifters
are included in the input. Furthermore, the need for trims and
voltage corrections normally associated with analog switches
are eliminated.
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Fig. 19. AVS supply voltage: (a) soft start of the worst process corner, (b) 50-mV supply voltage fluctuation (top signal) during load transition (bottom pulses)
between 65 and 350 mA (1-grid: 200 mV, 1 ms), (c) low to high full swing (0.7 to 1.1 V) of worst process corner sample, (d) high to low full swing (0.9 to 0.6 V)
of the worst process corner sample, (e) low to high 4-step swing (120 mV) of the best process corner sample, and (f) high to low 4-step swing (160 mV) of the
worst process corner sample (1-grid: 200 mV, 40 s).
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239
ACKNOWLEDGMENT
The authors greatly appreciate the help that G. Walker, at the
National Semiconductor Corporation, provided in designing the
demo-boards.
REFERENCES
[1] T. D. Burd and R. W. Brodersen, Design issues for dynamic voltage
scaling, in Proc. ISLPED Conf., 2000, pp. 914.
[2] K. Suzuki et al., Variable supply-voltage scheme for low-power highspeed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, no.
3, pp. 454462, Mar. 1998.
[3] G.-Y. Wei and M. Horowitz, A fully digital, energy-efficient, adaptive
power-supply regulator, IEEE J. Solid-State Circuits, vol. 34, no. 4,
pp. 520528, Apr. 1999.
[4] J. Kim and M. Horowitz, An efficient digital sliding controller for
adaptive power supply regulation, in Proc. Very Large Scale Integr.
(VLSI) Circuits Dig. Tech. Papers Conf., 2001, pp. 133136.
[5] D. W. Kang, Low-power digital adaptive voltage controller design
based on hybrid control and reverse phase mode, Ph.D. dissertation,
Dept. Elect. Comp. Eng., Northeastern Univ., Boston, MA, 2003.
[6] V. von Kaenel, P. Macken, and M. Degrauwe, A voltage reduction
technique for battery operated systems, IEEE J. Solid-State Circuits,
vol. 25, no. 5, pp. 11361140, Oct 1990.
[7] T. Kuroda et al., Variable supply-voltage scheme for low-power highspeed CMOS digital design, IEEE J. Solid-State Circuits, vol. 33, no.
3, pp. 454462, Mar. 1998.
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006
James T. Doyle (SM03) received the B.S.E.E. degree from the University of Nebraska, Lincoln, NE,
in 1972, and the M.B.A. degree from Nova Southeastern University, Fort Lauderdale, FL, in 1992.
He was a Chief Technologist for the CCG Division of the Intel Corporation, Chandler, AZ. He was
the Chief Architect of the 3G Mitsubishi Analog
Baseband Chip and also the Technical Lead on the
Solano 815 Chip Set project at Intel. He spent 13
years in Motorolas Handheld Products Division,
Fort Lauderdale, FL, and contributed to the HT, MX