Decoupling

Effective Power/Ground
Plane Decoupling for PCB

Dr. Bruce Archambeault
IBM Distinguished Engineer
IEEE Fellow
IBM
Research Triangle Park, NC
Barch@us.ibm.com
IEEE
October 2007
Power Plane Noise Control
Ground
Bounce
October 2007
Power/Ground-Reference Plane Noise

Must consider TWO Major Factors
EMC -- Reduce noise along edge of board from IC
somewhere else
Functionality -- Provide IC with sufficient charge
Decoupling strategies are FULL of Myths

Consider the physics
Dont forget Inductance!
October 2007
Source of Power/Ground-Reference
Plane Noise
Power requirements from IC during
switching
Critical Net currents routed through via
October 2007
Power Bus Spectrum

Clock Driver IDT74FCT807
October 2007
Noise Injected between Planes Due

to Critical Net Through Via
20 cm
I/O Pin/Via
Signal Via
30 cm
FR4 r=4.2
October 2007
Loss tan=0.02
Transfer Function from Via to I/O Pin

Transfer Function From Via-to-Via
20x30cm Board
0
5 mil Seperation
10 mil Seperation
15 mil Seperation
25 mil Seperation
35 mil Seperation
-10
Transfer Function (dB)
-20
-30
-40
-50
-60
-70
1.E+08
1.E+09
1.E+10
Frequency (Hz)
October 2007
Decoupling Must be Analyzed in

Different Ways for Different Functions
EMC
Resonance big concern
Requires STEADY-STATE analysis
Frequency Domain
Transfer function analysis

Eliminate noise along edge of board due to
ASIC/IC located far away
October 2007
Decoupling Must be Analyzed in

Different Ways for Different
Functions
Provide Charge to ASIC/IC
Requires TRANSIENT analysis
Charge will NOT travel from far corners of the
board fast enough
Local decoupling capacitors dominate
Impedance at ASIC/IC pins important
October 2007
Steady-State Analysis
Measurements and Simulations
Test Board with Decoupling capacitors
every 1 square
October 2007
10
Test Board Ports

12
11
10
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
#11
#12
#13
#14
#15
5
1
1
3
Figure 1
6
9
October 2007
11
S21 Used for Decoupling Goodness

Ratio of Power out to power in
Better Indicator of EMI noise transmission
across board
Also used to validate simulations
October 2007
12
Measured S21 for 12" x 10" PC Board Between Power/Ground Planes

with No Decoupling Capacitors
(Measured Center to Corner)
0
-10
-20
Board
Capacitance
Dominates
S21 (dB)
-30
-40
-50
-60
-70
Physical Board Size Resonances Dominate
-80
0.0E+00 1.0E+08 2.0E+08 3.0E+08 4.0E+08 5.0E+08 6.0E+08 7.0E+08 8.0E+08 9.0E+08 1.0E+09
Frequency (Hz)
October 2007
13
Test Board Decoupling Capacitor

Placement for 25 .01 uf Caps
Possible Cap
Location
Populated
Cap
Locations
October 2007
14
Test Board Decoupling Capacitor

Placement for 51 .01 uf Caps
Possible Cap
Location
Populated
Cap
Locations
October 2007
15
Measured S21 for 12" x 10" PC Board Between Power/Ground Planes

with Various Amounts of Decoupling Capacitors
(Measured Center to Corner)
0
-10
-20
-30
S21 (dB)
-40
-50
-60
No Caps
-70
25 Caps
-80
50 Caps
99 Caps
-90
-100
0.0E+00
2.0E+08
4.0E+08
6.0E+08
8.0E+08
1.0E+09
1.2E+09
1.4E+09
1.6E+09
1.8E+09
Frequency (Hz)
October 2007
16
S21 Between Port #8 and Port #1 on Test Board

With Various Amounts of .01 uf Decoupling Capacitors
0
No Caps
-10
25 Caps
51 Caps
S21 (dB)
-20
99 Caps
-30
-40
-50
-60
0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09
Frequency (Hz)
October 2007
17
Cap Impedance
0.01uF
22pF
0.01uF in parallel with 22pF
10000
|Z| (Ohms)
1000
100
10
1
0.1
1.00E+6
1.00E+7
1.00E+8
1.00E+9
1.00E+10
Freq (Hz)
October 2007
18
Test Board Decoupling Capacitor Placement

for 41 22pf Caps
(In Addition to 99 .01uf Caps)
Possible Cap
Location
Populated
Cap
Locations
October 2007
19
S21 Between Port #8 and Port #1 on Test Board

With 99 .01 uf Decoupling Capacitors and Various Amounts of 22pf
Capacitors Added
0
-10
9 22pf Caps
17 22pf Caps
S21 (dB)
-20
21 22pf Caps
33 22pf Caps
41 22pf Caps
-30
99 22pf Caps
99 Caps
-40
-50
-60
0.0E+00 2.0E+08 4.0E+08 6.0E+08 8.0E+08 1.0E+09 1.2E+09 1.4E+09 1.6E+09 1.8E+09
Frequency (Hz)
October 2007
20
Measured Comparison of Multiple and Single Value

Decoupling Capacitor Strategies
0
-10
S21 Transfer Function (dB)
-20
-30
-40
-50
No Caps
99 0.01 uF Caps
0.01 uF and 330 pF Caps
-60
-70
-80
-90
-100
0.0E+00
2.0E+08
4.0E+08
6.0E+08
8.0E+08
1.0E+09
1.2E+09
1.4E+09
1.6E+09
1.8E+09
Frequency (Hz)
October 2007
21
Comparison of Model and Measured Data

for 10" x 12" Board
99 caps -- alternating .01uF and 330pF
0.0
-10.0
-20.0
-30.0
S21 (dB)
-40.0
-50.0
-60.0
CIAO - .01uF & 330 pF

Measured
-70.0
-80.0
-90.0
-100.0
0.0E+00
1.0E+08
2.0E+08
3.0E+08
4.0E+08
5.0E+08
6.0E+08
7.0E+08
8.0E+08
9.0E+08
1.0E+09
Frequency (Hz)
October 2007
22
S21 Transfer Function for Different Value Capacitors

Center-to-Corner
10" x 12" Board
-10
-20
S21 (dB)
-30
-40
-50
99 .01uF caps
99 0.1uF caps
-60
99 0.33uF caps
99 Caps (0.01uF and 330pF)
-70
99 2nh shorts
-80
0.0E+00
1.0E+08
2.0E+08
3.0E+08
4.0E+08
5.0E+08
6.0E+08
7.0E+08
8.0E+08
9.0E+08
1.0E+09
Frequency (Hz)
October 2007
23
Voltage Distribution @ 350 MHz

.01uF and 330pF Case (Source in
Center)
October 2007
24

Center)
October 2007
25

Center)
October 2007
26
Decoupling Capacitor Mounting

Keep as to planes as close to capacitor
pads as possible
Via Separation
Inductance Depends
on Loop AREA
Height above Planes
October 2007
27
Decoupling Capacitor Mounting

Keep as to planes as close to capacitor
pads as possible
IC
IC Connection
Inductance Loop
Capacitor
Capacitor Connection
Inductance Loop
Plane Inductance Loop
October 2007
28
Via Configuration Can Change

Inductance
SMT Capacitor
Via
The Good
Best
Capacitor Pads
The Bad
Better
The Ugly
Really Ugly
October 2007
29
Comparison of Decoupling Capacitor Impedance

100 mil Between Vias & 10 mil to Planes
1000
1000pF
100
0.01uF
Impedance (ohms)
0.1uF
1.0uF
10
0.1
0.01
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
Frequency (Hz)
October 2007
30
Comparison of Decoupling Capacitor

Via Separation Distance Effects
Via Separation
10 mils
0.1 uF Capacitor
Via Seperation (mils)
Inductance (nH)
Impedance @ 1 GHz (ohms)
20
40
60
80
100
150
200
300
400
500
.06
0.21
0.36
0.5
0.64
1.0
1.4
2.1
2.75
3.5
.41
1.3
2.33
3.1
4.0
6.23
8.5
12.69
17.3
21.7
October 2007
31
Example Connection Inductance Values

Spacing
between
Vias
Complex
Formula
(20 mils to
plane)
Simple rect loop

(20 mils to
plane)
Complex Formula
(10 mils to plane)
Simple rect loop

(10 mils to plane)
0805 + 2*10mil
3.0 nH
3.1 nH
2 nH
1.38 nH
0805 +
2*100mil
4.1 nH
4.3 nH
3 nH
2.0 nH
0805 +
2*160mil
5.1 nH
5.1 nH
3.5 nH
2.5 nH
0603 + 2*10mil
2.3 nH
1.74 nH
1.1 nH
0.8 nH
0603 +
2*100mil
3.3 nH
3.15 nH
2.1 nH
1.5 nH
0603 +
2*160mil
4.2 nH
4.3 nH
2.4 nH
2.07 nH
Sources for complex formula:

Knighten, James L., Bruce Archambeault, Jun Fan, Samuel Connor, James L. Drewniak, PDN Design
Strategies: II. Ceramic SMT Decoupling Capacitors Does Location Matter?, IEEE EMC
Society Newsletter, Issue No. x, Winter 2006, pp. 56-67. (www.emcs.org)
Fan, Jun, Wei Cui, James L. Drewniak, Thomas Van Doren, and James L. Knighten, Estimating the
Noise Mitigating Effect of Local Decoupling in Printed Circuit Boards, IEEE Trans. on Advanced
Packaging, Vol. 25, No. 2, May 2002, pp. 154-165.
October 2007
32
Transient Analysis
(Time Limited)
Provide charge to ASIC/IC
Inductance dominates impedance
Loop area 1st order effect
Traditional analysis not accurate

enough
October 2007
33
Current in IC During Logic Transitions

(CMOS)
IC
driver
VCC
switch
IC load
Z0, vp
CL
VDC
GND
VCC
VCC
IC
driver
charge
Z0, vp
shoot-thru
GND
current
October 2007
logic 0-1
IC load
IC
driver
discharge IC load
VCC
Z0, vp
shootthru
current
GND
0V
logic 1-0
34
Typical PCB Power Delivery

DC/DC converter
(Power source)
electrolytic
capacitor
SMT capacitors
GND
GND
VCC
VCC
GND
VCC
IC load
GND
GND
IC driver VCC
GND
VCC
VCC
October 2007
35
Equivalent Circuit for Power Current

Delivery to IC
connector
and wiring
Lps
Lbulk
capacitor
leads
Lvia
VDC
Cbulk
DC/DC
converter
October 2007
via interconnect
PCB
wiring
Ltrace
IC load
Cplanes
switch
CSMT
electrolytic
capacitors
SMT
capacitors
VCC/GND
plane
36
Traditional Analysis #1
Use impedance of capacitors in parallel
ESR1
ESR2
ESL1
ESL2
1uF
Impedance to IC
power/gnd pins
October 2007
0. 1uF
ESR3
ESL3
0.01uF
ESR4
ESL4
.001uF
No Effect of Distance Between Capacitors

and IC Included!
37
Traditional Impedance Calculation

for Four Decoupling Capacitor Values
1000
100
.1uF
.01uF
Impedance (ohms)
.001uF
.0001uF
10
All in Parallel
0.1
0.01
1.00E+07
1.00E+08
1.00E+09
Frequency (Hz)
October 2007
38
Traditional Analysis #2
Calculate loop area Traditional loop
Inductance formulas
Which loop area? Which size conductor
ESR1
ESR2
ESR3
ESL1+Ld1
ESL2+Ld2
ESL3+Ld3
1uF
Impedance to IC
power/gnd pins
0. 1uF
0.01uF
ESR4
ESL4+Ld4
.001uF
Over Estimates L and Ignores Distributed Capacitance

October 2007
39
More Accurate Model Includes

Distributed Capacitance
Intentional Decoupling Capacitors
IC Power Pin
Distributed
capacitors
October 2007
40
Schematic
Intentional
Capacitor
ESR
Loop L
Note: L increases
as distance from
source increases
Capacitance
Source
October 2007
41
Effect of Distributed
Capacitance
Can NOT be calculated/estimated using
traditional capacitance equation
Displacement current amplitude changes
with position and distance from the source
October 2007
42
Displacement Current
500 MHz via @450 mils from
Source
October 2007
43
Need to Find the Real Effect of

Decoupling Capacitor Distance
Perfect decoupling capacitor is a via
between planes
FDTD simulation to find the effect of
shorting via distance from source
Vary spacing between planes, distance
to via, frequency, etc
October 2007
44
Impedance of Shorting Via vs. Frequency

Four Via Case (20 mil Seperation Between Plates)
100
Impedance (ohms)
10
0.1
1.E+08
1.E+09
20mils
40mils
50mils
60mils
70mils
80mils
90mils
100mils
120mils
130mils
140mils
150mils
160mils
180mils
200mils
220mils
240mils
250mils
350mils
450mils
1.E+10
Frequency (Hz)
October 2007
45
Impedance Result
Linear with frequency (on log scale)
Looks like an inductance only!
Consider this inductance an Apparent
Inductance
Apparent inductance is constant with
frequency
October 2007
46
Apparent Inductance for One Shorting Via Case

20 mil Plate Separation
1.2
Inductance (nH)
0.8
0.6
50mils
110mils
120mils
200mils
250mils
350mils
450mils
0.4
0.2
0
1.E+08
1.E+09
1.E+1
Frequency (Hz)
October 2007
47
Formulas to Predict Apparent

Inductance
Lone via = (0.1336 s 0.0654) Ln(dist ) + (0.2609 s + 0.2675)
Ltwo via = (0.1307 s 0.0492) Ln(dist ) + (0.2948s + 0.1943)
Lthree via = (0.1242 s 0.0447) Ln(dist ) + (0.2848s + 0.1763)
L four via = (0.1192 s 0.0403) Ln(dist ) + (0.2774 s + 0.1592)
s = separation between plates (mils/10)
dist = distance to via
October 2007
48
True Impedance for Decoupling Capacitor

IC
Capacitor
Power
Gnd
LIC
Lapparent
Lcap
Lapparent
ESR
Lcap + LIC
Source
October 2007
Nominal
Capacitance
49
Impedance Calculation with Apparent Inductance

for Four Decoupling Capacitor Values
10
Cap Value
0.1 uF
0.01 uF
0.001uF
0.0001uF
Case1
Distance to Cap from IC

Case 1
Case 2
Case 3
800mils 1200mils 1500mils
600mils
900mils 1100mils
400mils
700mils 800mils
200mils
400mils 400mils
Case2
Case3
Traditional Calculation
Impedance (ohms)
0.1
0.01
1.E+07
1.E+08
1.E+09
Frequency (Hz)
October 2007
50
Effect of Distributed
Capacitance
Can NOT be calculated/estimated using
traditional capacitance equation
Displacement current amplitude changes with
position and distance from the source
Following examples use cavity resonance
technique (EZ-PowerPlane)
Frequency Domain to compare to measurements
Time Domain using SPICE circuit from cavity
resonance analysis
October 2007
51
Parameters for Comparison to

Measurements
Dielectric thickness = 35 mils
Dielectric constant = 4.5, Loss tan = 0.02
Copper conductivity = 5.8 e7 S/m
October 2007
52
Measured vs Model (MoM) S21 for 12" x 10" PC Power/gnd

with 25 .01uF caps
Position 8-to-1
No Caps - Measured
-10
EZ-PP No Caps
S21 (dB)
-20
-30
-40
-50
1.0E+07
1.0E+08
1.0E+09
1.0E+10
Frequency (Hz)
October 2007
53
Measured vs Model (EZ-PP) S21 for 12" x 10" PC Power/gnd

with 25 .01uF caps
Position 8-to-1
0.0
-10.0
-20.0
-30.0
S21 (dB)
-40.0
-50.0
-60.0
Measured
-70.0
EZ-PP 25 caps
-80.0
-90.0
-100.0
1.0E+07
1.0E+08
1.0E+09
1.0E+10
Frequency (Hz)
October 2007
54
Measured vs Model (EZ-PP) S21 for 12" x 10" PC Power/gnd

with 95 .01uF caps
Position 8-to-1
0.0
-10.0
-20.0
-30.0
S21 (dB)
-40.0
-50.0
-60.0
95 Caps - Measured
95 Caps - EZ-PP
-70.0
-80.0
-90.0
-100.0
1.0E+07
1.0E+08
1.0E+09
1.0E+10
Frequency (Hz)
October 2007
55
Impedance at Port #1
Single 0.01 uF Capacitor at Various Distances (35mil Dielectric)
30
20
Impedance (dBohms)
10
-10
-20
no caps
300 mils
500 mils
700 mils
1000 mils
-30
-40
1.0E+07
October 2007
1.0E+08
Frequency
(Hz)
Dr. Bruce
Archambeault
1.0E+09
1.0E+10
56
Z11 Phase Comparison as Capacitor distance Varies for 35 mils FR4

ESL = 0.5nH
2
1.5
Phase (rad)
0.5
-0.5
100 mils
200 mils
300 mils
400 mils
1000 mils
2000 mils
-1
-1.5
-2
1.0E+06
1.0E+07
1.0E+08
1.0E+09
Frequency (Hz)
October 2007
57
Impedance at Port #1
20
10
Impedance (dBohms)
0
no caps
300 mils
500 mils
700 mils
1000 mils
-10
-20
-30
-40
-50
1.0E+07
October 2007
1.0E+08
Frequency
(Hz)
Dr. Bruce
Archambeault
1.0E+09
1.0E+10
58
Cavity Resonance (EZ-PowerPlane)

Equivalent Circuit for HSPICE
Lij
Port i
Lii
October 2007
Port j
Ljj
Nmni
C0
Lmn Gmn
Nmnj
N01i
C0
L01 G01
N01j
N00i
C0
G00
N00j
Por
tn
59
Impedance Comparison (EZ-PP vs HSPICE) at Port #1

20
10
Impedance (dBohms)
-10
-20
300 mils
300 mils (HSPICE)
1000 mils
1000 mils (HSPICE)
-30
-40
-50
1.0E+07
October 2007
1.0E+08
Frequency
(Hz)
Dr. Bruce
Archambeault
1.0E+09
1.0E+10
60
Current Source Pulse for Simulated IC Power/GND

750 ps Rise/Fall
1.2
Current (amps)
0.8
0.6
0.4
0.2
-0.2
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
61
Time Domain Noise Voltage Across Simulated IC Power/GND Pin (1 amp)

Single Capacitor (with 2 nH) at Various Distances (Fullwave Simulation)
2
1.5
750ps Rise, 35 mil planes,1uF @ 10mils
750ps Rise, 35 mil planes, 1uF @ 400mils
Level (volts)
0.5
-0.5
-1
-1.5
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
62
Time Domain Current through Capacitor From Simulated IC Power/GND (1 amp)

Single Capacitor (with 2nH) at Various Distances
50
0
-50
Current (milliamps)
-100
-150
-200
-250

-300
-350
-400
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
63

Single Capacitor (with No L) at Various Distances
2
1.5

Level (volts)
0.5
-0.5
-1
-1.5
-2
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
64
Time Domain Current through Capacitor From Simulated IC Power/GND (1 amp)

Single Capacitor (with no L) at Various Distances
400
200
Current (milliamps)
-200
-400
-600

-800
-1000
-1200
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
65

Single Capacitor with Various Capacitor Connection Inductance
0.6
0.5
0.4
0.3
Level (volts)
750ps Rise, 10 mil planes, (2nH) 1uF @ 400mils
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
0.5
1.5
2.5
3.5
4.5
Time (ns)
October 2007
66

Single Capacitor with Various Capacitor Connection Inductance
2

750ps Rise, 35 mil planes,(2nH) 1uF @ 400mils
1.5
Level (volts)
0.5
-0.5
-1
-1.5
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
67
Maximum Time Domain Noise Voltage Across Simulated IC Power/GND Pin

Single Capacitor at Various Distances (Fullwave Simulation)
0.8
0.7
0.6
Voltage (volts)
0.5
0.4
750 ps Rise, 10 mil planes,1uF, 2 nH
750 ps Rise, 10 mil planes,1uF, 0.5 nH
750 ps Rise, 10 mil planes,1uF, No L
0.3
0.2
0.1
0
0
200
400
600
800
1000
1200
1400
1600
1800
Distance (mils)
October 2007
68

0.8
0.7
0.6
Voltage (volts)
0.5
0.4
1 ns Rise, 10 mil planes,1uF, 2 nH
1 ns Rise, 10 mil planes,1uF, 0.5 nH
1 ns Rise, 10 mil planes,1uF, No L
0.3
0.2
0.1
0
0
200
400
600
800
1000
1200
1400
1600
1800
Distance (mils)
October 2007
69

1.8
1.6
1.4
Voltage (volts)
1.2
1

0.8
750 ps Rise, 35 mil planes,1uF, 0.5 nH

750 ps Rise, 35 mil planes,1uF, No L
0.6
0.4
0.2
0
0
200
400
600
800
1000
1200
1400
1600
1800
Distance (mils)
October 2007
70

1.6
1.4
1.2
Voltage (volts)
1
1 ns Rise, 35 mil planes,1uF, No L
1 ns Rise, 35 mil planes,1uF, 0.5 nH
0.8
0.6
0.4
0.2
0
0
200
400
600
800
1000
1200
1400
1600
1800
Distance (mils)
October 2007
71
Maximum Voltage vs Distance to Capacitor for 1 ns Rise/fall time

0.01 uF Capacitor with 0.5 nH ESL and 30 mOhm ESR
1.4
Maximum Voltage at source (volts)
1.2
35 mil FR4
10 mil FR4
2 mil FR4
1 mil FR4
0.5 mil FR4
0.8
0.6
0.4
0.2
0
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Distance From Capacitor (mils)
October 2007
72
So Far
Frequency domain simulations not
optimum for charge delivery decoupling
calculations (phase not considered)
Time domain simulations using single
pulse of current indicate limited capacitor
location effect
Connection inductance of capacitor much
higher than inductance between planes
Charge delivered only from the planes
October 2007
73
Charge Depletion
IC draws charge from planes
Capacitors will re-charge planes
Location does matter!
October 2007
74
Model for Plane Recharge

Investigations
r = 4 .5
b = 10
Port2
(4,5)
Port3
(4,4.95)
Port1
(8,7)
Cdec
(4.05,5)
d = 35 mil
Vdc
a = 12
Decoupling Capacitor :
C = 1uF
ESR = 30mOhm
ESL = 0.5nH
I input
DC voltage used to
charge the power
plane
Port 2 represents IC current draw

October 2007
75
Charge Between Planes vs..

Charge Drawn by IC
Board total charge : C*V = 3.5nF*3.3V = 11nC
Pulse charge 5A peak : I*dt/2 = (1ns*5A)/2=2.5nC
October 2007
76
Triangular pulses (5 Amps Peak)
October 2007
77
Noise Voltage from Inductive Effect

of Current Draw
(a)
(b)
Current pulses too small to see charge

depletion effects in this time scale
October 2007
78
Charge Depletion Voltage Drop

4
plane
[V]
3.5
3
2.5
Ls = 1nH
Ls = 10 nH
Ls = 50 nH
1.5
1
October 2007
4
6
Time [ns]
10
79
Charge Depletion vs. Capacitor Distance
October 2007
80
Charge Depletion for Capacitor @ 400 mils

for Various Connection Inductance
October 2007
81
Effect of Multiple Capacitors While Keeping

Total Capacitance Constant
The decap locations are 800mils, 1200mils, 2700mils from the power pin
(power-ground pins at IC center)
Port1 (8,7)
(Ls 50nH)
C=1uF
ESL=0.5nH
ESR=1
Decap
10
1 inch
Ground pin
Port2 (4,5)
(power pin)
r =4.5
12
October 2007
82

Port1 (8,7)
(Ls 50nH)
C=0.5uF
ESL=0.5nH
ESR=1
Decap
10
1 inch
Ground pin
Port2 (4,5)
(power pin)
r =4.5
12
October 2007
83

Port1 (8,7)
(Ls 50nH)
C=0.25uF
ESL=0.5nH
ESR=1
Decap
10
1 inch
Ground pin
Port2 (4,5)
(power pin)
r =4.5
12
October 2007
84
Constant Capacitance
800 mil Distance
October 2007
85
800 mil Distance
October 2007
86
1200 mil Distance
October 2007
87
1200 mil Distance
October 2007
88
2700 mil Distance
October 2007
89
2700 mil Distance
October 2007
90
Example #1
Low Cap Connection Inductance
IC
Cap
PWR
GND
PCB
October 2007
91
Example #2
High Cap Connection Inductance
IC
Cap
PWR
GND
PCB
October 2007
92
Example #1
Hi Cap Connection Inductance
IC
Cap
PCB
PWR
GND
October 2007
93
Example #1
Lower Cap Connection Inductance
IC
PCB
PWR
GND
Cap
October 2007
94
Mutual Inductance Helps Reduce Path

Inductance
Dos
Donts
J. L Knighten, B. Archambeault, J. Fan, et. al., PDN Design Strategies: II. Ceramic SMT
Decoupling Capacitors Does Location Matter?, IEEE EMC Society Newsletter, Issue No.
207, Winter 2006, pp. 56-67.
October 2007
95
Effect of Capacitor Value??

Need enough charge to supply need
Depends on connection inductance
Charge = C*V
October 2007
96

Single Capacitor (with No L) with Various Capacitor Values
0.6
0.5
750ps Rise, 10 mil planes, (0.0 nH) 1uF @ 400mils

750ps Rise, 10 mil planes,0.01uF @ 400mils
0.4
750ps Rise, 10 mil planes, 100pF @ 400mils
Level (volts)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
97

Single Capacitor (with 0.5 nH Connection L) with Various Capacitor Values
0.6
0.5
750ps Rise, 10 mil planes, (0.5nH) 1uF @ 400mils
0.4
750ps Rise, 10 mil planes, (0.5nH) 0.01 uF @ 400mils

750ps Rise, 10 mil planes, (0.5nH) 100 pF @ 400mils
Level (volts)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
98

Single Capacitor (with 1 nH Connection L) with Various Capacitor Values
0.6
0.5

750ps Rise, 10 mil planes, (1nH) 0.01uF @ 400mils
0.4
750ps Rise, 10 mil planes, (1nH) 1000pF @ 400mils

750ps Rise, 10 mil planes, (1nH) 100pF @ 400mils
Level (volts)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
0.5
1.5
2.5
3.5
Time (ns)
October 2007
99
Noise Voltage is INDEPENDENT of

Amount of Capacitance!
As long as there is
enough charge
Dist=400 mils
ESR=30mOhms
ESL=0.5nH
October 2007
100
Decoupling Summary (1)

EMC Frequency Domain analysis
Steady-state conditions resonances
Transfer function across the board
Measurements and simulations agree well
Distance of capacitors from ASIC load does
not change steady-state impedance
October 2007
101

Charge Delivery Time-Limited analysis
Using equivalent SPICE circuit from simulations
Current from capacitors change significantly as
capacitor moves further away from ASIC
Noise at ASIC pins increase significantly as capacitor
moves further away from ASIC
Steady-state frequency domain analysis not sufficient
for charge delivery design of decoupling
capacitors
October 2007
102

Recharge the planes
Location of Capacitor does matter!
Effect more significant for thick dielectrics
Connection Inductance is important

Value of capacitance not important
More capacitors is better than
larger/fewer capacitors
October 2007
103
IEEE
October 2007
104

Decoupling

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Decoupling

Uploaded by

Copyright:

Available Formats

Effective Power/Ground

Plane Decoupling for PCB

Power Plane Noise Control

Dr. Bruce Archambeault

Power/Ground-Reference Plane Noise

Decoupling strategies are FULL of Myths

Dr. Bruce Archambeault

Dr. Bruce Archambeault

Power Bus Spectrum

Dr. Bruce Archambeault

Noise Injected between Planes Due

Transfer Function from Via to I/O Pin

Transfer Function (dB)

Dr. Bruce Archambeault

Decoupling Must be Analyzed in

Transfer function analysis

Dr. Bruce Archambeault

Decoupling Must be Analyzed in

Dr. Bruce Archambeault

Dr. Bruce Archambeault

Test Board Ports

Dr. Bruce Archambeault

S21 Used for Decoupling Goodness

Dr. Bruce Archambeault

Measured S21 for 12" x 10" PC Board Between Power/Ground Planes

Physical Board Size Resonances Dominate

Dr. Bruce Archambeault

Test Board Decoupling Capacitor

Dr. Bruce Archambeault

Test Board Decoupling Capacitor

Dr. Bruce Archambeault

Measured S21 for 12" x 10" PC Board Between Power/Ground Planes

Dr. Bruce Archambeault

S21 Between Port #8 and Port #1 on Test Board

Dr. Bruce Archambeault

Dr. Bruce Archambeault

Test Board Decoupling Capacitor Placement

Dr. Bruce Archambeault

S21 Between Port #8 and Port #1 on Test Board

Dr. Bruce Archambeault

Measured Comparison of Multiple and Single Value

S21 Transfer Function (dB)

Dr. Bruce Archambeault

Comparison of Model and Measured Data

CIAO - .01uF & 330 pF

Dr. Bruce Archambeault

S21 Transfer Function for Different Value Capacitors

Dr. Bruce Archambeault

Voltage Distribution @ 350 MHz

Dr. Bruce Archambeault

Voltage Distribution @ 750 MHz

Dr. Bruce Archambeault

Voltage Distribution @ 950 MHz

Dr. Bruce Archambeault

Decoupling Capacitor Mounting

Dr. Bruce Archambeault

Decoupling Capacitor Mounting

Plane Inductance Loop

Dr. Bruce Archambeault

Via Configuration Can Change

Dr. Bruce Archambeault

Comparison of Decoupling Capacitor Impedance

Dr. Bruce Archambeault

Comparison of Decoupling Capacitor