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Filippo Persia
ATE & RF Systems Engineer
Agenda
• Introduction to FPGAs in Test & Measurement
• LabVIEW FPGA 2009: more power
CLIP Node
NI Labs Additional Features
• FPGA for T&M hardware: FlexRIO
Architecture
Designing custom I/O adapter modules
Software Defined System Architecture
Software-Defined
Standard Virtual Bus Interface Measurementt
M
and I/O Analog or
Instrumentation Digital
Control
Model NI LabVIEW Driver Front End
Software Hardware
10011011
FPGA Based System Architecture
FPGA-Based
Bus Interface/
Open Programmable Measurement
FPGA FPGA Analog or
Digital
System Front End
Model LabVIEW Driver
Software NI Hardware
• Protocol-aware ATE
Protocols • Interfacing (digital or modulated)
RIO IF Transceiver
LabVIEW FPGA Virtex‐5 R Series
LabVIEW FPGA &
demonstrated at
demonstrated at R Series Released
NI Week Lots of
cRIO stuff! FlexRIO
CompactRIO sbRIO
DRAM support
IP Integration (CLIP node)
IP Integration (CLIP node)
External Clocks*
Peer‐to‐Peer Streaming*
p
DMA Transfer rates up to 800MB/s*
Up to 16 DMA channels per device*
*on selected targets
What Is a CLIP?
PXI
Terminaal Blocck
Socketeed CLIP
PXI Bus
PXI Bus LabVIEW FPGA VI
LabVIEW FPGA VI
P
Socketed CLIP Socketed CLIP
DRAM DRAM
Adding a CLIP to the LabVIEW Project
• CLIP Node Files:
IP source code (HDL, netlists, coregen)
Constraints file (optional)
XML file
• Describes the interface between the CLIP and
LabVIEW
• Identifies ppath to source code
Adding
g a CLIP to the LabVIEW Project
j
AnalogFrontEndCLIP.vhd
entity AnalogFrontEnd is
port (
adcCh0_LV : out std_logic_vector(15 downto 0);
adcCh0_TB : in std_logic_vector(15 downto 0) := x"0000"
);
end AnalogFrontEnd;
<InterfaceList>
<I t f Li t>
<Interface Name=“AnalogIO">
<InterfaceType>LabVIEW</InterfaceType>
<Signal Name=“ADC Ch0_LV">
<HDLName>adcCh0_LV</HDLName>
<DataType><I16/></DataType>
<Direction>FromCLIP</Direction>
<SignalType>data</SignalType>
</Signal>
</Interface>
</InterfaceList>
</CLIPDeclaration>
Adding
g a CLIP to the LabVIEW Project
j
Demo: reuse a DDS Netlist
NI FlexRIO Adapter Module
• C
Cardd edge
d connector t
• Defines I/O for NI
LabVIEW FPGA
• Self identification
• Custom connectivityy
• Adapter Module
Development Kit (MDK)
NI FlexRIO Adapter Module Options
Third-Party
Thi dP t Custom
C t
NI Modules
Modules Modules
• Complete • Expands NI • Requires PCB
integration with I/O breadth and HDL design
LabVIEW FPGA • Custom and work
• R Series-like application- • Supported
experience specific modules through MDK
NI 6581
High-Speed Digital Adapter Module
100 MHz digital I/O
54 single-ended
g channels
Selectable voltage levels
1.8,
1 8 2.5,
2 5 33.33 V (5 V compatible)
External DIO voltage reference
Voltage Reference
Data Out
DDC
Output Enable
Data In NI 6581
NI 6581 - CLIPs
PXI-6585R
NI FlexRIO Partner Modules
• Optional Parameters
Serial Number
User Space
Byte Address Size (Bytes) Field Name Required?
0x0 2 Vendor ID Yes
0x2 2 Product ID Yes
0x4 4 Serial Number No
0x8 24 Reserved No
0x20 224 User Space No
Adapter Module Interface Protocol
1. Check TB_Present_n
Adapter Module Inserted
Software forced redetect
System power up or FPGA download
2. Enable Veeprom
3. Read EEPROM ID, check bitstream for match
4
4. E bl allll power rails
Enable il
5. Wait for TB_Power_Good
6
6. Set CLIP signal rIoModGpioEn high
Allows CLIP to enable outputs and BUFGCE safely
Adapter Module Configuration File
• Important part of Adapter Module development
• Configure VCCOA and VCCOB
Ensures proper bank voltages
• Determine Module ID
Used by LabVIEW project
Add d to
Added t UCF dduring
i compilation
il ti
Virtex 5 FPGA IO Bank Voltage
• User I/O Pins are Divided into 4 Banks
• Each bank is powered by VccoA or VccoB
• Consider Necessary Logic Levels When
Choosingg How to Divide the Voltage
g Banks
GPIO Bank Mapping on Virtex 5
GPIO Banks
FPGA IO Standards
• Xilinx FPGA IO Blocks support several IO
St d d
Standards
• FlexRIO GPIO support
pp a subset of these IO
Standards, including:
IO Standard Vcco
LVTTL 3 3V
3.3V
LVCMOS__ 1.2V, 1.5V, 1.8V, 2.5V, 3.3V
LVDCI__ (DCI R = 50Ω) 1.5V, 1.8V, 2.5V, 3.3V
LVDS_25 (inputs use internal 100Ω) 2.5V
• IO Standards
St d d may be b mixed
i d within
ithi a bank,
b k if
Vcco voltages are the same
• See Virtex 5 User Guide for more details
Example .tbc File
[General]
FormatVersion=1 0
FormatVersion=1.0
Manufacturer=National Instruments
Model=NI 5681
Basic adapter module info
Description= National Instruments IF module
V
VccoALevel=2.5
AL l 2 5
VccoBLevel=3.3
Set Logic Levels: must match I/O Standard constraint
IOModuleID=0x10935681
Used by LV project
DefaultCLIP=IFModuleClip
[Constraints]
INST "*Ibufd*" DIFF_TERM = TRUE; Additional Xilinx Physical Interface Constraints
INST "*Ibufgd*" DIFF_TERM = TRUE;
A
Adapte
So
Interchangeable I/O
ocketeed CLIP
hardware defines the FPGA
to hardware interface
LabVIEW
er Mo
PXI Bus
The user defines FPGA VI
representation of hardware
odule
P
in LabVIEW
Socketed Socketed
• Allows for use of specific CLIP CLIP
FPGA
G I/O
/O ffeatures
DRAM DRAM
Implementing Socketed CLIP
Create or Acquire IP
• Create or Acquire IP
Fixed hardware interface (GPIO, etc)
Shared I2C bus
Adapter
p Module Socket Signals
g
Signal Name Direction Data Type
aUserGpio Bidirectional std_logic_vector(65 downto 0)
aUserGpio_n
p Bidirectional std_logic_vector(65
g ( downto 0))
rIoModGpioEn To CLIP std_logic
UserGClkLvds To CLIP std_logic
UserGClkLvds_n To CLIP std_logic
UserGClkLvttl To CLIP std_logic
Signal
g Name Direction Data Type
yp
IoModClipClock0 From CLIP std_logic
IoModClipClock1 From CLIP std_logic
Shared I2C Bus
• Share bus with
Signal Name Direction Data Type
Socketed CLIP rLvFpgaReqI2cBus From CLIP std_logic
HSDIO Cable
GPIO 0:11 +
clock DDR
AD9752
TxDAC
Custom Adapter
NI 9999
Upcoming
p g NI FlexRIO Adapter
p Modules
Digitizer Module Baseband Transceiver
• 250 MS/s,
MS/s 4 ch.,
ch 1414-bit
bit • 100 MS/s,
MS/s 2 ch.,
ch 1414-bit
bit ADC
• AC or DC coupled • 100 MS/s, 2 ch., 16-bit DAC
• Q4 2009/ Q1 2010 • Q4 2009