2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia

June 2-5, 2012, Harbin, China

Application of IR Digital Controller IRMCF143 in

Photovoltaic Inverter System
Wang Pan-bao, Wang Wei, Xu Dian-guo

Li Ming, Takahashi Toshio

School of Electrical Engineering and Automation

Harbin Institute of Technology
Harbin, China
wangpanbao@hit.edu.cn

Digital Control IC Design Center

International Rectifier Corporation
Xian, China
mli1@irf.com
algorithms. Through the optimized design, the PV inverter
system can achieve the optimum of performance and cost.

AbstractSmall-scale photovoltaic (PV) inverter can be widely

used in households and many other occasions. This paper uses IR
digital controller IRMCF143 to design an 800W single phase PV
inverter. This chip integrates two processors especially for
inverter control. A two-stage topology is applied in the system.
Both stand-alone and grid-connected control strategies are
analyzed. Combine the system requirements and the chip
characteristics, the system hardware framework, maximum
power point tracking (MPPT) algorithm, islanding detection
methods and fault handling functions was designed. At last, the
experimental system is built. The two processors integrated in
one chip can work independently but cooperatively. The aim to
cut the design cycle and cost is realized and the PV inverter
system is tested to achieve the design target and get a stable
running.

II.

A. The Main Topology

The PV inverter systems main topology is a two-stage
structure [2] [3] containing a DC-DC boost converter and a
DC-AC H-bridge inverter. The DC-DC converter boost DC
power generated from PV arrays into a high voltage level and
the DC-AC inverter inverts the DC power into AC power, and
sent it to local load or grid after an L-filter which can eliminate
high-frequency harmonic conducted by high switching working
IGBT. The isolation transformer is used to eliminate the DC
component and electrical protection.

Keywords-photovoltaic inverter system; dual-core controller;

maximum power point tracking; islanding detection

I.

GLOBAL SYSTEM

INTRODUCTION

PV

The photovoltaic (PV) energy has a bright future compared

with traditional energy due to its enormous reserve capacity
and pollution-free features [1]. PV inverter is a key in PV
power generation. Small-scale single-phase PV inverter system
features low investment, high flexibility and adaptability. It can
be used in households, companies and many other occasions
need small-scale power supply. Reduce the small-scale PV
inverters design cycle and cost is an effective way to promote
the development of PV industry.

DC-DC

DC-AC

Load
or
Grid

Filter

Figure 1. Main topology

B. Inverter Control Strategy

The goal of the stand-alone control strategy is to invert the
DC to AC which waveform is sinusoidal, frequency is 50Hz
and the RMS voltage level is 220V.

Depending on the application, PV inverter can be divided

into two types of stand-alone operation mode and gridconnected operation mode. Between the two modes, the
inverters hardware structures are similar but control strategies
are different. This paper used IR Digital Controller IRMCF143
to build a PV inverter system witch can operate in the two
modes.

PV

C2

C1

L1

DC/AC

DC/DC

T1-4

C3

Load

L2
iinv
PWM

U dcbus
Uref*

The chip IRMCF143 was designed specifically for inverter

control. It integrates two processors and some general and
special peripheral devices in one chip. These two processors
can exchange data via a dual port RAM. In this case, one
processor is assigned to execute the stand-alone and gridconnected control algorithms which need good real-time
feature, and the other processor is assigned to execute other

SPWM

PI

i*inv

PI

sin

U *ac

PI

Figure 2. Stand-alone control strategy

As shown in figure 2, in the stand-alone control strategys

first stage, there is a voltage PI closed loop in the boost stage. It
regulates the DC bus voltage to the setting value 400V. In the
second stage, a double closed loop whose inner loop is a

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978-1-4577-2088-8/11/$26.00 2012 IEEE

algorithm including islanding detection, where the stand-alone

and grid-connected algorithms are basic missions. Some
application functions like LCD display and Key control are
also in the controller missions. A relay is used to switch the
inverter output to grid or load.

current control closed loop and outer loop is a voltage control

closed loop is used in the DC-AC stage to switch DC power
into AC power.
The goal of the grid-connected control strategy is to invert
the DC to AC which can be injected to the grid. Generally, a
voltage inverter controls the output current to be a sinusoidal
waveform and the power factor is 1. The grid-connected
currents frequency and phase also need to be equal to the
grids.
L1

DC/AC

DC/DC

C1

C2

T1-4

PV

B. Control System Design Based on IRMCF143

IRMCF143 is a dual-core controller which integrates two
processors specifically designed for the inverter control. One is
a firmware FPGA (named MCE) which can execute high
calculations. Its peripheral devices contain a low-loss SPWM
generator, a 12 bit high-speed A/D converter and so on.
Another is an enhanced 8051 microcontroller, whose peripheral
devices contain three general timers, one watchdog timer, one
universal asynchronous receiver / transmitter (UART), three
general I / O ports and so on. The MCEs control bus and
8051s address / data bus are connected via a dual port RAM
for signal and data exchanging.

C3

Grid

L2
Upv

I pv

iinv
PWM

MPPT

Uin*

SPWM

Udc

PI

sin

PI

PI

*
inv

ugrid

PLL

*
Ipeak

U *dc

8051

Timer 0

Figure 3. Grid-connected control strategy

MCE
SPWM

Timer 1

III.

Upv
Ipv
A/D
Sample

DC-DC

Driver

Udc
A/D
Sample

DC-AC

LED
KEY
PC

PORT 3

Emulator
Debugger

Xtal
4MHz

Dual Port
RAM
MCE
Program
RAM

MCE Control Bus

Local
RAM

PORT 2

MCE
Modules

A/D
MUX
S/H

Interrupt
Control
JTAG

Control
Sequencer

PLL

Figure 5. Block diagram of IRMCF143

Figure 6 is the diagram of IRMCF143 applied in PV

inverter control system. In the dotted line on the left are the
8051 and its external interface, in which the 8051s RS232
communication interface is connected to a PC to monitor the
system status and data. Some I / O pins are connected with a
control panel. On the right are the MCE and its devices. MCE
exports PWM signals to drive the power module and convert
the analog signal to digital from power module. The dual port
RAM and a clock line serve as the bridge between MCE and
8051.

Filter

A/D
Sample

8bit
CPU

PORT 1

iinv
Driver

FLASH

I2C

SYSTEM CONFIGUATION

Relay
Grid

LCD

Single
shunt
current
reconst

UART

A. Systems Block Diagram

The systems block diagram is shown as in figure 4. The
wide lines are signified as power transmission and the narrow
lines are signified as signal transmission.
PV

PWM

Watchdog

8bit Address/data bus

As shown in figure 3, in the grid-connected control

strategys first stage, a maximum power point tracking (MPPT)
algorithm is used to determine the PVs work voltage by a
voltage control closed loop. In the second stage, the DC bus
voltage is regulated by a double closed loop whose outer loop
is a voltage control closed loop and inner loop is a current
control closed loop (PLL). A phase locked loop is needed to
track the grids frequency and phase then generate a
synchronous sinusoidal waveform signal. The voltage closed
loops output multiplies this synchronous sinusoidal signal and
then compares it with the inverters sample current iinv before
sending it to a PI controller.

Timer 2

Load

IRMCF143
MPPT
Algorithm
Application
Code

Stand-alone /
Grid-connected
Algorithm
Faults Handle

Controller

PC

Zero
Detect

COMM
8051

Control
Panel

Faults
Detect

I/O

Dual
Port
RAM

MCE

PWM
&
A/D

clk

Power
Module

Load / Grid

Figure 6. IRMCF143 application partitioning

Figure 4. Block diagram of PV power system

The MCE has a hardware library containing PI controller,

sinusoidal signal generator and so on, and the MCE is a high
speed processor who is good at calculation control, so the
stand-alone and grid-connected invert algorithms are designed

As shown in figure 4, the controller undertakes many

missions as stand-alone invert algorithm, grid-connected invert
algorithm, PLL algorithm, MPPT algorithm and faults handle

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Figure 9 shows the program flow diagrams in the 8051,

which includes a main program, a capture interrupt, a timer
interrupt and a MCE interrupt.

in the MCE. The 8051 is a microcontroller who is good at logic

control, so other algorithms like the MPPT, grids zero capture
and the application codes are designed in the 8051. To enhance
the systems safety, the faults handling is fulfilled by both the
MCE and the 8051.
Figure 7 shows the details of control flow among the MCE
and the 8051. The 8051 can be seen as an assistant of the MCE,
which configures some system parameters like the MCEs
clock, PI controller parameters and so on to initialize the MCE.
Capture

fgrid

Initialization

Command
RS232
&
I/O Infromation

Appliance Sequence states

System
Control
Faults
MCE data
8051

Interrupt 0

Interrupt 1

Interrupt 2

Initialization

MPPT

Read
Time Counter

Clear
Watchdog

Boot MCE

Passive
Anti-islanding

Calculate
AC Frequency

Active
Anti-islanding

Data Exchange

End

Read Faults

Data Handling

PWM
Stand- alone
/
Gridconnected
Control

Start

I/O Control

End

LCD Display

A/D
Sample

MCE

Stop MCE

RS232 Comm

End

Figure 7. Flow of PV inverter system control

When the initialization was done, the 8051 can switch the
MCE working sequence states and the 8051 can convert some
data from the MCE to user data and send them to PC and
control panel to display.

Figure 9. Program flow diagrams in 8051

C. Program Design
To enable the system sequence state working and switching,
a state handler program needs to be designed first. Defined
three basic states: Idle, Run and Fault.
Boot

The main programs missions contain initialization as the

8051 and MCE clock configuration, the 8051 and MCEs
peripheral devices configuration and so on. I / O control, LCD /
LED display and RS232 communication are also in the main
program. By counting the ac sides zero crossing signal rising
edge and failing edge in capture interrupt (interrupt 1), the
output ac voltage or grid frequency can be captured and
calculated.
The MPPT and passive anti-islanding algorithms are
realized in the MCE interrupt. Perturb and observing (P&Q)
method is a common, sample and stable MPPT algorithm [4-7],
which adjusts the PV arrays working voltage periodically by
judging the output power of this time and that of last time. If
the rusults for the two times are nearly equal, it can be seen that
the system reaches the maximum power point (MPP).
Reserchers have achevied a lot of achievements on it so this
paper selects it to realize the MPPT function.

Initialiation

State Idle

Is there a
fault?

State Run

State Fault

Anti-islanding detection contains passive anti-islanding

detection and active anti-islanding detection [8] [9]. In china,
relevant policies claim that grid-connected inverter should have
both passive and active protection methods. The common and
effective passive methods are under / over voltage protection
(UVP / OVP) and under / over frequency protection (UVF /
OVF) [10]. There are various active methods and a good one
named "self-adapted phase shift [11]" was used in this design.
It makes less harmful harmonic and has less detection dead
zone.

Figure 8. State handler

Combined with Figures 7 and 8, when the boot started, the

8051 initialized the MCE and switch it to the state Idle, and
if the PV inverter system external environmental conditions
like the PV arrays output voltage and control command from
external control panel meet the operating conditions, the 8051
will switch the MCE to the state Run. If there is a fault
detected by the 8051 or MCE, whether the state now is Idle
or Run, the MCE state will be switched to Fault.

The MCE handles some faults by itself, and the 8051 also
handles some faults to determine the MCEs sequence state. A
watchdog is also set to monitor the controllers operation. The
fault handle function is realized in a 2 millisecond timer
interrupt, if there is a fault, the 8051 will send a stop command
to the MCE, so the PV inverter system can stop to ensure
safety.

In fact, the MCE is a calculation core based on FPGA in

IRMCF143, PI controller and some usual control units are
customized as firmware in the MCE. So designer can build the
needed PI closed loops in MCE easily by the previous control
strategy in figure 2 and 3.

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IV.

special software name MCE designer developed by IR was

installed in PC. It can configure parameters to MCE and
display waveform in real time by PC. When the debugging
stage completed, the system configuration parameters can be
moved to the 8051 easily to ensure the PV inverter system
operating independently. The MCE designer reduced the PV
inverter system development cycle.

EXPERIMENTAL SYSTEM AND RESULTS

A. Exeriment Plantform
Figure 10 shows the 800W single-phase PV inverter
experimental system. A PV simulator was used to simulate PV
arrays output feature. It can be set the MPP working voltage
and test the PV inverter systems tracking efficiency. A MCE
PV Simulator

PC

Power
Analyser

Oscilloscope

Isolation
Transformer

Inverter

Control Panel
Figure 10. Experimental system

Figure 13 and figure 14 are AC over / under voltage passive

anti-islanding testing waveforms.

B. Experimental Results
Figure 11 and 12 gives the stand-alone and grid-connected
operation waveforms. The waveforms indicate that the standalone modes output voltage is sinusoidal and the gridconnected modes current phase and frequency equal to the
grid. The DC-bus voltage is stable in the set value 400V.

udcbus

ugrid
t (50ms / di v)

Figure 13. AC over voltage protection waveform

iload

uinv
ugrid

t (5ms / di v)

t (50ms / di v)

Figure 11. Stand-alone operation waveform

Figure 14. AC under voltage protection waveform

When the grid is disconnect and the load power is less /

more than the PV inverter output power, there will be an over /
under voltage occurred on the output side. The system detects
the abnormal voltage and stops the inverter.

udcbus
i

Figure 15 and figure 16 are AC over / under frequency

passive anti-islanding testing waveforms. When the grid is
disconnect and the load power includes inductive / capacitive
load, there will be an over / under frequency occurred on the
output side. The system detects the abnormal frequency and
stops the inverter.

ugrid
t (10ms / di v)

Figure 12. Grid-connected operation waveform

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time inverter process is thought to be needed. Meanwhile some

application functions such as data displaying and state control
from a control panel are also needed. In order to realize these
characteristics of PV inverter system, a dual-core controller
IRMCF143 is applied in the PV inverter control system. This
controllers internal blocks and mechanism are introduced. The
design scheme for 800W single-phase PV inverter system is
presented.

ugrid
t (20ms / di v)

Through the optimized design of the MCE processor and

the 8051 microcontroller, the application is implemented and
the PV inverter experimental system has been built. As a result,
both the stand-alone mode and grid-connected mode operation
is realized. Experimental results show that the MPPT and antiislanding functions can be executed correctly and timely. The
PV inverter systems stand-alone and grid-connected operation
parameters, such as the stand-alone voltages THD, gridconnected currents THD, inverter efficiency, MPPT tracking
efficiency and power factor, meet the IEEE-standard.

Figure 15. AC over frequency protection waveform

ugrid
t (20ms / di v)

Figure 16. AC under frequency protection waveform

ACKNOWLEDGMENT

If the load power matches the PV inverters output power

occasionally, the system can detect the islanding via the active
anti-islanding algorithm. Figure 17 shows the active antiislanding waveform.

This work was supported by National Natural Science

Foundation of China (51077017).
REFERENCES
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ugrid
t (50ms / di v)

Figure 17. Active anti-islanding protection waveform

The PV simulator can simulate and test the inverters

MPPT efficiency. When adjusted the voltage of the maximum
power point online, the inverter can track the new maximum
power point timely. When the output power is more than 300W,
the MPPT efficiency is more than 99.2%.

Figure 18. MPPT testing result

V.

CONCLUSIONS

In this paper, a two-stage topology single-phase PV inverter

system has been designed and built. Through the analysis of
the systems operating functions and control principle, a real-

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