MIMO/Smart Antenna Development Platform

Florian Kaltenberger, Gerhard Humer, Georg Pfeiffer

ARC Seibersdorf research GmbH
Tech Gate Vienna, A-1220 Vienna, Austria, Donau-City-Strae 1, 4th Floor
phone: +43(0)50550/4149, fax: +43(0)50550/4150
email: <firstname.lastname>@arcs.ac.at, web: www.arcs.ac.at/IT/ITS

Abstract Smart Antennas (SA) and Multiple Input Multiple Output (MIMO) systems are considered
as one of the key technologies for the third generation
mobile communication systems and are now even being
included in the UMTS standard [1]. With those technologies it is possible to improve the signal-to-noise ratio at the receiver and increase capacity in mobile radio
systems.
To test and evaluate new algorithms for those systems a MIMO/SA development platform has been developed. It comprises a MIMO real-time channel simulator and a receiver unit. The real-time channel simulator uses a geometry based stochastic channel model
(GSCM) proposed by COST 259 [2] to simulate MIMO
channels accurately and in real-time. The MIMO/SA
receiver allows rapid prototyping and real-time evaluation of MIMO/SA algorithms.
The hardware of the development platform is made
up of an expandable architecture of up to ten parallel
processing boards. The DSP-boards combine the versatility of a DSP with the raw power of a FPGA and offer
a performance of up to 12000 MIPS. Together with an
analog I/O board for RF and IF signals, the DSP-board
is ideally suited for software defined radios (SDR).
Index Terms Smart Antennas, MIMO, Channel
Modelling, Real-time Simulation, Software Defined Radio

crease the capacity of mobile communication systems

by using spatial multiplexing of signals. If the number
of antennas is the same on the sender and the receiver
side, it can be shown that the capacity increases with
the number of antennas [4].
To simulate smart antennas as well as MIMO systems in real-time, a MIMO/SA development platform
has been developed. The whole system is formed by
an expandable architecture of eight parallel processing boards (DSP-boards) for channel simulation, and
by one or two receiver boards, which operate with up
to eight antenna signals. The development platform is
subject of section III.
The DSP-boards were designed especially for the
use in software defined radios (HW/SW co-design)
[5]. They combine the versatility of a DSP with
the raw power of a FPGA. The DSP is capable of
handling complex algorithms at high speeds while
the FPGA can accelerate many tasks using parallel
computations and handle fast external data I/O easily. Each DSP-board can be equipped with its own
analog I/O-board with separate inputs for digital, analog, RF and IF signals and thus forming an ideal SDR
transceiver. A detailed description of the hardware
architecture can be found in section II.

I. I NTRODUCTION
Smart antennas use antenna arrays to reject interference and to improve system capacity in mobile
communication systems. Multiplying the signals received at the different antenna elements with complex
weights and summing them up (combining) results
in the characteristic beamforming pattern. By using
adaptive algorithms to compute the weighting factors
, the antenna system induces a sensitivity maximum
in the direction of the desired signal and nulls out the
interferer signals. For a good overview of smart antennas see [3].
MIMO Systems employ antenna arrays on the
sender as well as on the receiver side. They can in-

The testing and evaluation of MIMO/SA algorithms requires a very accurate channel model. The
geometry based stochastic channel model (GSCM)
proposed by COST 259 [2] for MIMO systems shows
promising results when compared to real world measurements. A brief description of the model and its
implementation on the DSP-boards will be given in
section IV-A.
Finally, in section IV-B the implemented receiver
algorithms and the optimized distribution of these algorithms to the hardware resources is explained. This
implementation can also be used as a framework for
the rapid prototyping of new MIMO/SA algorithms.

II. T HE P ROCESSING B OARDS

At the heart of the MIMO/SA development platform are the DSP-board and its analog I/O board.
They will be described in the following sections.
A. The DSP Board
The DSP-board uses two main computational components: A Texas Instruments TMS320C6416 DSP
(Digital Signal Processor) and a Xilinx Virtex2
XC2V2000 FPGA (Field Programmable Gate Array).
Further a Motorola Coldfire CPU is available. A
block diagram of the DSP-board can be found in figure 1.
16 MByte
SDRAM

Xilinx Virtex 2
XC2V2000

USB 1.1
Transceiver

USB
C onnector

RS232
Transceiver

6-pin
Western
C onnector

Ethernet
Transceiver

RJ45
C onnector

DSP
TMS320C6416
(600 MHz)

32 MByte
SDRAM

EMIF A

4 MByte
Flash ROM

512 MByte
SDRAM
(SO-DIMM)

32 Bit Memory Bus

EMIF B

96 P in Connector; Power Supply 5V

2 MByte
Flash ROM
dig. Out or
LVDS

Motorola Coldfire
MCF5272

Fig. 1. Block diagram of the DSP-board

The DSP uses 4 MByte Flash-ROM to store its own

applications and the configuration files of the FPGA.
In addition to its internal 1 MByte Cache/RAM it is
equipped with 32 MByte external RAM (expandable
to 512 MByte using a standard SO-DIMM). Clocked
at 600 MHz it is capable of executing up to 4800
MIPS and offers hardware-support for problems commonly found in signal processing, most notably a
Viterbi Decoder and a Turbo Decoder.
The FGPA contains 2 million system gates and
56 dedicated 18-bit x 18-bit multipliers that provide
computing power roughly equivalent to 3200 MIPS
(measured using the UMTS channel simulator presented in section IV-A).
It also features a total of 624 I/O pins, that can be
configured to comply to different interface standards,
and can be used in pairs for LVDS (Low Voltage Differential Signaling) at up to 400 Mbit/sec/pair, or as
general, high speed I/O pins. Although the FPGA
is the centerpiece of the board design and many of
its I/O pins are used for internal purposes (data- and
address-busses to the DSP and CPU, various control
signals), it still offers enough freely usable pins to
implement six external LVDS links (usable as input
or output; compliant to the ChannelLink standard,
each using six LVDS pairs for data transmission and

one LVDS pair for synchronization, for up to 2400

Mbit/sec/link). Two of these links are implemented
as standard ChannelLink connectors and accessible at
the front panel while the remaining four are linked to
the 96 pin connector at the back panel, which also
provides pins for synchronization, power supply, and
detection of logical board position.
It is worth noting that every LVDS channel can provide its own clock that doesnt need to be synchronized with any other LVDS clocks. The FPGA contains eight clock managers, making it possible to receive each LVDS channel with its own timing.
In addition to the two chips dedicated to data processing a Motorola XCF5272VF66 Coldfire CPU is
available. It is clocked at 66 MHz and provides support for Fast Ethernet, USB 1.1 and RS232 and is thus
used as a communication subsystem to exchange data
with the controlling PC without burdening the computation components with the overhead and complexity of external interfaces. The Coldfire is equipped
with 2 MByte of Flash-ROM and 16 MByte of RAM.
Since the FPGA and the DSP do not run any operating system, any communication would have to
be hand coded by the application programmer. The
Coldfire on the other hand, runs a copy of Clinux, a
slim edition of Linux, that has been trimmed down to
fit the needs of embedded devices (low memory footprint, low processing capacity, no MMU (Memory
Management Unit)). Even though the entire Clinux
is just a few hundred KByte in size, it still retains its
communication subsystem, so writing TCP/IP based
applications for data exchange with external systems
is very convenient.
Both the DSP and the Coldfire have their own, separate Flash- and RAM-Memory. It is not possible
for the Coldfire to directly access the DSPs memory
or vice-versa. Communication between the components takes place by means of a dual-ported RAM
(DPRAM), that is implemented in the FPGA and that
can be accessed via separate busses from the DSP and
the Coldfire.
The components are mounted on a 12-layer printed
circuit board (PCB). Great care has been taken to ensure proper shielding of high frequency signal and
compatibility with relevant EMC (Electro Magnetic
Compatibility) standards. At least one GND/Vcc
layer is used after two signal layers.
B. The Analog I/O Boards
To make the DSP-board usable with a broad range
of signal sources and receivers, we also plan to equip

each DSP-board with a analog I/O board for input and

output of RF and IF signals. The AEROFLEX1 PXI
3020 Digital Generator can be used as a transmitter,
the AEROFLEX PXI 3030 RF Digitizer as a receiver
and the AEROFLEX PXI 3010 RF Synthesizer as an
oscillator for both modules. The AEROFLEX PXI
modules provide real time LDVS digital IQ or IF output resp. input and are thus ideally suited for use with
the DSP-board.
The signal generator provides a frequency range
from 250 MHz to 2.5 GHz and an output level range
of -120 to +5 dBm. The digitizer provides a frequency
range from 300 MHz to 3 GHz, a digitized bandwidth
of 15 MHz and a 14 bit A/D-conversion with 61,44
MHz sampling rate.
III. T HE D EVELOPMENT P LATFORM
The hardware of the MIMO/SA development platform is formed by a real-time MIMO channel simulator comprising eight DSP-boards, and by a receiver
unit comprising two DSP-boards and two extension
boards that can handle up to eight antenna signals.
Both units can be integrated in one rack that also provides power supply and cooling.
The development platform is controlled over Fast
Ethernet by a Graphical User Interface (GUI) running on a PC or laptop. Input signals can either be
generated on the DSP-boards or they can be feed in
the DSP-boards directly. Up to now, the development
platform only has in- and outputs for digital baseband
signals, but an extension to RF and IF signals is under
development as pointed out in section II-B. Figure 2
shows a picture of the development platform.
A. MIMO Channel Simulator
In a n m MIMO scenario, n m DSP-boards are
needed. One board is used for each channel, computing the signal distortion (effects of fading, phase shift,
multi- path propagation) for one sender-receiver pair.
For the channel simulator, the two ChannelLink
connectors at the front side of the DSP-boards are
used for digital baseband input (BB-in) and output
(BB-out) respectively. The DSP-boards are connected
to a backplane (via the 96 pin connector) that supplies
global synchronization signals and a LVDS daisy
chain (2400 MBit/sec) for board-to-board communication.
Channels leading to the same output have to be calculated by adjacent boards. The output signals of
1

http://www.aeroflex.com

Fig. 2. Development Platform

Fig. 3. MIMO 2 4 scenario and the corresponding configuration of development platform.

each of board in this group are routed through the

LVDS daisy chain of the backplane to the the last
board of the group, where they are combined and output to the BB-out connector at the front side.
In addition to the LVDS daisy chain, the backplane
features two LVDS-channels (one input, one output)
accessible at the rear side of the rack using standard
ChannelLink connectors. Those connections have to
be used, if the user wants to provide his own digital
baseband input signals. By connecting outputs and
inputs at the rear side of the rack it is possible to configure different MIMO scenarios (8 1, 4 2, 2
4, 1 8 with eight boards).
The user input signals are replicated at the BB-out
connectors at the rear side, so that the input signal
can be looped through to all the boards that simulate
a channel originating at the same antenna. So to configure a 4 2 MIMO scenario, for example, the inand outputs at the rear side of the rack have to be connected like depicted in figure 3.
Larger MIMO scenarios: The total system size
of the development platform is not limited by the

capacity of a rack. Larger systems can be built by

using stacks of up to eight racks, where up to 64
(88) DSP-boards form a uniform pool of computing
resources (with completely transparent rack-to-rack
boundaries). With those systems it is possible to simulate MIMO scenarios with up to eight transmit and
receive antennas (8 8).
It is worth to point out, that such a cluster of
64 DSP-boards provides a total peak performance of
0.75 TeraOP/sec and a total communication peak performance of 450 GBit/sec.

Line-of-Sight Path

Near
Scatterer

Base
Station
Mobile Station

Near Cluster

Macro cell
Far Cluster

B. Receiver Unit
For the receiver unit, the two DSP-boards are complemented with two extension boards providing additional LVDS input channel connectors at the racks
front. Both the DSP-boards and the extension boards
are connected to the backplane. The input signals
from the extension boards are directly routed to the
receiver board without any processing.
IV. S OFTWARE A RCHITECTURE
The software consists of the implementation of the
channel model and the receiver. At the moment only
the GSM standard is supported. Extension of the software for systems like EDGE, UMTS, W-LAN and
Bluetooth standards is currently under development.
For the channel model in the MIMO/SA development platform the geometry based stochastic channel model (GSCM) proposed by COST 259 [2] was
chosen, since only a geometrical channel model can
simulate MIMO scenarios realistically. However, it is
also possible to implement other channel models or
even use channel sounder measurements for channel
simulation.
Section IV-A outlines the principles of the GSCM
and its real-time implementation on the DSP-boards
[6]. Section IV-B shows a framework how receiver
algorithms can be implemented on the development
platform.
A. MIMO Channel Simulator
According to COST 259, scatterers are arranged in
clusters, comprising a Near Cluster (NC) representing
the immediate Mobile Station (MS) surrounding, and
several Far Clusters (FC). Clusters are uniformly distributed within a radio cell as well as scatterers within
a cluster. Assuming specular reflection at the scatterers, raytracing is used to compute the multipath components created by the scatterers (see Figure 4).

Far Scatterer

Fig. 4. Modelling of signal propagation for GSCM

The signal at the output of each channel simulator can be calculated as superposition of the weighted
multipath components (MPC). A special FPGA module, called Channel Engine, performs the core tasks
of the channel simulation (phase shifts and fading for
each propagation path, summation of the partial results) efficiently by using extensive parallelism.
Calculation of phase delays and fading factors as
well as the position of the scatterers is done by the
DSP. The calculation is not carried out for each symbol (3.67s for GSM and 260ns for UMTS), because this would drastically exceed available computing power even of todays fastest processors. As
a consequence, the calculation is split in a small scale
update and a large scale update.
The large scale update updates the positions of the
scatterers according to the stochastic properties of the
channel model and thus simulates long term fading.
Since those values are varying significantly only after a MS movement of some wave lengths they are
refreshed every 40 timeslots.
The small scale update updates the phase delays
and fading factors for all MPCs and thus corresponds
to the geometrical part of the channel model. It occurs every timeslot, since those values are varying
very fast even when the MS is moving only a fraction of a wavelength. To simulate short term fading,
linear interpolation between the computed values is
performed.
B. MIMO/SA Receiver
Various algorithms for MIMO and smart antenna
receivers have been proposed in literature. See, for
example [7] for a MIMO algorithm and [8] for a

smart antenna algorithm. Most of the algorithms are

computationally expensive, since they include a lot of
matrix operations and filters. The special HW/SWcodesign of the DSP-board makes it ideally suited
for these kinds of algorithms. The following paragraphs outline how a MIMO/SA receiver can be implemented on the DSP-board.
The digitized baseband signals are feed in the DSPboard over LVDS, where they are received by the
FPGA and stored in a buffer. Optionally the FPGA
can also perform pre-processing like AGC (automatic
gain control) or complex derotation. One FPGA can
handle up to six LVDS channels. If more channels are
necessary a second DSP-board has to be employed.
The DSP transfers the data from the FPGAs buffer
via direct memory access (DMA) over the EMIF-B
memory interface in its local memory. Then it executes the MIMO/SA algorithms to calculate the combiner weights and the combined impulse response of
the channel. The combining of the signals (complex
multiplication and addition) is also done in the DSP.
Finally the DSP detects the data out of the combined
signal with the help of one of its powerful coprocessors (e.g. the Viterbi coprocessor for GSM).
The detected data is then made available for the
CPU, which sends it to the PC over Fast Ethernet. On
the other hand the CPU receives parameters and control commands from the PC and passes them to the
DSP.
V. OTHER A PPLICATIONS
Due to the flexible design of the DSP-board the development platform can also be used for a broad range
of other software defined radio applications. In this
section, we will outline some of those concepts.
Together with the HF-frontend the development
platform can also be used as a channel sounder.
Therefore the external RAM of the DSP boards has
to be expanded to the maximum of 512MByte. The
digitized baseband signals are received in the same
way as pointed out in section IV-B, but are stored in
the external RAM. When the RAM is full, the channel sounder has to stop recording and transfer the data
over Gigabit Ethernet to a PC. As a signal source the
PXI 3020 Digital Generator can be used.
The communication subsystem and the Fast Ethernet connections on the DSP-board makes it easy to interconnect the DSP-boards to a cluster. Such a cluster
could be used as a number cruncher for signal processing or general purpose applications. As already
pointed out at the end of section III-A, the aggregated
computing power of such a cluster of 64 DSP-boards
reaches 0.75 TeraOPS.

VI. C ONCLUSIONS AND O UTLOOK

We have presented a development platform for
MIMO systems and smart antennas, which contains
a MIMO channel simulator and a MIMO/Smart Antenna receiver unit. This tool eases the design process
for MIMO systems and smart antennas from the algorithm development to the end product.
The hardware of the development platform is made
up of highly flexible and scalable DSP-boards, that
combine the versatility of a DSP with the raw power
of a FPGA and offer a performance of up to 12000
MIPS. Equipped with an analog I/O board the DSPboards can also be used as an software defined radio
(SDR) transceiver.
Future plans include the development a Matlab/
Simulink interface for the development platform. The
interface makes it possible to develop MIMO/smart
antenna algorithms in Matlab or Simulink and evaluate them with the MIMO channel simulator. The entire process is fully transparent to the user who is not
forced to change his accustomed workflow, but will
enjoy significant speedups in the computation of his
simulations.
R EFERENCES
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TSG, Tech. Rep. 3GPP-TSG-RP-030571, 3GPP-3GPP2,
Hawaii, Dec. 2003. [Online]. Available: www.3gpp.org
[2] Louis M. Correia, Ed., Wireless Flexible Personalised Communications, Wiley, 2001.
[3] W. Schuttengruber, A.F. Molisch, and E. Bonek, Smart
antennas for mobile communications, Internet Tutorial,
2001. [Online]. Available: www.nt.tuwien.ac.at/
mobile/research/
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311335, 1998.
[5] G. Humer and G. Pfeiffer, Hardware platform for software
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[6] G. Humer, R. Kloibhofer, G. Pfeiffer, and G. Steinbock,
COST 259 channel model implementation for real-time
simulation, in Proceedings of the COST 273 Meeting,
Prague, Sept. 2003.
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