Institut f

ur Integrierte Systeme
Integrated Systems Laboratory

Analog Integrated Circuits

Exercise 6: Layout
Danny Luu ETZ J61, Xu Han ETZ J64.2
Hand out: 05.12.2014

The exercise takes place in room ETZ D61.1 on 5th and 12th of December. The exercise
starts at 13:15 and ends at 15:00.

1 Introduction
From Exercise 2 to Exercise 5, we have calculated different circuits, and simulations are used to guarantee the specifications. Now, the designers of Analog IC must convert the schematic into a physical chip.
For that, a so-called layout must be generated, which will be used as photolithography masks during the
fabrication of the chips.
In this exercise, a finished layout of a simple amplifier (OTA) is provided, and it will be analyzed and
compared with the associated schematic. For the layout, certain geometrical rules (Design Rules) must
be satisfied, e.g. minimum width and minimum spacing. A program (DRC=Design Rule Check) can
be used to check the Design Rules and announce possible errors. Furthermore, it must be guaranteed
that the schematic and the layout represent the same circuit. In order to do this, the layout should be
extracted firstly. A program (Extractor) looks into the layout to extract electrical devices (transistors, resistors, capacitors) and generate a netlist from it. Secondly, with a further program (LVS=Layout Versus
Schematic) this netlist is compared with the netlist of the schematic and is examined for agreement.

2 CMOS Process
In this exercise, a 0.35m CMOS process with four metal layers and two polysilicon layers is used.
The minimum channel length of the transistors is 0.35m. With four metal layers low impedance
connections can be implemented. Usually, the polysilicon is used only for the gates of transistors,
since its resistance is much higher than the metals. As here in the special case of two polysilicon layers,
the second layer is used for poly-poly capacitors only.
Figure 1 shows the cross section of an NMOS (left) and a PMOS transistor (right). All transistors are
fabricated in a weakly doped p-type substrate (p-), which also forms the bulk connections of all NMOS
transistors. Drain and source of the NMOS transistor consist of two heavily doped n-type (n+) regions.

Figure 1: The symbol, cross section and layout of MOS transistors

The channel is under the Polysilicon gate. In addition, contacts must be etched in the isolating oxide to
connect diffusions with metals.
Underneath the cross section, the layout of the corresponding transistors is shown (top view). It consists
of the drain and source diffusions (light gray), the polysilicon gate (dark gray), the contacts (black)
and the metal leads for drain and source (transparency). In contrast to the NMOS transistor, the PMOS
transistor lies additionally in a weakly doped n-type well (n-), while the drain and source diffusions are
heavily doped (p+).
Because of the weakly doping, the p-substrate conduction is poor. So everywhere in the substrate, it is
necessary to add many substrate contacts and connect them with metal directly. The same applies to the
n-well, too. In addition, consider that in the cross section of Figure 1 not only MOS transistors, but also
some unwanted diodes (pn junction) exist. These diodes must be reversed biased to prevent them from

conducting. Therefore, the substrate is always connected to the lowest potential of the circuit, and the
n-wells are usually connected to the highest potential.
Besides MOS transistors, resistors and capacitors can also be integrated. In this exercise, we will concentrate on MOS transistors only. Bipolar transistor (BJT) needs further process steps and thus also
further masks, so it cannot be integrated in an ordinary CMOS process.
Remark: Although a MOS transistor consists of separate diffusion areas for drain and source, only a
large diffusion is drawn in the layout, which covers the channel together with drain and source. The
reason for this lies in the fabrication process. In a modern CMOS process, the polysilicon gates is
deposited firstly, and then the wafer is exposed to a dopant source. So, the gate acts as barrier and
prevents the channel from doping. The advantage of this procedure is that the channel is always exactly
under the gate, even if the mask is slightly shifted.

3 Design Rules
As was already mentioned in the preceding section, the minimum channel length of the transistors is
equal to 0.35m. This length is determined by the chip manufactory (wafer foundry). With shorter
channel length, more transistors can be integrated, which is favorable for very large circuits (microprocessors, memorys, etc.) and high speed circuits.
In Table 1 the minimum widths and spacings within the same mask are listed for all masks. The data
are all in micrometers. Figure 2 contains some geometrical rules for the masks among themselves.
Mask
n-Well
Diffusion
n+ Diffusion
p+ Diffusion
Polysilicon 1
Polysilicon 2
Contact
Metal 1
Via 1
Metal 2
Via 2
Metal 3
Via 3
Metal 4

Abbreviation
NTUB
DIFF
NPLUS
PPLUS
POLY1
POLY2
CONT
MET1
VIA1
MET2
VIA2
MET3
VIA3
MET4

Minimum Width
1.7
0.3
0.6
0.6
0.35
0.65
0.4
0.5
0.5
0.6
0.5
0.6
0.5
2.5

Minimum Spacings
1
0.6
0.6
0.6
0.45
0.5
0.4
0.45
0.45
0.5
0.45
0.6
0.45
2

Table 1: Minimum widths and spacings of the masks

For n+ and p+ diffusion, three masks are needed. The n+ diffusion must be drawn with the masks
DIFF and NPLUS, and the p+ diffusion must be drawn with DIFF and PPLUS. Three masks for only
two diffusion types may be strange, however, in most CMOS processes this is a normal case.

Figure 2: Additional design rules for transistors, contacts, metals and vias

Mask Via 1 defines connections between Metal 1 and Metal 2, and Via 2 defines connections between
Metal 2 and Metal 3.

4 Layout Editor
In this section the layout editor will be introduced. On the basis of a finished layout, simple operations,
e.g., zoom in/out and fading in/out different layers will be presented.
In a terminal, enter the following commands:
cp -r ~aic 00/uebung6 .
cd uebung6
icdesign&
Start the Design Framework II and open the library manager. If you dont see the library ueb6 in your
library manager, contact an assistant. Open the the layout view of the cell ota from the library ueb6.
This will open a window, which is shown in Figure 3, containing the layout of the circuit and the layer
selection window (LSW) on the left.
Possibly, in the layout window, not all hierarchy levels are displayed. In order to display these levels,
open the display option form with the command Options.Display... and modify the Stop value
of Display Levels from 0 to 20. Alternatively, use Shift + f and Ctrl + f to toggle between showing
all hierarchy levels or top level only.
The LSW may include some layers (masks) which are not needed at all. From the LSW dropdown
menu (see Figure 3) select Layer Set.Import... to import the file ueb6Layers.layerSet. Now,
the LSW contains only the layers listed in the Table 1 and the pin layers. With the help of the LSW,
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Figure 3: Layout view of the circuit with layer selection window (LSW).

arbitrary layers in the layout window can be made visible or invisible. In the LSW, click the layer POLY1
with the left mouse button. Now it is dark bordered, which means that POLY1 is the active layer (if we
draw something now, then this would be in POLY1). When you click the NV (None Visible) button, the
background of all layers except the active layer is grayed in the LSW. The inactive layers are faded out
in the layout window and only POLY1 is visible. In the LSW, with the left mouse button, selected layers
can be made visible again. Try this for some layers. Click the AV (All Visible) button, all layers become
visible again.
Zooming the layout view works similar as in the schematic view:
Zoom In/Out: mouse wheel
Zoom In: Draw a rectangle with the right mouse button pressed
X-Axis Scroll: Shift + mouse wheel
Y-Axis Scroll: Ctrl + mouse wheel
Fit all: f
You can arbitrarily detail the editing layout. Often, it is necessary to know the exact dimensions. Here
exists a useful command Tools.Create Ruler k to measure dimensions in the layout window.
Use Shift + k to clear all rulers. The layout editor also provides a multiplicity of further functions. For
example, you can test the function of the arrow keys in the layout window.
With the commands described above, the problems of the following section can be solved.

5 Layout Analysis
In this section a finished layout is to be analyzed and be compared with the schematic in Figure 4. Use
the commands from the preceding section (zoom in/out, ruler and layer fade in/out).
Solve the following problems and annotate the results in the layout of Figure 4.

Problems:
1. Find all transistors (Hint: Crossing of the layer POLY1 and the layer DIFF forms a transistor)
2. Differentiate the NMOS transistors from the PMOS transistors (Hint: PMOS transistors lie in a
n-well)
3. Determine the sizes of all transistors (W/L)
4. Compare the found W/L with the schematic. Obviously, the layout has more transistors than the
schematic. Why is that possible? (Hint: A transistor can consist of several fingers in the layout).
5. Assign all transistors in the layout to the transistors in the schematic. Use the numbering used in
the schematic (M0, M1, M2, . . . )
6. Give the number of fingers for all transistors (you can use the table in Figure 4)
7. The geometrical structure of the differential pair M1, M2 is called common centroid. Consider
yourself, why such an arrangement is favorable for the offset of OTAs.
8. The bulk of the NMOS transistors is the p-substrate and must be connected to the lowest potential,
thus to VSS (why?). Find the substrate contacts. Why do the substrate contacts lie in the proximity
of drain and source of the transistors if possible?
9. The bulk of the PMOS transistors is the n-well. It must be connected to a high potential (why?).
Find the n-well contacts. The n-well contacts lie in the proximity of drain and source, too.

Figure 4: Schematic and layout of the OTA

6 Layout Drawing
In the previous section, a finished layout was analyzed. Now, you will draw your own layout for the same
schematic (Figure 4). In order to simplify the layout, common centroid is not used for the differential
pair, and the W/L of the transistors remains the same. M1, M2 and M0 are to exhibit four fingers,
M3M6 and M9 two fingers and M7, M8 one finger.

Create a new layout in the library ueb6, with the cell name myota and the type layout. Firstly, you
shall draw the transistors. Fortunately, the software saves a large part of work we need to do. The
transistors can be generated with Create.Instance... i . Browse for the desired component.
The MOS transistors are in the library PRIMLIB. The cell name is nmos4 and pmos4, and the view
name is layout. Enter the width, length and number of fingers (number of gates). With the left mouse
button, the transistor can be placed in any desired location.
Generate all transistors with correct W/L and the indicated number of fingers. You may want to rotate
certain transistors. Select the transistor and open the Properties with Edit.Basic.Properties
q . In the Attribute tab, you can change the rotation angle of the instance and in the Parameter tab,
you can modify the transistor dimensions. In addition, the selected transistors can be deleted with
Edit.Delete Del .
After you placed all transistors, you can store your layout with File.Save.
The transistors must be electrically connected now. For this, layers Metal1, Metal2, and Metal3 should
be used. Metal4 is a thick metal and not intended for local interconnections. In the LSW, select Metal1,
Metal2 or Metal3 (with the left mouse button, the selected layer will be dark bordered), and draw a
rectangle with Create.Shape.Rectangle r . A more comfortable alternative for interconnections
is to use the so-called Path Create.Shape.Path p . It does not matter for the layout whether
rectangles or paths are drawn.
In order to connect the different transistors, you also need to place contacts and vias. Poly1-gates and
diffusion areas must be connected with Metal1 by contacts and the different metals are connected by
vias. As in the case of transistors, contacts and vias can also be generated automatically. You can use
the command Create.Via... o . There are several different contact and via types. P1 C can be
used to connect Poly1 and Metal1, PD C is used to connect p+ diffusion and Metal1, ND C is used to
connect n+ diffusion and Metal1, VIA1 C is used to connect Metal1 and Metal2, and VIA2 C is used to
connect Metal2 and Metal3.
Finally you need to specify the input and output ports where the circuit will be connected to the surrounding environment. The way to do this depends on the toolkit being used. In the setup used here, it
is sufficient to place labels using the PIN layer. For example if a wire on Metal3 connects to the output
of the circuit, you have to create a label by Create.Label... l , give it a name, select the PIN
layer with subtype Metal3 (PIN|M3) and place it on top of the wire. Make sure that the crosshair of the
label is inside the metal area. There is no option to specify whether a label represents an input or output
port. Place labels in the layout view with exactly the same names as the pins in the schematic view of
the circuit.
When drawing the layout, pay attention not to violate the design rules. Accomplish regularly design rule
check and you can correct the errors promptly. The checker can be started with Assura.Run DRC.
Fill in the DRC form in accordance with Figure 5 (Notice the Switch Names!). Press OK to start the
DRC and confirm if there are windows asking about overwriting previous results. Wait until the DRC
run has completed successfully (if not, ask an assistant) and have a look at the results. The violated
design rules are listed in the left part of the Error Layer Window (ELW). You can browse the individual
violations by clicking on the left-/right-arrow buttons on top of the right part of the ELW. The violation
will then also be highlighted in the layout view.

Figure 5: Design rule check form

Problems:
Finish all connections in the layout. Connect the substrate and the n-well (or possibly, the n-wells) with
VSS or with VDD. Examine the layout with the design rule checker to see whether all design rules are
satisfied.

7 Verification
After the layout was drawn and has no design rule errors, it should be verified that it is matched with
the schematic. As previously mentioned, this verification is divided into two steps. In the first step, a
program, named the extractor, looks into the layout for components and analyzes the connections between the individual components. The result is a netlist. In the second step, a further program compares
this netlist with the netlist of the schematic for agreement. This program is called LVS (Layout Versus
Schematic).
The LVS can be started with Assura.Run LVS.... Fill in the form in accordance with Figure 6.
Then you can run the LVS by clicking OK in the LVS form. After the comparison is completed, a

Figure 6: LVS Form

result summary will appear. The wonderful thing is Schematic and Layout Match in this window,
which means that there are no discrepancies between layout and schematic. Otherwise, you must locate
and correct the errors. Sometimes, this is very time intensive especially for larger circuits. The software
offers some support, however, that will not be treated in this exercise. Who is interested in the details, can
consult the documentation in the Cadence. You can evoke it by using the command Help.Virtuoso
Documentation.

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