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1. General description
The 74LVC2G34 provides two buffers.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
74LVC2G34
NXP Semiconductors
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC2G34GW
40 C to +125 C
SC-88
SOT363
74LVC2G34GV
40 C to +125 C
TSOP6
SOT457
74LVC2G34GM
40 C to +125 C
XSON6
74LVC2G34GF
40 C to +125 C
XSON6
74LVC2G34GN
40 C to +125 C
XSON6
SOT1115
74LVC2G34GS
40 C to +125 C
XSON6
SOT1202
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC2G34GW
YA
74LVC2G34GV
Y34
74LVC2G34GM
YA
74LVC2G34GF
YA
74LVC2G34GN
YA
74LVC2G34GS
YA
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
1Y
2A
2Y
Logic symbol
74LVC2G34
mnb064
mnb063
Fig 1.
Fig 2.
Y
001aac536
Fig 3.
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74LVC2G34
NXP Semiconductors
6. Pinning information
6.1 Pinning
74LVC2G34
74LVC2G34
1A
1A
1Y
GND
VCC
1Y
GND
VCC
2A
2Y
2A
2Y
Fig 5.
1Y
GND
VCC
2A
2Y
1A
001aag030
001aab677
001aab676
Fig 4.
74LVC2G34
Fig 6.
Pin description
Symbol
Pin
Description
1A
data input
GND
ground (0 V)
2A
data input
2Y
data output
VCC
supply voltage
1Y
data output
7. Functional description
Table 4.
Function table[1]
Input
Output
nA
nY
[1]
74LVC2G34
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74LVC2G34
NXP Semiconductors
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
VI
input voltage
IOK
VI < 0 V
[1]
IO
output current
ICC
supply current
IGND
ground current
Ptot
Tstg
storage temperature
Min
Max
Unit
0.5
+6.5
50
mA
0.5
+6.5
50
mA
Active mode
[1][2]
0.5
VCC + 0.5
Power-down mode
[1][2]
0.5
+6.5
50
mA
100
mA
100
mA
250
mW
65
+150
output voltage
VO
[1]
Conditions
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For SC-88 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
Symbol
Parameter
VCC
Conditions
Min
Typ
Max
Unit
supply voltage
1.65
5.5
VI
input voltage
5.5
VO
output voltage
Active mode
VCC
5.5
40
+125
20
ns/V
10
ns/V
Tamb
ambient temperature
t/V
74LVC2G34
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NXP Semiconductors
VIH
LOW-level
input voltage
VIL
VOH
40 C to +85 C
Conditions
VCC = 1.65 V to 1.95 V
Min
Max
Min
Max
Unit
0.65VCC
0.65VCC
1.7
1.7
2.0
2.0
0.7VCC
0.7VCC
0.35VCC
0.7
0.7
0.8
0.8
0.3VCC
0.3VCC
VCC 0.1
VCC 0.1
1.2
0.95
HIGH-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
0.35VCC V
1.9
1.7
2.2
1.9
2.3
2.0
3.8
3.4
0.10
0.10
0.45
0.70
LOW-level
VI = VIH or VIL
output voltage
IO = 100 A;
VCC = 1.65 V to 5.5 V
VOL
40 C to +125 C
Typ[1]
0.30
0.45
0.40
0.60
0.55
0.80
0.55
0.80
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
0.1
20
IOFF
power-off
leakage
current
VCC = 0 V; VI or VO = 5.5 V
0.1
10
20
ICC
0.1
10
40
ICC
additional
per pin; VCC = 2.3 V to 5.5 V;
supply current VI = VCC 0.6 V; IO = 0 A
500
5000
CI
input
capacitance
2.5
pF
[1]
74LVC2G34
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74LVC2G34
NXP Semiconductors
40 C to +85 C
Conditions
power dissipation
capacitance
CPD
Unit
Min
Max
Min
Max
1.0
3.8
8.6
1.0
10.8
ns
0.5
2.4
4.4
0.5
5.5
ns
VCC = 2.7 V
0.5
2.5
5.0
0.5
6.3
ns
0.5
2.2
4.1
0.5
5.1
ns
0.5
1.9
3.2
0.5
4.0
ns
20
pF
[2]
tpd
40 C to +125 C
Typ[1]
[3]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
[3]
12. Waveforms
VI
nA input
VM
VM
GND
tPLH
tPHL
VOH
VM
nY output
VM
VOL
mnb072
Fig 7.
74LVC2G34
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74LVC2G34
NXP Semiconductors
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5VCC
0.5VCC
2.3 V to 2.7 V
0.5VCC
0.5VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VEXT
VCC
VI
RL
VO
DUT
RT
CL
RL
mna616
Fig 8.
Table 10.
Supply voltage
Input
Load
VEXT
VCC
VI
tr = tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
2.0 ns
30 pF
1 k
open
2.3 V to 2.7 V
VCC
2.0 ns
30 pF
500
open
2.7 V
2.7 V
2.5 ns
50 pF
500
open
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
open
4.5 V to 5.5 V
VCC
2.5 ns
50 pF
500
open
74LVC2G34
7 of 17
74LVC2G34
NXP Semiconductors
SOT363
HE
v M A
pin 1
index
A1
2
e1
bp
c
Lp
w M B
detail X
2 mm
scale
A1
max
bp
e1
HE
Lp
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT363
Fig 9.
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
74LVC2G34
8 of 17
74LVC2G34
NXP Semiconductors
SOT457
HE
v M A
pin 1
index
A
A1
c
3
Lp
bp
w M B
detail X
2 mm
scale
A1
bp
HE
Lp
mm
1.1
0.9
0.1
0.013
0.40
0.25
0.26
0.10
3.1
2.7
1.7
1.3
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT457
JEITA
SC-74
EUROPEAN
PROJECTION
ISSUE DATE
05-11-07
06-03-16
9 of 17
74LVC2G34
NXP Semiconductors
SOT886
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
b
1
3
4x
(2)
L1
5
e1
4
e1
6x
(2)
A1
D
terminal 1
index area
0
2 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
max
nom
min
A(1)
0.5
A1
e1
0.6
0.5
L1
0.35 0.40
0.30 0.35
0.27 0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
Outline
version
SOT886
sot886_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
04-07-22
12-01-05
MO-252
10 of 17
74LVC2G34
NXP Semiconductors
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
b
3
4
(1)
L1
e
5
e1
4
e1
(1)
A1
D
terminal 1
index area
0
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
e1
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
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74LVC2G34
NXP Semiconductors
SOT1115
b
3
(4)(2)
L1
e
e1
e1
(6)(2)
A1
terminal 1
index area
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
e1
0.3
L1
0.35 0.40
0.30 0.35
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1115_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1115
12 of 17
74LVC2G34
NXP Semiconductors
SOT1202
b
3
(4)(2)
L1
e
e1
e1
(6)(2)
A1
E
terminal 1
index area
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
e1
L1
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1202_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1202
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74LVC2G34
NXP Semiconductors
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
DUT
ESD
ElectroStatic Discharge
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
Revision history
Document ID
Release date
Change notice
Supersedes
74LVC2G34 v.7
20120704
74LVC2G34 v.6
Modifications:
74LVC2G34 v.6
Modifications:
20111129
74LVC2G34 v.5
74LVC2G34 v.5
20100902
74LVC2G34 v.4
74LVC2G34 v.4
20070720
74LVC2G34 v.3
74LVC2G34 v.3
20070321
74LVC2G34 v.2
74LVC2G34 v.2
20040910
Product specification
74LVC2G34 v.1
74LVC2G34 v.1
20030725
Product specification
74LVC2G34
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74LVC2G34
NXP Semiconductors
Product status[3]
Definition
Development
This document contains data from the objective specification for product development.
Qualification
Production
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC2G34
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74LVC2G34
NXP Semiconductors
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
74LVC2G34
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74LVC2G34
NXP Semiconductors
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section Legal information.