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ABSTRACT
This research presents the review of Analog to Digital Convertor (ADC). For ADC there are mainly four different methods,
Flash ADC, Pipelined ADC, Successive Approximation ADC, and Sigma Delta ADC. The Flash ADC is the Fast ADC. For
Designing the ADC, the parameters important are Static and Dynamic. In static parameters Differential Non Linearity Error
(DNLE), Integral Non Linearity Error (INLE) and in dynamic parameters Signal to Noise Ratio (SNR ), Effective Number of
Bits ( EONB ), Spurious-Free Dynamic Range (SFDR), Dynamic Range (DR). The design issues which consist first CMOS
inverter used in CDC architecture, MUX based Decoder and DAC.
1. INTRODUCTION
Analog to digital convertor circuit converts analog signal into digital signal. Analog signal is the signal whose
amplitude is continuously changing with respect to time. But in the digital signal the amplitude and time is discrete.
The ADC is characterized by three factor speed, area, and power consumption, the cost of ADC is varying from
application to application. For considering the speed of ADC we have to design the ADC with small voltage supply and
we have to shrink the size of ADC, for this application we are designing Flash ADC with Clocked Digital Convertor
(CDC) configuration which eliminates the resistive network required for generation of internal reference voltage [1-4].
Types of ADC
1. Sigma Delta ADC.
2. Successive Approximation Register (SAR) ADC.
3. Pipelined ADC.
4. Flash ADC.
Comparison between different ADC [5].
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2. RESEARCHES
2.1. Introduction to Analog to Digital Converter
Analog to digital converters are the basic building blocks that provide an interface between an analog world and the
digital domain. As it is the main block in mixed signal applications, it becomes a bottleneck in data processing
applications and limits the performance of the overall system. In this chapter we will give the introduction of a number
of A/D converter architectures. We will start from the basic definition of ADC then we will look into different
architecture of ADCs that include Flash, Sigma-Delta, Pipeline, Successive Approximation and Dual Slope ADCs. At
last we will compare the different architectures and will see the impact of CMOS technology on ADC architectures [2427].
2.2. ADC
Analog to Digital Converter (ADC) is a device that accepts an analog value (voltage/current) and converts it into
digital form that can be processed by a microprocessor. Figure 2, shows a simple ADC with two inputs and 8 output
bits. The signal that we want to convert into digital form is applied to input while the reference voltage should be
applied to VREF. The 8 bits at the output represents the input signal in digital form [28].
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places in many clock cycles. The other disadvantage of sigma-delta converter is the complexity in designing of the
digital filter that is used to convert duty cycle information into digital word [38].
2.3.3. Pipelined ADC
The pipelined analog-to-digital converter is one of the most popular ADC architecture. It can work from few mega
samples to more than hundreds of mega samples with resolution from 8 bit to 16 bits. Due to its high resolution and
sampling rate range it is widely use in medical and communication applications e.g. CCD imaging, ultrasonic medical
imaging, digital receiver, base station, digital video (for example, HDTV), xDSL, cable modem, and fast Ethernet [39,
40]. Speed, resolution, power and dynamic performance are greatly improved in Pipeline ADC but SAR and integrating
architectures are still used for low sampling rate applications, whereas for high sampling rate (e.g. 1 GHz) flash ADC
is still the choice. The block diagram of 12 bits pipelined ADC is shown in Figure 5.
Figure 5: Pipelined ADC with four 3-bit stages (each stage resolves 2 bits) [41].
Initially sample-and-hold (S&H) circuit, samples and holds the input VIN. The flash ADC in the first stage will convert
this signal into 3 bit digital output. This 3 bits digital code is applied to DAC and the analog output is subtracted from
the original signal, the remainder is then multiplied by 4 and then applied to the next stage. This process will continue
till the last stage (stage 4) and every stage provides 3 bits. After last stage the amplified remainder will feed into 4 Bit
flash ADC that will generate 4 least significant bits.
As every stage generates bits at different instant in time therefore it is required to align all the bits by shift register prior
to applying 12-bit digital output to the digital-error-correction logic. During the interval when one stage completes the
processing of one sample and passes the magnified remainder to the other stage. The next stages are also performing
the same operation because sample and hold circuit is embedded in every stage. This pipelining technique increases the
throughput.
2.3.4. Successive Approximation ADC
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are mostly use in medium to highresolution and low sampling rate applications. These are mostly in the range between 8 to 16 bits. It also provides low
power consumption and small form factor. As its power consumption is low therefore it is the good choice for low
power application such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal
acquisition [42, 43].
SAR ADC actually implements binary search algorithm, therefore its internal circuitry might work at several
megahertz but due to the successive approximation algorithm the sampling rate of ADC is quite small. There are many
ways to implement SAR ADC but its basic structure is shown in Figure 6.
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In this structure track/hold circuit is used to hold the analog input voltage (VIN). The binary search algorithm is
implemented by N-bits register. Initially the value of register is set to mid-scale i.e. MSB set to 1 and all the other
bits are set to 0. The output of DAC (VDAC) becomes half the reference voltage VREF/2, where VREF is the reference
voltage of ADC. The comparator will compare the input voltage, VIN with VDAC. If VIN is greater than VDAC, the
comparator output will be set to 1, and the MSB of the N-bit register remains at '1'. If the input voltage VIN is less
than VDAC, then the comparator output becomes 0. The SAR control logic will change the MSB of the register to '0',
set the next bit to 1 and perform comparison again. This process continues till LSB and once this process is
completed the N-bit digital word is available in the register [45].
2.3.5. Dual-Slope ADC
In order to understand the architecture of Dual slope ADC we first need to understand the concept of single slope ADC.
The single slope ADC is also known as integrating ADC and the main theme of this architecture is to use analog
ramping circuit and digital counter instead of using DAC. The op-amp circuit that is also called an integrator is used to
generate a reference ramp signal that will compare with input signal by a comparator. The digital counter clocked with
precise frequency is used to measure time taken by the reference signal to exceed the input signal voltage [46]. The
Dual-Slope ADC input voltage ( VIN ) integrates for fixed time interval ( TINT ), then it will de-integrate by using
reference voltage ( VREF ) for a variable amount of time ( TDE -INT) as shown in Figure 7 [47].
Ultra-High
Speed when
power
consumption
DUAL SLOPE
SAR
Medium to high
resolution (8 to
16bit),
(Integrating
ADC)
Monitoring DC
signals,
high
resolution, low
power
PIPELINE
SIGMA
DELTA
High resolution,
low to medium
speed,
no
precision
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not primary
concern?
consumption,
good
noise
performance
consumption than
flash.
ICL7106.
external
components,
simultaneous
50/60Hz
rejection, digital
filter
reduces
antialiasing
requirements.
3. DISCUSSION
ADC Parameters:
The parameters of an ADC can be obtained from the data sheet of ADC. The parameters are classified into two
categories.
1) Static Parameters
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pW p
V
V
nWn dd Tp Tn
Vm
pW p
1
nWn
Figure 13: Formula for Finding Internal Reference Voltage [50].
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where Vtn and Vtp are the threshold voltages for NMOS and PMOS devices, respectively; and Kn = (W/L)n . mn Cox
Kp = (W/L)p . mp Cox.
Multiplexer Based Decoder [51]:
The multiplexer based decoder circuit uses 2:1 Mux so we required 11 Mux for implementing 15 inputs. The 2:1 Mux
required two input signals with one select line, the select line should vary between two logics 0 to 1 depending on the
select line the Muxll transmit the logic, the truth table of 3 bit thermometer code itself expressing the logic the M.S.B.
bit of binary input equal to middle bit of thermometer code because it follows the twin logic.
Thermometer Code
Binary Code
T3
T2
T1
B2(MSB)
B1
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4.CONCLUSION
By considering all these we can design the 4 bit Flash ADC and find all the given parameters. Compare these
parameters with the standard parameters.
REFERENCES
[1] C. Mostafa and H. Qjidaa, "1 GS/s, low power flash analog to digital converter in 90nm CMOS technology," in
Multimedia Computing and Systems (ICMCS), 2012 International Conference on, 2012, pp. 1097-1100.
[2] M. El-Chammas and B. Murmann, "A 12-GS/s 81-mW 5-bit time-interleaved flash ADC with background timing
skew calibration," Solid-State Circuits, IEEE Journal of, vol. 46, pp. 838-847, 2011.
[3] M. Mishali, Y. C. Eldar, O. Dounaevsky, and E. Shoshan, "Xampling: Analog to digital at sub-Nyquist rates," IET
circuits, devices & systems, vol. 5, pp. 8-20, 2011.
[4] Y. Chae, J. Cheon, S. Lim, M. Kwon, K. Yoo, W. Jung, et al., "A 2.1 M Pixels, 120 Frame/s CMOS image sensor
with column-parallel ADC architecture," Solid-State Circuits, IEEE Journal of, vol. 46, pp. 236-247, 2011.
[5] J. Yoo, "A TIQ based CMOS flash A/D converter for system-on-chip applications," The Pennsylvania State
University, 2003.
[6] S. Fan, H. Tang, H. Zhao, X. Wang, A. Wang, B. Zhao, et al., "Enhanced Offset Averaging Technique for Flash
ADC Design," Tsinghua Science & Technology, vol. 16, pp. 285-289, 2011.
[7] J. I. Lee and J.-I. Song, "Flash ADC architecture using multiplexers to reduce a preamplifier and comparator
count," in TENCON 2013-2013 IEEE Region 10 Conference (31194), 2013, pp. 1-4.
Page 15
[8] A. Varzaghani, A. Kasapi, D. N. Loizos, S.-H. Paik, S. Verma, S. Zogopoulos, et al., "A 10.3-GS/s, 6-Bit Flash
ADC for 10G Ethernet Applications," 2013.
[9] J. Pernillo and M. P. Flynn, "A 1.5-GS/s flash ADC With 57.7-dB SFDR and 6.4-bit ENOB in 90 nm digital
CMOS," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 58, pp. 837-841, 2011.
[10] J.-I. Kim, W. Kim, and S.-T. Ryu, "A 6-b 4.1-GS/s Flash ADC with Time-Domain Latch Interpolation in 90-nm
CMOS," Solid-State Circuits, IEEE Journal of, vol. 48, pp. 1429-1441, 2013.
[11] Y.-D. Jeon, J.-W. Nam, K.-D. Kim, T. M. Roh, and J.-K. Kwon, "A Dual-Channel Pipelined ADC With Sub-ADC
Based on FlashSAR Architecture," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, pp.
741-745, 2012.
[12] A. Nicholson, J. Jenkins, A. N. Irfansyah, N. Politi, A. van Schaik, T. J. Hamilton, et al., "A 0.3 mm 2 10-b
100MS/s pipelined ADC using Nauta structure op-amps in 180nm CMOS," in Circuits and Systems (ISCAS),
2013 IEEE International Symposium on, 2013, pp. 1833-1836.
[13] G.-G. Oh, C.-K. Lee, and S.-T. Ryu, "A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating
Temperature for WAVE Applications," 2014.
[14] P. Huang, S. Hsien, V. Lu, P. Wan, S.-C. Lee, W. Liu, et al., "SHA-less pipelined ADC with in situ background
clock-skew calibration," Solid-State Circuits, IEEE Journal of, vol. 46, pp. 1893-1903, 2011.
[15] S. M. Hamed, A. H. Khalil, H. H. Amer, M. Abdelhalim, and A. Madian, "Testing of one stage pipelined Analog
to Digital converter," in Computer Engineering & Systems (ICCES), 2011 International Conference on, 2011, pp.
193-198.
[16] S.-Y. Baek, J.-K. Lee, and S.-T. Ryu, "An 88-dB Max-SFDR 12-bit SAR ADC with speed-enhanced ADEC and
dual registers," 2013.
[17] X.-L. Huang, P.-Y. Kang, H.-M. S. Chang, J.-L. Huang, Y.-F. Chou, Y.-P. Lee, et al., "A self-testing and
calibration method for embedded successive approximation register ADC," in Proceedings of the 16th Asia and
South Pacific Design Automation Conference, 2011, pp. 713-718.
[18] G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, "10-bit 30-MS/s SAR ADC using a switchback switching
method," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 584-588, 2013.
[19] C. Zhang and H. Wang, "Reduction of Parasitic Capacitance Impact in Low-Power SAR ADC," Instrumentation
and Measurement, IEEE Transactions on, vol. 61, pp. 587-594, 2012.
[20] M. Joseph, S. Sreelal, and J. J. Edathala, "End to end simulation of sigma delta ADC," in Emerging Research
Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy
(AICERA/ICMiCR), 2013 Annual International Conference on, 2013, pp. 1-4.
[21] S. Tao, S. Rodriguez, and A. Rusu, "Two-step continuous-time incremental sigma-delta ADC," Electronics Letters,
vol. 49, 2013.
[22] C. C. Lee and M. P. Flynn, "A 14 b 23 MS/s 48 mW resetting ADC," Circuits and Systems I: Regular Papers,
IEEE Transactions on, vol. 58, pp. 1167-1177, 2011.
[23] M. Yue, D. Wu, and Z. Wang, "Data Compression for Image Sensor Arrays Using a 15-bit Two-Step Sigma-Delta
ADC."
[24] M. Mohammed, M. Hassan, A. Fuad, and M. M. Jaber, "Follow up System for Directorate of Scholarship and
Cultural Relations in Iraq."
[25] S. Medawar, B. Murmann, P. Handel, N. Bjorsell, and M. Jansson, "Static Integral Nonlinearity Modeling and
Calibration of Measured and Synthetic Pipeline Analog-to-Digital Converters," 2014.
[26] V. Kerzerho, V. Fresnaud, D. Dallet, S. Bernard, and L. Bossuet, "Fast digital post-processing technique for
integral nonlinearity correction of analog-to-digital converters: validation on a 12-bit folding-and-interpolating
analog-to-digital converter," Instrumentation and Measurement, IEEE Transactions on, vol. 60, pp. 768-775, 2011.
[27] T. J. Abaas, A. S. Shibghatullah, and M. M. Jaber, "Use Information Sharing Environment Concept to Design
Electronic Intelligence Framework for Support E-Government: Iraq as Case Study," vol, vol. 4, pp. 22-24, 2014.
[29] M. H. Ali and M. A. Othman, "Towards a Exceptional Distributed Database Model for Multi DBMS," in
Advanced Computer and Communication Engineering Technology, ed: Springer International Publishing, 2015,
pp. 553-560.
[30] M. Saberi and R. Lotfi, "Segmented Architecture for Successive Approximation Analog-to-Digital Converters,"
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 22, pp. 593-606, 2014.
[31] Y. Gupta, L. Garg, S. Khandelwal, S. Gupta, S. Jain, and S. Saini, "A 4-bit, 3.2 GSPS flash analog to digital
converter with a new multiplexer based encoder," in Electrical Engineering/Electronics, Computer,
Telecommunications and Information Technology (ECTI-CON), 2014 11th International Conference on, 2014, pp.
1-6.
Page 16
[32] G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. Van der Plas, and J. Vandewege, "Low-power 4-bit flash analogue to
digital converter for ranging applications," Electronics letters, vol. 47, pp. 20-22, 2011.
[33] V. Bhatia, N. Pandey, and A. Bhattacharyya, "Application based comparison of different analog to digital
converter architectures," International Journal of Engineering Science and Technology, vol. 2, pp. 3396-3404,
2010.
[34] V. Srinivas, S. Pavan, A. Lachhwani, and N. Sasidhar, "A distortion compensating flash analog-to-digital
conversion technique," Solid-State Circuits, IEEE Journal of, vol. 41, pp. 1959-1969, 2006.
[35] C. Zhang and Z. Shao, "Analysis and simulation of distributed T/H with averaging technique in folding and
interpolating A/D converters," International Journal of Circuit Theory and Applications, vol. 38, pp. 901-933,
2010.
[36] B. De Muer and M. S. Steyaert, "A CMOS monolithic -controlled fractional-N frequency synthesizer for DCS1800," Solid-State Circuits, IEEE Journal of, vol. 37, pp. 835-844, 2002.
[37] M. M. Jaber, M. K. A. Ghani, N. Suryana, M. A. Mohammed, and T. Abbas, "Flexible Data Warehouse
Parameters: Toward Building an Integrated Architecture," vol, vol. 7, pp. 349-353, 2014. DOI:
10.7763/IJCTE.2015.V7.984
[38] E. Sail, M. Vesterbacka, and K. Andersson, "A study of digital decoders in flash analog-to-digital converters," in
Circuits and Systems, 2004. ISCAS'04. Proceedings of the 2004 International Symposium on, 2004, pp. I-129-I132 Vol. 1.
[39] M. K. A. Ghani, M. M. Jaber, and N. Suryana, "TELEMEDICINE SUPPORTED BY DATA WAREHOUSE
ARCHITECTURE," 2006.
[40] S. P. Kopparthy, I. Makwana, and A. Gupta, "An asynchronous 8-bit 5 MS/s pipelined ADC for biomedical sensor
based applications," in Electronics, Computing and Communication Technologies (CONECCT), 2013 IEEE
International Conference on, 2013, pp. 1-6.
[41] O. J. L. Gerasta, L. S. Bete, J. C. Loreto, and S. D. M. Orlasan, "12-Bit Pipeline ADC Implemented in 0.09-um
Digital CMOS Technology for Powerline Alliance," 2014.
[42] J. Guo, J. Yuan, J. Huang, J.-Y. Law, C.-K. Yeung, and M. Chan, "32.9 nV/rt Hz 60.6 dB THD dual-band microelectrode array signal acquisition IC," Solid-State Circuits, IEEE Journal of, vol. 47, pp. 1209-1220, 2012.
[43] M. M. Jaber, M. K. A. Ghani, and N. S. Herman, "A REVIEW OF ADOPTION OF TELEMEDICINE IN
MIDDLE EAST COUNTRIES: TOWARD BUILDING IRAQI TELEMEDICINE FRAMEWORK."
[44] G. Beanato, "Design of a Very Low Power SAR Analog to Digital Converter," Master of Science, Department of
Electrical Engineering, The EPFL University, 2009.
[45] C. C. Lee and M. P. Flynn, "A SAR-assisted two-stage pipeline ADC," Solid-State Circuits, IEEE Journal of, vol.
46, pp. 859-869, 2011.
[46] N. Madhu Mohan, B. George, and V. J. Kumar, "A Novel Dual-Slope Resistance-to-Digital Converter,"
Instrumentation and Measurement, IEEE Transactions on, vol. 59, pp. 1013-1018, 2010.
[47] A. Julsereewong, S. Pongswatd, V. Riewruja, H. Sasaki, K. Fujimoto, and Y. Shi, "Accurate Dual Slope Analog-toDigital Converter Using Bootstrap Circuit," in Innovative Computing, Information and Control (ICICIC), 2009
Fourth International Conference on, 2009, pp. 1361-1364.
[48] W. Kester and J. Bryant, "ADC Architectures VIII: Integrating ADCs," ed: Analog Devices, MT-027, 2008.
[49] B. Le, T. W. Rondeau, J. H. Reed, and C. W. Bostian, "Analog-to-digital converters," Signal Processing Magazine,
IEEE, vol. 22, pp. 69-77, 2005.
[50] M. Wang, "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication
System-on-a-Chip," Wright State University, 2007.
[51] E. Sail and M. Vesterbacka, "A multiplexer based decoder for flash analog-to-digital converters," in TENCON
2004. 2004 IEEE Region 10 Conference, 2004, pp. 250-253.
Page 17