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TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
TPS54361-Q1 4.5-V to 60-V Input, 3.5-A, Step Down DC-DC Converter with Soft-Start
and Eco-mode
1 Features
3 Description
PACKAGE
TPS54361-Q1
2 Applications
BODY SIZE
SON (10)
4.00 mm 4.00 mm
4 Simplified Schematic
VI
PWRGD
VIN
TPS54361-Q1
100
90
RT/CLK
SS/TR
95
BOOT
SW
COMP
FB
VO
Efficiency (%)
EN
85
80
75
70
GND
36 V to 12 V
12 V to 5 V
12 V to 3.3 V
VO = 12 V, gs = 630 kHz
VO = 5 V and 3.3 V, gs = 400 kHz
65
60
0
0.5
1.5
2
Output Current (A)
2.5
3.5
D029
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
6
6
7
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
5 Revision History
Changes from Original (April 2014) to Revision A
Page
TPS54361-Q1
www.ti.com
10
PWRGD
VIN
SW
EN
GND
SS/TR
COMP
RT/CLK
FB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
BOOT
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
COMP
This pin is the error amplifier output and input to the output switch current (PWM) comparator. Connect
frequency compensation components to this pin.
EN
This pin is the enable pin, with an internal pullup current source. Pull EN below 1.2 V to disable. Float EN
to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and Adjust
Undervoltage Lockout section.
FB
This pin is the Inverting input of the transconductance (gm) error amplifier.
GND
Ground
VIN
This pin is the input supply voltage with 4.5-V to 60-V operating range.
PWRGD
10
The PWRGD pin is an open drain output that asserts low if the output voltage is out of regulation because
of thermal shutdown, dropout, over-voltage, or EN shut down.
RT/CLK
This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltage
when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL
upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal
amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop,
the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
SS/TR
This pin is the soft-start and tracking pin. An external capacitor connected to this pin sets the output rise
time. Because the voltage on this pin overrides the internal reference, SS/TR can be used for tracking and
sequencing.
SW
The SW pin is the source of the internal high-side power MOSFET and switching node of the converter.
The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
operation.
Thermal Pad
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VIN
0.3
65
EN
0.3
8.4
BOOT
Input voltage
73
FB
0.3
COMP
0.3
PWRGD
0.3
SS/TR
0.3
RT/CLK
0.3
3.6
0.6
65
65
40
150
BOOT-SW
Output voltage
SW
SW, 10-ns Transient
UNIT
V
C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
MIN
MAX
65
150
kV
750
750
Other pins
500
500
V(ESD)
(1)
Electrostatic discharge
UNIT
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
MAX
V(VIN)
4.5
60
UNIT
V
VO
Output voltage
0.8
58.8
IO
Output current
TJ
Junction Temperature
3.5
40
150
DPR
(10 PINS)
RJA
JT
0.3
JB
12.5
RJCtop
34.1
RJCbot
2.2
RJB
12.3
(1)
(2)
UNIT
35.1
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150C. This is the point where
distortion starts to substantially increase. See the power dissipation estimate in the Power Dissipation Estimate section of this data sheet
for more information.
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
60
4.3
4.48
4.5
4.1
325
mV
2.25
4.5
152
200
1.2
1.3
II
Input current
Ihys
Hysteresis current
1.1
Enable threshold 50 mV
Enable threshold 50 mV
4.6
0.58
1.2
-1.8
2.2
3.4
-4.5
0.792
0.8
0.808
87
185
VOLTAGE REFERENCE
Voltage reference
HIGH-SIDE MOSFET
On-resistance
V(VIN) = 12 V, V(BOOT-SW) = 6 V
ERROR AMPLIFIER
Input current
Error amplifier transconductance (gm)
V(FB) = 0.8 V
COMP to SW current
transconductance
50
nA
350
Mhos
77
Mhos
10 000
V/V
2500
kHz
30
12
A/V
CURRENT-LIMIT
Current-limit threshold
4.5
5.5
6.8
4.5
5.5
6.3
5.2
5.5
5.9
THERMAL SHUTDOWN
Thermal shutdown
Thermal shutdown hysteresis
176
12
1.55
0.5
1.2
V
V
Charge current
V(SS/TR) = 0.4 V
1.7
VSS(ofs)
SS/TR-to-FB matching
V(SS/TR) = 0.4 V
42
mV
SS/TR-to-reference crossover
98% nominal
1.16
354
V(FB) = 0 V
54
mV
(1)
FB falling
FB rising
90%
93%
FB rising
108%
FB falling
106%
Hysteresis
FB falling
2.5%
10
nA
On resistance
45
Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
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TEST CONDITIONS
MIN
TYP
MAX
0.9
TYP
MAX
UNIT
V
UNIT
RT/CLK
Minimum CLK input pulse width
15
ns
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(VIN) = 12 V, TA = 25C
540
60
ns
100
ns
CURRENT-LIMIT
Current limit threshold delay
SW
ton
Minimum on time
RT/CLK
Switching frequency range using RT mode
S
Switching frequency
100
R(RT) = 200 k
450
500
160
2500
kHz
550
kHz
2300
kHz
55
ns
78
TPS54361-Q1
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0.25
0.814
0.809
0.2
V o lta g e R e fe r e n c e ( V )
S ta tic D r a in - S o u r c e O n - S ta te R e s is ta n c e (: )
0.15
0.1
0.05
0.804
0.799
0.794
0.789
BOOT-SW = 3 V
BOOT-SW = 6 V
0
0.784
-50
-25
25
50
75
100
125
150
-50
-25
25
50
75
100
125
150
D004
D028
V(VIN) = 12 V
6.5
6.5
6.3
6.3
H ig h - S id e S w itc h C u r r e n t ( A )
H ig h - S id e S w itc h C u r r e n t ( A )
-40q
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
25q
150q
6.1
5.9
5.7
5.5
5.3
5.1
4.9
4.7
4.5
4.5
-50
-25
25
50
75
100
125
150
10
20
30
40
50
60
D027
D026
V(VIN) = 12 V
550
450
530
S w itc h in g F r e q u e n c y ( k H z )
S w itc h in g F r e q u e n c y ( k H z )
540
520
510
500
490
480
470
350
300
250
200
150
460
450
-50
400
100
-25
25
50
75
V(VIN) = 12 V
100
125
150
200
300
400
500
600
700
800
900
D025
R(RT) = 200 k
1000
D024
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
450
2000
T r a n s c o n d u c ta n c e ( P A /V )
S w itc h in g F r e q u e n c y ( k H z )
2500
1500
1000
500
400
350
300
250
200
0
50
100
150
200
-50
-25
25
50
75
100
125
D023
150
D022
V(VIN) = 12 V
120
1.3
100
90
E N T h r e s h o ld ( V )
T r a n s c o n d u c ta n c e ( P A /V )
110
80
70
60
50
40
1.27
1.24
1.21
1.18
30
20
1.15
-50
-25
25
50
75
100
125
150
-50
25
50
75
100
125
150
D020
V(VIN) = 12 V
-3.5
-0.5
-3.7
-0.7
-3.9
-0.9
In p u t C u r r e n t a t E N ( P A )
In p u t C u r r e n t a t E N ( P A )
V(VIN) = 12 V
-4.1
-4.3
-4.5
-4.7
-4.9
-1.1
-1.3
-1.5
-1.7
-1.9
-5.1
-2.1
-5.3
-2.3
-5.5
-2.5
-50
-25
25
50
75
V(VIN) = 12 V
100
125
150
-50
-25
V(EN) = Threshold + 50 mV
25
50
75
D019
-25
D021
V(VIN) = 12 V
100
125
150
D018
V(EN) = Threshold 50 mV
TPS54361-Q1
www.ti.com
100
V (FB) Falling
N o m in a l S w itc h in g F r e q u e n c y ( % )
-2.7
I ( E N ) H y s te r e s is ( P A )
-2.9
-3.1
-3.3
-3.5
-3.7
-3.9
-4.1
-4.3
-4.5
V (FB) Rising
75
50
25
-50
-25
25
50
75
100
125
150
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Voltage at FB (V)
D017
0.8
D016
V(VIN) = 12 V
2.5
2.5
S u p p ly C u r r e n t a t V IN (P A )
S u p p ly C u r r e n t a t V IN (P A )
1.5
0.5
1.5
0.5
-50
-25
25
50
75
100
125
150
20
30
40
50
V(VIN) = 12 V
60
D014
TJ = 25 C
210
210
190
190
S u p p ly C u r r e n t a t V IN ( P A )
S u p p ly C u r r e n t a t V IN ( P A )
10
D015
170
150
130
110
90
170
150
130
110
90
70
70
-50
-25
25
50
75
100
125
150
10
V(VIN) = 12 V
20
30
40
50
D013
60
D012
TJ = 25C
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
2.6
4.5
2.5
4.4
2.4
4.3
In p u t V o lta g e ( V )
In p u t V o lta g e a t B O O T - P H ( V )
2.3
2.2
2.1
2
4.2
4.1
4
3.9
1.9
3.8
1.8
3.7
-50
-25
25
50
75
100
125
150
-50
50
75
100
125
150
D010
P o w e r - G o o d R e s is ta n c e (: )
25
110
70
60
50
40
30
20
10
106
104
102
FB
100
FB Falling
98
FB Rising
FB Falling
96
94
92
90
88
-50
-25
25
50
75
100
125
150
-50
-25
25
50
75
100
125
D009
V(VIN) = 12 V
150
D008
V(VIN) = 12 V
900
60
800
55
S S /T R to F B O ffs e t ( m V )
700
600
O ffs e t ( m V )
80
500
400
300
200
50
45
40
35
30
25
100
0
20
0
100
200
300
400
500
600
700
SS/TR (mV)
V(VIN) = 12 V
800
-50
-25
25C
25
50
75
100
125
D007
V(VIN) = 12 V
10
-25
D011
150
D006
V(FB) = 0.4 V
TPS54361-Q1
www.ti.com
Stop
I n p u t V o lta g e ( V )
5.4
5.3
5.2
5.1
Dropout
Voltage
5
4.9
Dropout
Voltage
4.8
4.7
4.6
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
D005
Figure 25. 5-V Start and Stop Voltage (see Low Dropout Operation and Bootstrap Voltage (BOOT))
11
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
8 Detailed Description
8.1 Overview
The TPS54361-Q1 device is a 60-V, 3.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. The device implements constant-frequency current-mode control which reduces output capacitance
and simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHz
allows either efficiency or size optimization when selecting the output filter components. The switching frequency
is adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked
loop (PLL) connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of an
external clock signal.
The TPS54361-Q1 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the input
voltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current source
enables operation when the EN pin is floating. The operating current is 152 A under no load condition when not
switching. When the device is disabled, the supply current is 2 A.
The integrated 87-m high-side MOSFET supports high-efficiency power-supply designs capable of delivering
3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is
supplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54361-Q1 device reduces the
external component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is
monitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a
preset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54361-Q1 device to operate at
high duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply
voltage of the application. The minimum output voltage is the internal 0.8 V feedback reference.
Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft-start/tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor
divider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin is
discharged before the output powers up. This discharging ensures a repeatable restart after an over-temperature
fault, UVLO fault or a disabled condition. When the overload condition is removed, the soft-start circuit controls
the recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces the
switching frequency during start up and overcurrent fault conditions to help maintain control of the inductor
current.
12
TPS54361-Q1
www.ti.com
PWRGD
VIN
Shutdown
UV
Thermal
Shutdown
Enable
Comparator
Logic
UVLO
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Reference
Minimum
Clamp
Pulse
Skip
Error
Amplifier
Boot
UVLO
Current
Sense
PWM
Comparator
FB
BOOT
SS/TR
Logic
Shutdown
Slope
Compensation
SW
COMP
Frequency
Foldback
Overload
Recovery
Maximum
Clamp
Oscillator
with PLL
10/9/2013 A0272435
GND
POWERPAD
RT/ CLK
13
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
14
TPS54361-Q1
www.ti.com
where
Dmax 0.9
rDS(on) = 1 / (0.3 V(BOOT_SW)2 + 3.577 x V(BOOT_SW) 4.246)
I(BOOT_SW) = 100 A
V(BOOT_SW) = V(BOOT) + Vd
V(BOOT) = (1.41 V(VIN) 0.554 Vd S 10-6 1.847 103 I(BOOT_SW)) / (1.41 + S 10-6)
Vd = Forward Drop of the Catch Diode
(1)
V - 0.8 V
R(HS) = R(LS) O
0.8 V
(2)
RUVLO2 =
V(EN)th
VSTART - V(EN)th
+ I1
RUVLO1
(4)
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TPS54361-Q1
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V(VIN)
TPS54361-Q1
I1
RUVLO1
Ihys
TPS54361-Q1
RUVLO1
EN
EN
V(EN)th
RUVLO2
RUVLO2
10 k
Node
5.8 V
V(EN)
V(SS/TR)
V(FB)
VO
TPS54361-Q1
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TPS54361-Q1
PWRGD
EN
SS/TR
EN
V(EN)(1)
V(PWRGD)
SS/TR
PWRGD
VO(1)
VO(2)
17
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
EN
SS/TR
PWRGD
V(EN)(1), V(EN)(2)
VO(1)
VO(2)
TPS54361-Q1
3
EN
SS/TR
PWRGD
Figure 31 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs ramps up and reaches regulation at the same time. When calculating the soft-start time the
pullup current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.
TPS54361-Q1
EN
VO(1)
SS /TR
PWRGD
TPS54361-Q1
VO(2)
EN
R (TR)1
SS / TR
R(TR)2
PWRGD
FB
R (HS)
R(LS)
TPS54361-Q1
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R(TR)1 =
Vref
ISS
(6)
R(TR)2 =
Vref R(TR)1
VO(2) + DV - Vref
(7)
(8)
(9)
V = VO(1) VO(2)
R(TR)1 > 2800 VO(1) 180 V
V(EN)
V(EN)
VO(1)
VO(1)
VO(2)
VO(2)
19
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
V(EN)
VO(1)
VO(2)
S (kHz) =
101756
R(RT) (kW)1.008
(11)
20
TPS54361-Q1
www.ti.com
CL(peak)
Open-loop Current-limit
ton
Figure 37. Current Limit Delay
To protect the converter in overload conditions at higher switching frequencies and input voltages, the
TPS54361-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB
pin voltage falls from 0.8 V to 0 V. The TPS54361-Q1 device uses a digital frequency foldback to enable
synchronization to an external clock during normal start-up and fault conditions. During short-circuit events, the
inductor current may exceed the peak current limit because of the high input voltage and the minimum
controllable on time. When the output voltage is forced low by the shorted load, the inductor current decreases
slowly during the switch off time. The frequency foldback effectively increases the off time by increasing the
period of the switching cycle providing more time for the inductor current to ramp down.
With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current can
be controlled by frequency foldback protection. calculates the maximum switching frequency at which the
inductor current remains under control when VO is forced to VO(SC). The selected operating frequency must not
exceed the calculated value.
Equation 12 calculates the maximum switching frequency limitation set by the minimum controllable on time and
the input to output step down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.
IO RDC + VO + Vd
1
S(skip ) max =
ton V(VIN) max - IO rDS(on ) + Vd
where
(12)
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TPS54361-Q1
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where
(13)
TPS54361-Q1
R(RT)
Clock
Source
RT/CLK
RT/CLK
PLL
PLL
Hi-Z
Clock
Source
R(RT)
22
TPS54361-Q1
www.ti.com
V(SW)
V(SW)
EXT
EXT
IL
IL
V(SW)
EXT
IL
23
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
VO
Power Stage
gm ps 12 A/V
a
b
R(HS)
R(ESR)
R(L)
COMP
c
0.8 V
C(OEA)
R(COMP)
C(POLE)
R(OEA)
C(O)
FB
gmea
350 A/V
R(LS)
C(ZERO)
24
TPS54361-Q1
www.ti.com
ADC
V(c)
R(ESR)
P
R(L)
gmps
C(O)
Figure 43. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
s
1 +
2
Z
p
VO
= ADC
V(c )
s
1 +
2p P
(14)
(15)
P =
Z =
C(O)
1
R(L) 2p
(16)
1
C(O) R(ESR) 2p
(17)
25
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
R(HS)
FB
Type 2A
gmea
R(LS)
Type 2B
Type 1
COMP
Vref
R(COMP)
R(OEA)
R(COMP)
C(POLE)
C(POLE)
C(OEA)
C(ZERO)
C(ZERO)
Aol
P1
A0
Z1
P2
A1
BW
Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation
R(OEA) =
C(OEA)
Aol (V/V )
gmea
gmea
=
2p BW (Hz )
(18)
(19)
s
1 +
2p Z1
EA = A0
s
s
1 +
1 +
2p P1 2p P2
A0 = gm ea R(OEA)
R(HS) + R(LS)
A1 = gm ea R(OEA) P R(COMP)
26
(20)
R(LS)
(21)
R(LS)
R(HS) + R(LS)
(22)
TPS54361-Q1
www.ti.com
1
2p R(OEA) C(ZERO)
(23)
1
2p R(COMP) C(ZERO)
(24)
Type 2A
(25)
1
P2 =
Type 2B
2p R(COMP) P R(OEA) C(OEA)
P2 =
2 R(OEA)
(26)
1
type 1
(C(POLE) + C(OEA) )
(27)
27
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
+
CI
C(BOOT)
LO
C(VIN)
PH
BOOT
VIN
GND
R(HS)
GND
TPS54361-Q1
C(O)
R(LS)
FB
VO
EN
COMP
SS /TR
R(COMP)
RT /CLK
C(SS)
C(ZERO)
R(RT)
C(POLE)
Figure 46. TPS54361-Q1 Inverting Power Supply based on the Application Note, SLVA317
8.4.3.2 Split Rail Power Supply
The TPS54361-Q1 device can be used to convert a positive input voltage to a split rail positive and negative
output voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive and
negative voltage power supply. For a more detailed example see SLVA369.
+
VI
CO+
+
CI
C(BOOT)
BOOT
VIN
VO+
GND
PH
LO
C(VIN)
R(HS)
GND
CO
R(LS)
TPS54361-Q1
FB
VO
EN
SS /TR
COMP
R(COMP)
RT /CLK
C(SS)
R(RT)
C(ZERO)
C(POLE)
Figure 47. TPS54361-Q1 Split Rail Power Supply based on the Application Note, SLVA369
28
TPS54361-Q1
www.ti.com
PWRGD PULL UP
R8
+
DNP
DNPC10 DNPC3
2.2 F 2.2 F
C1
2.2 F
C2
2.2 F
R1
442 k
5
SS/TR
J2
R3
162 k
TP2
VIN
PWRGD
EN
BOOT
RT/CLK
SW
SS/TR
FB
COMP
GND
PAD
GND
C13
0.01 F
2
1
GND
EN
GND
R2
90.9 k
2
1
TP9
C4
L1
TP5
TP6
TP7
8.2H
FB
D1
C6
47 F
TPS54361-Q1
C8
39 pF
5 V at 3.5 A
0.1 F
R7
49.9
GND
C7 DNPC9
47 F
47F
+
C12
DNP
1
TP8
VO
GND
J1
GND
TP4
R5
53.6 k
C5
6800 pF
J4
GND
R4
13 k
10
1
C11
2
TP1
TP10 1.00 k
VI
GND
U1
7 V to 60 V
GND
J3
FB
R6
10.2 k
TP3
GND
GND
2 SS/TR
1
SS/TR
GND
J5
GND
EXAMPLE VALUE
5V
VO = 4 %
3.5 A
12 V nominal 7 V to 60 V
0.5% of VO
6.5 V
5V
29
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
Equation 12 and must be used to calculate the upper limit of the switching frequency for the regulator. Choose
the lower value result from the two equations. Switching frequencies higher than these values results in pulse
skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, ton, is 100 ns for the TPS54361-Q1 device. For this example, the output voltage is
5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 960 kHz to
avoid pulse skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits use
to determine the maximum switching frequency for frequency foldback protection. With a maximum input voltage
of 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 25 m, switch resistance of 87 m, a current
limit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 1220 kHz.
For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculated
maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in
Figure 6. The switching frequency is set by resistor R3 shown in Figure 48. For 600 kHz operation, the closest
standard value resistor is 162 k.
1
3.5 A 25 mW + 5 V + 0.7 V
S(skip) max =
= 960 kHz
100 ns
60 V 3.5 A 87 mW + 0.7 V
(28)
8
4.7 A 25 mW + 0.1 V + 0.7 V
= 1220 kHz
100 ns
60 V 4.7 A 87 mW + 0.7 V
92417
R3 (kW) =
= 163 kW
600 (kHz)0.991
S(shift) =
(29)
(30)
30
TPS54361-Q1
www.ti.com
V max - VO
VO
60 V 5 V
5V
LO min = I
= 7.3 H
IO KIND
VI max S 3.5 A 0.3
60 V 600 kHz
(31)
spacer
V (VI max - VO )
5 V (60 V 5 V)
Irip = O
=
= 0.932 A
VI max LO S
60 V 8.2 H 600 kHz
(32)
spacer
2
IL(RMS ) =
(IO )
VO (VI max - VO )
1
+
=
12 VI max LO S
(3.5 A )
5 V (60 V 5 V )
1
+
= 3.5 A
12
60 V 8.2 H 600 kHz
(33)
spacer
IL(peak ) = IO +
Irip
2
= 3.5 A +
0.932 A
= 3.97 A
2
(34)
31
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, two
47-F, 10-V ceramic capacitors with 5 m of ESR is used. The derated capacitance is 58 F, well above the
minimum required capacitance of 29 F.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current.
Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For this
example, Equation 39 yields 269 mA.
2 DIO
2 1.75 A
C(O) >
=
= 29.2 F
S DVO 600 kHz 0.2 V
(35)
C(O) > LO
((I
OH
)2 - (IOL )2
(Vf ) - V(int)
1
1
C(O) >
=
8 S VO(rip) 8
Irip
VO(rip)
25 mV
R(ESR) <
=
=
Irip
0.932 A
ICO(RMS) =
) = 8.2 H (2.625 A
(5.2 V
- 0.875 A 2
5V
)=
24.6 F
(36)
1
1
= 7.8 F
600 kHz
25 mV
0.932 A
(37)
27 mW
VO (VI min - VO )
12 VI min LO S
(38)
5V
(60 V 5 V )
= 269 mA
(39)
(VI - VO )
=
IO Vd
VI
(12 V
C j S (VI + Vd )
- 5 V ) 3.5 A 0.55 V
12 V
32
2
+
(40)
TPS54361-Q1
www.ti.com
VO
VI min
(VI min - VO )
VI min
= 3.5 A
5V
8.5 V
(8.5 V
5 V)
8.5 V
= 1.72 A
(41)
I 0.25
3.5 A 0.25
DVI = O
=
= 331 mV
CI S
4.4 F 600 kHz
(42)
CSS (nF) =
(44)
33
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
V(EN)
VSTART V(EN)
R1
=
+ I1
1.2 V
= 90.9 kW
6.5 V 1.2 V
+ 1.2 A
442 kW
(46)
(47)
9.2.2.10 Compensation
There are several methods to design compensation for DC-DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual crossover frequency is lower than the crossover frequency used in the
calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero
and the ESR zero is at least ten-times greater the modulator pole.
To get started, the modulator pole, P(mod), and the ESR zero, Z1 must be calculated using Equation 48 and
Equation 49. For C(O), use a derated value of 58.3 F. Use equations Equation 50 and Equation 51 to estimate a
starting point for the crossover frequency, CO. For the example design, P(mod) is 1912 Hz and Z(mod) is 1092
kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of
modulator pole and the switching frequency. Equation 50 yields 45.7 kHz and Equation 51 gives 23.9 kHz. Use
the lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target co
is 23.9 kHz.
Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a
compensating zero. A capacitor in parallel to these two components forms the compensating pole.
IO max
3.5 A
P(mod) =
=
= 1912 Hz
2 p VO C(O) 2 p 5 V 58.3 F
(48)
Z(mod) =
1
1
=
= 1092 kHz
2 p R6 C4
2 p 2.5 mW 58.3 F
where
CO = P(mod) Z(mod) =
34
= 45.7 kHz
(49)
(50)
TPS54361-Q1
www.ti.com
CO = P(mod)
S
=
2
1912 Hz
600 kHz
2
= 23.9 kHz
(51)
To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gmps,
is 12 A/V. The output voltage, VO, reference voltage, Vref, and amplifier transconductance, gmea, are 5 V, 0.8 V
and 350 A/V, respectively. R4 is calculated to be 13 k which is a standard value. Use Equation 53 to set the
compensation zero to the modulator pole frequency. Equation 53 yields 6404 pF for compensating capacitor C5.
6800 pF is used for this design.
2 p CO CO
VO
5V
2 p 23.9 kHz 58.3 F
R4 =
=
= 13 kW
gmps
12 A / V
0.8 V 350 A / V
Vref gmea
(52)
C5 =
1
1
=
= 6404 pF
2 p R4 P(mod)
2 p 13 kW 1912 Hz
(53)
A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the
compensation pole. The selected value of C8 is 39 pF for this design example.
C4 R 6
58.3 F 2.5 mW
=
= 11.2 pF
C8 =
R4
13 kW
(54)
1
1
C8 =
=
= 40.8 pF
R4 S p
13 kW 600 kHz p
(55)
9.2.2.11 Discontinuous Conduction Mode and Eco-mode Boundary
With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 300 mA. The power supply enters Eco-mode when the output current is lower than 24 mA. The input
current draw is 260 A with no load.
35
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
10 V/div
1 A/div
C4: IO
VI
20 mV/div
C3: VO AC coupled
Time = 5 ms/div
C1: VI
2 V/div
5 V/div 2 V/div
C3: VO
C3
C2: V(SS/TR)
C2
C3: VO
C4: V(PGOOD)
C3
C4
Time = 2 ms/div
Time = 2 ms/div
C1
C4: IL
C3: VO AC coupled
C3
C4
C1: V(SW)
C1
C4: IL
500 mA/div
10 V/div
C1: V(SW)
C4
20 mV/div
1 V/div
2 V/div
10 V/div
C2
1 A/div
C1: V(EN)
C1
C2: V(EN)
C3
C3: VO AC coupled
Time = 2 s/div
Time = 2 s/div
IO = 3.5 A
IO = 100 mA
36
5-V offset
C1
20 mV/div
VO
2 V/div
C3
5 V/div
100 mV/div
C4
TPS54361-Q1
10 V/div
C1: V(SW)
C1
C1: V(SW)
C1
1 A/div
C4: IL
C4: IL
C4
C3: VO AC coupled
C3: VI AC coupled
C3
200 mV/div
20 mV/div
200 mA/div
10 V/div
www.ti.com
C3
C4
Time = 2 s/div
Time = 2 ms/div
No Load
IO = 3.5 A
C1: V(SW)
2 V/div
C1: V(SW)
C1
C4: IL
C4
20 mV/div
C3: VI AC coupled
20 mV/div
200 mA/div
500 mA/div
10 V/div
C3
C4
C4: IL
C3
C3: VO AC coupled
Time = 2 s/div
IO = 100 mA
VI = 5.5 V
VO = 5 V
2 V/div
2 V/div
VI
VO
Time = 20 s/div
No load
EN floating
VI
VO
IO = 100 mA
Time = 40 s/div
EN floating
IO = 1 A
Time = 40 s/div
EN floating
37
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
100
100
90
95
80
90
E ffic ie n c y ( % )
E ffic ie n c y ( % )
70
85
80
75
VI =7V
60
50
40
VI =7V
30
V I = 12 V
V I = 12 V
70
V I = 24 V
V I = 24 V
20
V I = 36 V
V I = 36 V
65
V I = 48 V
V I = 48 V
10
V I = 60 V
V I = 60 V
60
0.5
1.5
2.5
3.5
VO = 5 V
0.001
0.01
0.1
D030
S = 600 kHz
VO = 5 V
D031
S = 600 kHz
100
100
VI =6 V
V I = 12 V
95
90
V I = 24 V
V I = 36 V
80
V I = 48 V
90
V I = 60 V
E ffic ie n c y ( % )
E ffic ie n c y ( % )
70
85
80
75
60
50
40
VI =6V
30
V I = 12 V
70
V I = 24 V
20
65
V I = 36 V
V I = 48 V
10
V I = 60 V
60
0
0
0.5
1.5
2.5
3.5
VO = 3.3 V
0.001
0.01
S = 600 kHz
VO = 3.3 V
0.1
D032
D034
S = 600 kHz
0.1
Gain
0.08
20
60
-20
-60
-40
-120
-60
-180
O u tp u t V o lta g e D e v ia tio n ( % )
120
P h a s e (q)
G a in ( d B )
Phase
40
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
10
100
1000
Frequency (Hz)
VO = 5 V
VI = 12 V
S = 600 kHz
10000
100000
0.5
IO = 3.5 A
1.5
2.5
3.5
D036
38
-0.1
VO = 5 V
S = 600 kHz
D033
VI = 12 V
TPS54361-Q1
www.ti.com
O u tp u t V o lta g e D e v ia tio n ( % )
0.08
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.1
0
10
20
30
40
50
VO = 5 V
S = 600 kHz
60
D035
IO = 1.75 A
11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade performance. See Figure 68 for a PCB layout example.
To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric.
Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and
the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to the
output inductor. Since the SW connection is the switching node, the catch diode and output inductor should
be located close to the SW pins, and the area of the PCB conductor minimized to prevent excessive
capacitive coupling.
The GND pin should be tied directly to the power pad under the IC and the PowerPAD. The PowerPAD
should be connected to internal PCB ground planes using multiple vias directly under the IC.
For operation at full rated load, the top side ground area must provide adequate heat dissipating area.
The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and
routed with minimal lengths of trace.
The additional external components can be placed approximately as shown.
It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has
been shown to produce good results and is meant as a guideline.
Boxing in the components in the design of Figure 48 the estimated printed circuit board surface area is 1.025 in2
(661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can be
done by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.
39
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
where
(56)
2. Switching loss:
E = VI S IO tr = 12 V 600 kHz 3.5 A 4.9 ns = 0.123 A
where
(57)
where
(58)
where
(59)
Therefore,
Ptot = PCON + E + PG + PQ = 0.45 W + 0.123 W + 0.022 W + 0.0018 W = 0.597 W
(60)
where
(61)
where
(62)
Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,
and PCB trace resistance impacting the overall efficiency of the regulator.
40
TPS54361-Q1
www.ti.com
Output
Capacitor
Topside
Ground
Area
Output
Inductor
Input
Bypass
Capacitor
BOOT
VI
UVLO
Adjust
Resistors
Catch
Diode
PWRGD
VIN
SW
EN
GND
SS/TR
RT/CLK
COMP
FB
Compensation
Network
Resistor
Divider
Thermal VIA
Soft-Start
Capacitor
Frequency
Set Resistor
Signal VIA
41
TPS54361-Q1
SLVSCC4A APRIL 2014 REVISED APRIL 2014
www.ti.com
12.3 Trademarks
Eco-mode, PowerPAD, WEBENCH are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
42
www.ti.com
17-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS54361QDPRRQ1
ACTIVE
WSON
DPR
10
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54361Q
TPS54361QDPRTQ1
ACTIVE
WSON
DPR
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
TPS
54361Q
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
17-May-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54361-Q1 :
Catalog: TPS54361
NOTE: Qualified Version Definitions:
Addendum-Page 2
24-Apr-2014
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS54361QDPRRQ1
WSON
DPR
10
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
TPS54361QDPRTQ1
WSON
DPR
10
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
24-Apr-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54361QDPRRQ1
WSON
DPR
10
3000
367.0
367.0
35.0
TPS54361QDPRTQ1
WSON
DPR
10
250
210.0
185.0
35.0
Pack Materials-Page 2
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