Professional Documents
Culture Documents
Annamaria
MESARO$
LUPU
Aurel
SUCIU
MICROPROCESSORS
Architectures and Applications
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Editura RISOPRINT
Cluj-Napoca 2003
Conten ts
CONTENTS
PREFACE
1.
2.
3.
1.9. Applications
1.1a.Exercise
19
29
.
3.3. The content of the memory and its accessing mode
4.
39
5.
6.
4.6. Exercise
APPLICATIONS ON THE INTERRUPT SYSTEM
5.1. The application support
5.2. Exercise
55
51
Contents
7.
8.
7.3. Exercise
9.
8.5. Exercise
....... . .
...
..
. . . .. . . . ... . ... 91
141
..... . . . . ............
144
149
...
.....
...
...
. . . ....
..
. ...
.....
. .
.
...
. ....151
154
..............
157
PREFACE
PC
its
Some
MICROPROCESSORS
Introduction
CPUIQ detection
Starting with the I ntel 486 processor family, the processors are able to
execute the CPU I D instruction . To execute the CPUID instruction , the
program has to establish if the processor supports the instruction. This can be
done in two ways:
One verifies if the I D flag 21st bit of EFLAG register (see Appendix 1 ) can
be modified . If the program can change this flag value, then the processor
supports the CPU I D instruction. For this test the following sequence can
be used:
pushfd
pop eax
mov ebx , eax
xor eax , 0 0 2 0 0 0 0 0h
'
push eax
popfd
pushfd
pop eax
cmp eax , ebx
j z NO CPUID
,
save s EFLAGS
l oads E FLAGS
has the 2 1 s t
Z = 1 CPUID is
on s t ack
in EAX
b i t change?
not supported
outcome
AMO K6 K6-2
Cyrix GXm Cyrix Ill "Joshua"
IDT C6-2
VIA Cyrix Ill
Transmeta Crusoe
Intel Pentium 4
Additionally, one can check the ASCII string that identifies the producer. If
EAX=O, the CPUID instruction returns the producer identifier in the EBX, EDX
and ECX registers. These registers contain the ASCII string "Genuinelntel"
(see Table 1 . 1 ) for Intel processors or different producer specific strings (see
Table 1.2).
6
ECX
BDX
BBX
31...
2 3 ...
15 ...
(6C)
(65)
(74)
(6e)
(49)
(65)
(6e)
(69)
(75)
(6e)
(65)
(47)
Producer
Genuineintel
Int e l
UM C UM C UMC
UMC
Authent icAMD
AMD
Cyrixinstead
Cyrix
NexGenDriven
NexGen
CentaurHauls
Centaur
RiseRiseRise
Rise Techn.
GenuineTMx86
Transmeta
Information re turned
EAX
highest
the
by
CPUID instruction
value
recognized
EAX " l
EAX
the
processor
by
CPUID
(ASCII string)
32
signature:
MSB
(95-64)
from
EAX ,,2"
EAX:EBX:ECX:EDX
descriptors
EAX,, 3"
EDX:ECX
EAX .. aooo_ooooh
EAX .. 0000_0001h
information
about
EAX,,8000 0002h
0003h
EAX,,8000 0004h
TLB
the
64
LS B
from
the
96
of
the
CPUID
for
bits
EAX
the
highest
value
recognized
by
extended functions
EAX
extended
processor
signature
feature flags
EAX .. aooo
and
cache
Ll TLB/
cache information
Table 1 . 3
CPUID outcome
and
extended
:
EAX=00000003
)
:
EAX=00000686
:
EDX=038?F9FF
Flags =000B?046
EAX=03020101
EBX=00000000
ECX=00000000
EDX=0C040882
1.4
Beginning with the Intel 486 family, the processor will return an
identification signature in the EDX register after RESET (see Fig 1.2). The
identification signature is a 32 bits value, consisting of 8 fields; two of them
are reserved (see Fig 1 .2}.
EDX
31 .. 28 27 ..
20 19
1615 14 13 12 11
Family
Model
extension
extel\sion
Type
Family
Model
ID
code
number
version
Value
__
Description
00
01
Overdrive processor
10
Dual processor
11
Intel reserved
Table 1.4
(bits 12
and 13)
1.5 The
When EAX=1 , CPUID will load the EDX register with the processor
feature or resources flags. The current flag indicates which features the
processor supports. Table 1 .5 indicates the different values of the features
flags. For future processors flags values one should consult the reference
guide or user guide or own documentation .
B y testing the processor feature flags in developed applications, the
software can detect and avoid eventual errors and incompatibilities.
it j Name
Description when
Comments
I
I
flag=l
0
FPU
VME
DE
Virtual Mode
extension
Debug. Extension
I O
PSE
TSC
MSR
Model Specific
registers
PAE
MCE
cx0
9
10
Physical Address
extension
APIC
-
11
SEP
12
MTRR
exception
CMPXCHG8 instruction
Machine check
on 8 bits is supported
supported
CMPXCHG8,
On-chip APIC
hardware suooorted
Reserved
PGE
14
MCA
15
Machine check
architecture
CMOV
16
Conditional move
instruction
supported
PAT
PSE36
17
PSN
18
CLFSH
20
21
DS
22
ACPI
/23
'--"'
MMX
24
FXSR
S'
SSE
SSE2
27
SS
extension
The processor serial
number is present
and enabled
19
CLFSH instruction is
supported
Intel Architecture
MMX technology
Supported
Streaming SIMD
extensions supported
Streaming SIMD
extension 2
Self-Snoop
Reserved
30
Reserved
Table
Reserved
TM
31
Debug store
29
28
Thermal monitor
supported
Reserved
1.5
10
At the same time with Pentium Ill, Pentium I l l Xeon and Intel Celeron
model 8, Intel extended the identification concept by adding the Brand ID
information, which is an 8-bit number accesible by CPUID instruction.
When EAX=1, CPUID loads the processor Brand ID in the O -7 bits in EBX.
This field was introduced to eliminate identity ambiguities (such as the
difference between Pentium II and Pentium II Xeon
51 2 K L2 cache),
providing a unique value for every processor name. Table 1.6 shows the
correspondence between the bits from the EBX and the corresponding
names.
EBX o 7
Description
-
...
ooh
Olh
02h
03h
04 h
08h
OEh
A l l other values
Table
1 .6
No t supported
I nt e l C e l e ron processor
Int e l Pentium I I I pro c e s s o r
I nt e l Pent ium I I I Xeon proce s s o r
I n t e l Pent i um I I I proce s s o r
I n t e l Pent ium 4 proc e s so r
I n t e l Xeon proce s s or
Re s e rved
0)
The Pentium Ill and Pentium Ill Xeon processors extend the
identification concept by attaching the processor serial number. The serial
number is a 96-bit number accessible by CPUID. This number can be used
by applications to identify the processor and the system.
The serial number of the processor creates a software identity accessible to
an individual processor. Combined with other features, the serial number can
be applied to user identification. Applications include authentication data,
backup/restore protection, file access protection or documents exchange
between users. The serial number is a modality to check the products. In the
case of system service, the serial number can be used to differentiate users
or for error report.
The serial number provides an identifier for the processor but one
should not consider it as a unique number. There are some ways that can
report wrong serial numbers. For example, if a processor operates outside a
specified operating system, the processor will not read correctly its serial
number. BIOS or software improper operations can produce wrong serial
numbers.
11
After running CPU I D , EDX contains the feature flags. If the j 8th bit
fla is 1, the seri n_ller of !!Je pro.@"'-_or is suppofled. If the
fr
18th bit from the register is O, thr.o.c_es.sor serial 11umbefTsnoi supp_orted
or ltisdisaI)ledotnerwiSefue-serial number is supported. This bit can be
conlrolled from the (for the newer processors) or by specific
ap
ns provided by the producer. To disable the access to the !Iial
nJ1ter one must set to "1" th--21.s.t_Qii_gf BBL_CR_CTL MSR register
(ModeTSpecffiCReglsterfrOm-address 119h). Once set, this bit cannot be
modified until the processor reset. Tne next sequence is an example that
can be used to disable the access to the processor serial number:
pliCatiO
MOV ECX , 1 1 9h
RDMSR
OR EAX , 0 0 2 (')0,0 0 0h
WRMSR
..
;reads MSR
;set s the 2 1 s t b i t
;wr i t e s MSR
After running CPU I D , EAX contains the most significant 32 bits (95-64)
of the serial number. This value from EAX must be saved before obtaining the
other 64 bits of the serial number. In order to access the other 64 bits, the
program must set EAX to 3 and then execute CPU I D :
MOV EAX , 0 3 h
CPUID
After running CPU I D , EDX contains the middle 32 bits (63-32) of the
serial number and ECX contains the less significant 32 bits (31-0). The
program must then concatenate the most significant 32 bits, EDX and ECX
before returning the complete serial number on 96 bits. The serial number
must be displayed as 6 groups of 4 hex digits.
12
1.9 Applications
Analyze the following programs CPU I D .CPP and CPU I D .ASM and
then run it on the PC. Analyze the results.
#pragma hdr s t op
# inc lude <conde f s.h>
# inc lude < s t dio . h>
#inc lude <Stdlib.h>
#inc lude <conio . h>
void decode_reg(int ) ;
void print reg(int reg ) ;
void PrintLeve l Cpuid( int l evel ) ;
vo i d cpu i d(uns igned inp ) ;
unsigned l ong Lax , Lbx , Lcx , Ldx;
vo i d cpu i d ( uns igned inp )
asm
. 59 6
mov eax , inp
cpu i d
mov Lax , eax
mov Lbx , ebx
mov Lcx , ecx
};
int main( )
int i;
uns i gned l ong l i , maxi , maxei;
/ * Print the information returned by CPUID f or the l eve l O * /
cpu i d(O ) ;
max i =Lax ;
for(i= O ; i <=maxi ; i+ + )
print f("\n\nCPUID l eve l %d11 , i ) ;
PrintLeve l Cpuid ( i ) ;
/*print the
the OxB O O O O O O O * /
cpu i d(OxB O O O O O O O ) ;
maxei= Lax ;
for( l i = O x B O O O O O O O ;l i<=maxe i ; l i+ + )
if (maxei= = O )
13
regi s t e r va lue * /
x &= Oxf f ;
printf ("%02x 11,x);
cpuid ( l eve l ) ;
print f ( 11\n
eax :
printreg (Lax)
print f ( " \n
ebx:
print reg ( Lbx )
e cx:
print f ( " \n
print reg ( Lex )
edx:
p r i nt f ( " \n
print reg ( Ldx )
") ;
;
") ;
;
") ;
;
") ;
;
14
dd
db
db
db
db
db
db
db
db
db
db
db
db
db
db
db
mov
mov
mov
and
call
cal l
mov
?
12 dup (? )
?
?
?
0
0
ax , data
ds , ax
e s , ax
sp not , 3
get_cpu id
print
ax, 4 c 0 0h
2 1h
s e t s egment reg i s t er
s e t s egment reg i s te r
al ign stack t o avo id
AC e rror
prog ram end
int
get_cpuid proc
.586
mov
i d_ f l ag , 1
s e t ind i cator f l ag
for CPU I D
paramet er for CPUI D
mov
eax , O
cpuid
dword ptr vendor_id , ebx
mov
; t e s t for I nt e l producer
dword ptr vendor_ id[ + 4 ] edx
mov
dword ptr vendor_ i d[ + 8 ] , ecx
mov
s i , o f f s e t vendor id
mov
d i , o f f set int e l id
mov
mov
cx, l ength int e l_ id
compare:
cmpsb
repe
i f I nt e l original ecx
cx , O
cmp
cpuid_data
jne
15
int e l _proc , 1
[intel - 1 ) , '
cpu id_data :
mov
eax , 1
cpui d
mov saved_cpu i d , eax
eax , O F O OH
and
eax, 8
shr
cpu_type , a l
mov
mov
mov
and
eax,saved_cpuid
stepp ing,al
st epp ing, O FH
mov
mov
and
shr
eax,saved_cpu id
themode l,al
themode l , O F
themode l , 4
end_get_cpu i d :
. 8086
ret
get_cpuid
..
endp
f e a tures
proc
ax
push
push
bx
push
ex
dx
; ver i fy i f the processor supports CPU I D
push
cmp
i d_f l ag,1
; if yes disp l ay informat ion
je
p r i nt_cpu id_data
dx,of fset id_msg
mov
mov
ah , 9h
disp l ay init i a l message
int
2 1h
print_cpu id_data :
cmp
cpu_type,5
p r i nt_cpu id_cont
j ne
dx,o ffset Pent ium
mov
mov
ah 9
2 1h
int
print_cpu i d_cont :
disp l ay " f ami ly : "
dx,o f fset f ami lymsg
mov
ah 9h
mov
2 1h
int
mov
a l , cpu_type
mov
byt e ptr dat aCR,al
add
byt e ptr dat aCR,3 0H
convert t o ASC I I
16
1.10
'
dx , of f s et dat aCR
ah 9h
2 1h
dx , of f s e t s t eppingmsg
ah 9h
21h
al , s t epp ing
byt e ptr dataCR , al
byt e ptr dat aCR , 3 0H
dx o f f se t dataCR
ah , 9h
21h
dx , of f s e t mode lmsg
ah , 9h
21h
a l , themode l
byt e p t r dataCR , al
byt e p t r dataCR , 3 0H
dx , of f se t dataCR
ah, 9h
21h
d i sp l ay CPU type
di sp l ay " s e r i a l no : "
convert t o ASCI I
di sp . s e r i a l number
convert t o ASC I I
display mode l number
dx
ex
bx
ax
start
Exercise
17
1st.
Year
CPUs
PC
Number of
transistors
1978-81
29,000
80286
1984
134' 000
1987-88
275,000
80486SX, 80486DX,
1990-92
1,200,000
3,100,000
Generation
2nd.
Generation
3rd.
Generation
4th.
Generation
5th.
Generation
5th.
Generation
Improved
6th.
Generation
6th.
Generation
Improved
1993-95
Cyrix 6X86
1996
AMD KS
1996
IDT WinChip C6
1997
3,500,000
Pentium MMX
1997
4,500,000
IBM/Cyrix 6x86MX
1997
6,000,000
IDT WinChip2 3D
1998
6,000,000
Pentium. Pro
1995
5,500,000
AMD K6
1997
8,800,000
Pentium II
1997
7,500,000
AMD K6-2
1998
9,300,000
1999
27,400,000
Mobile
Pentium II
Mobile Celeron
18,900,000
Pentium III
9,300,000
AMD K6-3
Pentium III CuMine
7th.
Generation
28,000,000
1999
22,000,000
2000
37,000,000
Pentium 4
2001
42,000,000
18
Data
Bus
Buffer
/RD
/WR
/CS
AO
Al
R/W
Logic
2.
word
Registe
block
CLKO
GATEO
OUTO
CLKI
GATE!
OUT!
CLK2
GATE2
OUT2
diagram
Through this buffer, the data is transferred from and to the circuit; this
is the way to program the working mode for the three existing channels, by
loading the counters y.tith the adequate time values or by reading the values
from the counters.
The counters (chan nels) 0 , 1 ,2 a re identical, independent, each one
being a 1 6-bit presetable countdown counter. Each cou nter can be selected
to cou nt BCD or binary. Their content can be read anytime without being
modified .
19
The R/W logic allows the circuit selection and the circuit registers
reading and writing control. The operations that take place for different
combinations of the control signals are presented in table 2 . 1 . The control
word register keeps the circuit programming information, which selects the
desired work mode for different channels.
/CS
/RD
/WR
Al
AO
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
Function
Loads coun t e r O
Loads c oun t e r 1
Loads coun t e r 2
Loads the contro l reg i s t e r
Reads coun t e r 0
Reads c oun t e r 1
Reads coun t e r 2
Not f unc t i on i ng
Unse l e c t e d c i rcu i t
Not func t i oning
the power, data and control signals, the typical signals for each channel are
the following:
Clk, (Clock)- are the clock entries (pulses) for the counter. The maximum
allowed frequency is 2 ,6 MHz (for 18254 is 1 0 MHz)
Gate.- these entries can work as validation gates for the clock entries or as
counting start pulses, depending on the programming mode of the circuit.
Out,- represents the channels outputs, whose evolution is dependent on
the circuit-programming mode.
8
CLKO
GO
9
11
CLKI
GI
15
14
OUTO
5
4
3
2
13
n
23
19
20
ll
10
CLKl
G2
OUTl
18
16
11
cs
8253
{j\ .
00
01
10
11
0- binary counting
00- reads counter
1- BCD counting
0 1 - reads/loads low byte
1 0- reads/loads h igh byte
1 1 -reads/loads low and then 000 - mode o ( lntrerrupt on Termi n al Count)
high byte
00 1 - mode 1 ( Programmable One-Shot)
x 1 0 - mode 2 ( Rate Generator)
- cou nter 0
x 1 1 - mode 3 ( Square Wave Rate Generator)
- cou nter 1
1 00 - mode 4 ( Software Triggered Strobe)
- cou nter 2
1 0 1 - mode 5 (Hardware Triggered Strobe)
- i l legal command
21
cou nter can be read without affecting the output. If a rising edge i s present
at the GATE input at some time during the pulse, it produces a new start of
the cou nting from the last value stored in the counter (fig.2.4 )
.
Mode 2 Rate Generator (Divide by n counter). The output wil l be " 1 " for
(n- 1 )TcLK periods after the control word and the counter value loading and it
wil l became "O'' i n the n-th period . If the GATE input is forced to "O'' during
the cou nting, the output will become " 1 " and when the GATE input returns
in " 1 " , the cou nter will decrement again from the in itial value; the GATE
input can be used for the cou nter synchronization. The counter
decrementation starts immediately after the last data byte loading and if the
cou nter is reloaded d u ring this period , the change wil l be reflected in the
next period .
-
Mode
CL Ki
Interrupt on Terminal
Count
WR
OUTi
(n= 4)-----------+---+---+---+--/
------
Mode
CL Ki
GATE
OUTi
(n=3)
Programmable
Mode
CL Ki
(n=3J
Mode
CLKi
WR
OUTi
(n=4)
Mode
CLKi
___,
21
0.
Rate
WR
OUTi
Generator
Generator
__..
...__
0(4)
2
4 Software Triggered Strobe
3
I
WR
OUTi-----1--'---
Mode
CL Ki
GATE
4
0
--+-- -- -(n=4,
1-l1-- -+-+- --:_
1
-+
OUTi
____,
Mode 3
........-- u.
""' L(
e.ve.......
JJ
,.Z
(?1+1,Yi...
-:.
C'
(j
"
"
"
"
I
B
Low
Or
Fal l ing Edge
Rising Edge
- Di s ab l e s coun t i ng
- Di s ab l e s Counting
- S e t s output
immediat e ly high
- Di s ab l e s counting
- S a l e s output
immediat e ly high
- Di s ab l e s counting
High
- Enab l e s
Counting
- I nitia t e s counting
- Re s e t s output a f t e r
next c l ock
- Re l oads coun t e r
- I nitiat e s counting
-
Initiat e s c ounting
- Enab l e s
counting
- Enab l e s
c ounting
- Enab l e s
c ounting
Initi a t e s c ounting
PC
For compatible IBM computers, one uses a timer circuit for fulfilling
d ifferent functions. The three circuit channels are used for:
23
' l'
BO Bl
CLKl
DRQO (PC-XT)
OUTl -----
GATEl
PORT B (61H)
PIO-I8255A
org l O Oh
a s s ume c s: code ,
ds : c ode,
; s t a r t s at l O Oh a f t e r P S P
e s : c ode , s s : code
25
; = =ma in p rogram da t a
mes_in db O dh , O ah , " Generat ing notes f rom I V o c t ave , O dh , O ah , " $ "
mes out
db O dh , O ah , 11 End 11 , 0 dh , O ah , 11 $ 11
; - - PLAY_NOTE : Generat i ng not e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - BL = note numb e r f rom Do , o c t ave IV
; - - Input
DL = note
l ength in 1 / 1 8 second mu l t ip l es
;-Output
- Reg i s t e rs : AX , ex , ES and FLAGS are mod i f i e d
i = = = = = = = == = = = = = = = ===== = = = = =
play_not e p r o c near
push dx
push bx
mov al , O b 6 h
out
xor
shl
mov
out
mov
out
in
or
mov
mov
out
play : cmp
j ne
; No t e done ?
; No
> wa i t
- -
26
a l , 6 lh
; reads l oudspeake r
and
a l , l l l l l l O Ob
; S e t s to O b i t s B O , B l
out
61 h , a l
pop
bx
; D i s ab l e s l oudspeaker
; Recove rs BX and DX f rom s t ack
dx
pop
ret
cont ro l b i t s
pl ay_not e endp
; - - new u s e r int e r rupt ( l Ch ) of the t imer - - - - - - ; ca l l e d 1 8 t ime s p e r s e cond
proc f a r
sound_t i
dee
c s : nr s
j ne
end st
; De c rement s coun t e r
; i f # 0 j ump , = 0 done
mov
c s : end_s , O
; pa s s e d note l eng th
; back
end s t : i re t
sound ti
;
==
endp
var i ab l e s
t ime_o l d
nr s db
dw
(?)
db
end s
not e
= =
f o r rout ines = = = = = = = = = = = =
( ? ) , ( ? ) ; o l d addre s s f o r t ime r i n t e r rup t
; rema i n i ng l ength f o r a not e , i n s e c ond
; l / 1 8 mu l t ip l e s
( ? ) ; i nd i c a t e s i f the not e was gene r a t e d
dw 4 5 6 0 , 4 3 0 4 , 4 0 6 3 , 3 8 3 4
dw 3 61 9 , 3 41 6 , 3 2 2 4 , 3 0 4 3
; f rom o c t ave IV :
dw 2 8 7 3 , 2 711 , 2 5 5 9, 2 4 1 5
; Fa , S o l , S o l # , La , La# , S i
End
Do , Do# , Re , Re # , M i
= = = = = = = = = == = = = = ===================== = = = = = = = = = = = = = = =
code ends
end sound
; p rogram end
*-------------------------------------------------------------*
I
'1 '
CLKO
GATEO
OUT !
OUTO
'1 '
CLK2
GATE2
D
CLK
SET
r--+-''\/\l\--o+5
Fig . 2 . 6 The timer channe ls connection
27
OUT2
15
14
13
12 .
11
10
9
7
t-=--U...
3
6
11
Al
E!1....
lll!B
RD
AOW
AOR
07
D6
D5
D4
D3
D2
01
00
\ ' \
O IJT'2
G2
CLK2
O UT1
G1
CLK1
O UTIJ
GO
CLl<D
SYS CLK/16
8253
28
3 . TH E REAL TI M E C LO C K AN D TH E C M O S M E M O RY
3.1
General i nformation
AD O - AD 7 .
AS
Bus
DS
InterfacE
R /WR
RST
.
.
- -
D O - D7
DO - D7
'"
A O - A7
'
/CS
RTC
onur
DO -D7
,. n _ ,. .,
CMOS
Memory
AO - A7
I RQ
CKF S
PS
P ower
management
I- -
Addre s s Data
Bus
Fig . 3 . 1
The
MC 1 4 6 8 1 8
30
Bus
block diagram
3.2.2
ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7
RESET
IRQ
AS
OS
PS
CKFS
SQW
cs
CKOUT
RiW
23
21
31
3-0
6-4
Upda t e in p r og re s s
DV2 - DVO
( UI P )
Rate s e l e c t o r f o r SQW :
RS 3 - RS O
Register B {R/W}
I
S ET
7
SET
6
PIE
5
AIE
4
UIE
3
SQWE
DM
24 / 1 2
DSE
IRQ F
6
PF
AF
UF
2
0
1
0
0
0
I RQ F - i nterru pt req u est flag is active ("1 ) if at least one of the followi n g cond itions
"
is tru e : PF = P I E = 1 ; UF = U I E = 1 ; when thi s bit is " 1 " , / I RQ pin is low . The reg i ster
bits reset at the reg i ster read i n g or when the signal /RESET i s active
PF - period ic interrupt flag is set on " 1 " when a certa i n front is detected at the
d ivider cha n n e l . Its periodicity is commanded by the RS3 - RSO b its .
AF - alarm i nterrupt flag activates if cu rrent ti me equals alarm ti me and generates
an i nterru pt if flag A I E = 1
U F - U pd ate - ended i nterru pt flag , is activated after every u pd ati ng cycle. If U I E =
1 , the U F activation sets bit I RQF and activates i nterru pt signal /I RQ .
7
VRT
6
0
5
0
4
0
2
0
1
0
0
0
VRT - Val i d RAM a n d Time i n d i cates RAM content status depe n d i n g on the
tension level o n pin PS. VRT = O i n d i cates that the level on PS i s low, so the
battery is empty.
To read the content of a CMOS memory location one must follow the
next steps:
Send to port ?Oh the address of the location that wil l be read
Example:
mov a l , addr e s s
out 7 0 h
al
in a l , 7 1h
,
To write a location of the CMOS memory one fol lows the next steps:
Send to port ?Oh the address of the location
Write the new value to port 7 1 h
Example:
mov a l , address
out ? O h
al
mov a l , new_value
out 7 l h
al
,
3.4
The operating system allows user access to the system clock (used
by B IOS) and to the real time clock (which updates independently) through
B I OS services I NT 1 Ah . For data reading from CMOS - RTC , the operating
system provides the fol lowing services ( I NT 1 Ah ) :
Reads the clock from CMOS -RTC
CH = hour in BCD (EX: CX= 1 1 49 H = 1 1 :49)
CL = minutes in BCD
D H = seconds in BCD
CY = 1 when RTC is locked
AH=03h
Time setting in CMOS-RTC
C H , CL = hours, min utes in BCD
Input:
D H = seconds i n BCD
D L = 1 sets automatic change winter/summer time
AH=04h
Reads date from CMOS
Output:
C H = century in BCD (Ex: CX= 1 987h= 1 987)
CL = year i n BCD
D H = month i n BCD (Ex: DX=03 1 2h=March)
D L = day in BCD
C F = CY = 1 if RTC is locked
AH=OSh
Sets date in CMOS
Input:
C H , CL = century, year in BCD
DH, DL = month , day i n BCD
AH=06h
Sets the RTC alarm . At the set time, the user i nterrupt routine is
called from the address corresponding to INT 4Ah . It may be only one
alarm activated .
AH=02H
Output:
34
Input:
Output:
AH=07h
Para l l e l Port
00
01
013
11
in s t a l l e d
- S e r i a l p r i n t e r i n s t a l l ed
Dll -09
Port RS2 3 2
DB
07 - 0 6
F l oppy d i sk driver
D3 -D2
10
012
D S - 04
Not
AX
000
Not
001 . . 111
1. ..... 7 port s
i n s t a l l ed
instal led
- DMA p r e s ent
V i de o Mode
RAM memory s i z e
00
01
10
11
00
Re s e rved
01
4 0 c o l o r c o lumns
10
8 0 c o l o r c o l umns
11
Monochrome TTL
00
01
1 6k
10
32k
11
64k+
Dl
DO
- D i s k un i t
ins t a l l e d
INTllh
in
AX
byt e retur ;
asm {
mov a l ,Address
out Rt cA d rPort , a l
in a l ,Rt cDa t aPort
mov retur,Al
};
return
( retur ) ;
/ / Fun c t ion t h a t wr i t e s
to a l o c a t i on f rom
CMOS
asm {
mov
out
mov
out
};
a l ,Address
Rt cAdrPort,a l
a l Conten t
Rt cDataPort,al
,
vo i d ma i n ( vo i d )
whil e ( b i oskey ( l ) = = O )
c l rscr ( ) ;
i f ( ! ( CmosRead ( D i agnose ) & l 2 8 ) )
36
/ / reads
p r i nt f ( " RTC
RTC
emp l oy mode
i s u s ed
/ / r e a d s hour
p r i n t f ( " The
t i me
in
f rom r eg i s t e r B
Cmo s Re a d ( S e conds ) ) ;
/ / reads
da t e
else
p r i nt f ( " At t ent i on !
};
de l ay ( S O O ) ;
37
; .
Poll i ng the microprocessor tests the devices one by one and serves
the one that requires a special attention . Polling can be used in the
case of some devices or in microprocessor systems but not in PCs,
because it is too slow. Many processing cycles can be lost, because
most of the times the devices response is negative. In add ition, the
devices need data transfer or attention with d ifferent freq uencies (e.g .
the mouse needs much less attention than a hard-d isk when i t is
activated for data transfer).
The above tasks are solved differently for some microprocessors (e. g .
Z80). The i nterrupt system is distributed to each circuit from t h e Z80 family
and the i nterrupt priorities are solved depending on the circuit position on a
priority chai n called "daisy-chain". The circuits also provide the
corresponding i nterrupt vector. The PIO Z80 circuit from figure 4 . 1 has
39
maxi mum priority, being the first component on the priority chain con nected
through the I E I ( I nterru pt Enable I nput) and I EO ( I nterrupt Enable Output)
signals. The P I C (Programmable I nterrupt Controller) 1 8259A circuit is
used in PC.
'I'
IE I
PIO
CTC
Z80
INT
IEO
IEO 1---- IE I
IEO 1---- IE I
Z80
INT
INT
INT
(Z80)
40
/ I'NTA
Data
Control Logic
/SP//EN
I'NT
I'NTERNAL
.-------. BUS
Read/Write
Logic
Cascading
Logic
IMR
I /O
2 0H
2 1H
2 0H
2 0H
2 0H
2 1H
I
I
0
0
0
0
S igni f icance
Re ad IRR , I'sR
Re ad I MR
Wr i t e OCW2 i f D4 ,
Wr i t e OCW3 if D4 =
Wr i t e I CWl , i f D4
Wr i t e OCWl , I CW2 ,
D3
00
1
= 1
I CW3 , I CW4
=
IRQ7
I RQi
=
=
IRQ6
IRQS
IRQ4
IRQ3
IRQ2
IRQl
IRQO
Wl
WO
W2
= 0 there is no i nterru pt
= 1 there is a n interru pt
Mi
1Kl
=0
= 1
M6
MS
M4
M3
M2
Ml
MO
W>oJY2\,.Q 'S
The user does not have access to this register. The register
compares the current i nterrupt priority level with the one from ISR.
42
Name
/CS
/WR
I /O
Pin
/RD
AO
27
I/O
4
11
I/O
12 14
D7
DO
CASO CAS2
-
/SP/ /EN
I/O
16
INT
17
IRO - IR7
18 25
/ INTA
26
Function
C i rcu i t s e l e c t i on
Ac t ive on ' 0 ' l eve l when c ommand words are
rece ived f rom the m i c ropro c e s s o r
Act ive on ' 0 ' l eve l when reading I 8 2 5 9A
c i rcu i t s t atus
AO together w i t h / CS , / RD , / WR de t e rmine
command/ s t at u s
t he
word
wh i c h
t he
m i c roproc e s sor wr i t e s / reads i n / f rom I 8 2 5 9A
c i rcu i t .
Norma l ly
is
conne c t e d
to
0
addr e s s l ine (Al f o r I 8 0 8 6 )
B i di re c t i onal
dat a
l in e s
for
cont ro l ,
s t atus inf orma t i on t r an s f e r and inte rrup t
ve c t o r t rans f e r .
For c a s cad ing
S l ave Program/ Enab l e Bu f f e r i s a doub l e
func t i ona l i ty p i n .
I n buf f e red mode
is
used a s a bus tran s f e r cont r o l s i gna l and
in unbu f f ered mode , S P = l f o r MASTER and
S P = O for SLAVE
output
INTe rrup t
c onne c t e d
to
INT
proc e s sor input ; t hrough i t , the interrupt
reque s t are t ransmi t t ed
a s ynchronous i nput s
( In t e rrup t Reque s t )
c onne c t e d to t he o f f - l ine c i rcu i t s wh i ch
t he
to
proc e s sor ,
inte rrup t s
gene rat e
u s i ng P I C I 8 2 5 9A
( INTe rrup t Acknow l e dge ) - u s e d f o r inte rrupt
acknowledge and int errup t ve c t o r reading
-
CASO
CA51
CAS2
43
I LTIM I
SNGL
ICW4
T7
T6
TS
T4
T3
Ti are bits 3 to 7 from the code sent in the second /I NTA cycle. The
n u m ber (type) of the interrupt vector for single mode is 8 ( I RQO), 9
( I RQ 1 } , . . F ( I RQ7).
.
S7
S6
SS
S4
S3
S2
Sl
so
IDl
IDO
ID2
SFNM
BUF
M/ S
AEOI
PROC
BUF M/S
0
SIGNIFICANCE
l
l
No externa l da t a buf f e r
Ext e rnal dat a buf fer ; s l ave P I C
Ext e rna l
da t a
buf f e r ; ma s t e r P I C
M7
M6
MS
M4
M3
M2
EOI
Ml
MO
Mi = 0 u nmasked level
= 1 masked level
SL
LO
Ll
L2
R (Rotate) = 1 : until the. next OCW2 . the. last served i nterru pt gets 8
lowest priority
SL (Specific Level ) = 1 : specific EOI is used . See the table below for
priority mode selection.
EOI (End of I nterrupt) = 1 : P I C is annou nced at the end of the served
interrupt procedu re
L2 , L 1 , LO: contain the binary code of the served priority level
SL
EOI
0
1
0
1
1
- 0
0
0
1
Significance
Rot a t e in AEOI mode - C l e a r
Non - spe c i f i c EOI
No e f f e c t
Spec i f i c EOI
Rot a t e in AEO I mode - S e t
Rot a t e t o non - spec i f i c EOI
Set s p r i o r i ty
Rot a t e t o spec i f i c AEO I
0
1
ESMM
SMM
PR
RI S
ES MM S MM
Signi ficance
RR
RIS
Signi ficance
No e f f e c t
IMR s e l e c t i on
Spec i a l mask
reset
Spec i a l mas k
s e t t ing
I RR s e l e c t i on
I S R s e l e c t i on
ICWl
ICW2
NO
NO
ICW4
Ready for
interrupts
(OCW)
4.4
command for erasing it before interrupt service routine ends. I n AEOI mode
the bit stays in 1 until the last i nterrupt acknowledge /I NTA cycle ends. As
long as the I S R bit is set, any other interrupt requests are ignored , except
the more prioritary ones that are served (if the microprocessor is set to
accept the interrupt requests).
EOI mode
The I S R bit corresponding to the served i nterru pt i s automatically
reset i n AEO I mode (without using a special command) or using a
command word activated before EOI mode interrupts serving routi ne ends.
In cascaded mode, the served interrupt corresponding bit has to be erased
from both master and slave .
AEOI mode
Automatic End of I nterrupt - is activated when AEOI bit from I CW4 is
1 and it is equ ivalent with a non-specific EOI command activated when the
interrupt recognizing cycle ends (the third for 1 8080 and the second for
18086 mode).
Automatic (non-specific) priority rotation
There are cases when an off-line device after being served becomes
the last one in the priority list and it wil l not be served u ntil the other seven
off-line devices from the priority list wil l be served properly.
Specific Priority Rotation
The user can dynamically change the priority order from the program.
A low priority level is defi ned and the other levels will be modified according
to this one.
I nterrupt masking
Each i nterrupt request i nput can be masked using I M R, which is
programmed with OCW.
Special mask mode
In this mode the interrupt req uests with the same priority, as the
served i nterrupt, are i nval idated but the more prioritary or less prioritary
than the served one a re accepted . This mode is programmed with ESMM =
1 and S M M = 1 i n OCW3 .
Polling mode
In this mode, the i nterrupt system is invalidated at the microprocessor
level. The i nterrupt requests are scanned using a polling command . Polling
mode is set with P = 1 in OCW3. The 18259A controller handles the fi rst
reading cycle (/RD and /CS) as the first cycle from the i nterru pt accepting
sequence . The most prioritary request bit is set i n ISR.
47
17
INT
CASO
C A S1
CAS2
CASO
CAS1
CAS2
I RO
IR1
IR2
IR3
IR4
IRS
IR6
IR7
17
IRO
IR1
I R2
IR3
I R4
IRS
I R6
IR7
INT
PIC SLAVE
P I C MASTER
/EN
con nected to the master I Ri in puts. If a slave i nterrupt request is active and
th is i nterrupt request is the most prioritary one, the master wil l validate the
corresponding slave through the cascading l ines, so that the slave put the
interrupt routine address or the interrupt type on the data bus.
4.5
( mo s t p r i or i t ary )
CO T ime r
08h '
IRQl
Keyboard
09h
I RQ2
Not used
OAh
I RQ 3
COM2
COM l
O Sh
I RQ4
I RQ S
Hard Disk
O Dh
I RQ 6
F l oppy D i sk
O Eh
I RQ 7
LPT
O Fh
IRQO
O Ch
Priori ty
Vec tor
0
1
0 8h
0 9h
2
-
OAh
11
O Bh
12
O Ch
13
O Dh
14
O Eh
Typical
Employment
T ime r
Keyboard
Ca s c ading
( I RQ S - 1 5 )
COM2 ( s e r i a l
port )
COMl
Sound B l a s t e r
( SB ) , HD
Fl oppy D i s k
Con t ro l l e r
49
O ther Ut i l i t i e s
-
15
O Fh
7 0h
71h
10
72h
11
73h
12
74h
- PS / 2 mou s e
13
75h
14
7 6 11
15
10
77h
NC ,
PC!
NC ,
PCI
NC ,
Coproce s s o r
( F PU)
IDE - 1 channe l
( HD )
IDE - 2 channe l
SB , S C S I adap t e r ,
dev i c e
SB , IDE channe l ,
dev i c e
SB , S C S I adap t e r ,
VGA card
NC , SB , S C S I adap t e r ,
I D E channe l
-
SCS I adap t e r
SCSI adap t e r , NC
4.6 Exercise
a . Study the architecture a n d programming mode for the 1 8259A controller
and the employment of the controller in the I B M-PC compatible
com puters.
b . Write a test program for P I G .
c. Where can we find the addresses of the interrupt handler routines i n
IVT, for the req uests from the slave PIG inputs?
d.
f.
al , 2 0h
2 0h , al
50
S
CLK
Q t-----.
'I'
SYSCLK/16
GATE2
:
2 -....;::,_ _
OUT2 i---=u1
CLI<2
IRQ7
(B21 -ISA)
For the interrupt source 1 the application I NT? .ASM presented below
was developed . The application counts the interrupts arrived on the line ' 1 '
from the pushbutton (and cleaned with a RS Fl i p-Flop) and signals it on the
screen .
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - -
PAGE 6 0 , 1 3 2
T I TLE INT7
COMMENT * Gene rat e s i n t errup t s f rom a pus hbu t t on on I RQ 7 *
STACK SEGMENT PARA STACK ' STACK '
512
DUP ( ? )
DW
ENDS
STACK
; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - -
51
- -
t
(l 'I-
'V ,
- -
u VP}(
_
'-
52
; be ep at exi t
; end program t hrough
; ex i t DOS func t i on c a l l
PROC NEAR
IRQ7 INT
; - - new inte rrupt rou t ine - - pu sh ax
push ds
mov ax , data
mov ds , ax
mov ah , O eh
mov a l , cha rac t e r
int l Oh
; chara c t e r d i s p l ay
inc chara c t e r
mov a l , 7
gene ra t e s s ound
int l Oh
ov a l , 2 0 h
; EOI
out 2 0 h , a l
pop ds
pop ax
iret
; re turn
END
; = = End = = ===-== = = = = = = = = = = = = = = = = = = = = = = = = = = = =
code ends
; CODE segment end
end ma i n
; program end
* - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * ,
5.2 Exercise
a. Analyze the I NT7 .AS M application and run it.
b. Rewrite the application :
using the controller i n poll i ng mode
using software cleaning instead of the fli p-flop.
c. Adapt the application for the second interrupt source (channel2 - timer)
d . The thi rd i nterrupt source i s a phone dial disk (see fig u re 5.2). Write a n
application that takes the i mpulses from i t a n d d isplays the d ialed
n umber. Attention to cleaning!
53
PC
.
,-........................... -.....................................................................
! PARALLEL
+5
PORT
10
-ACK
Dial disk
4K7
18-25
GND
IR 7
! - IRQBN
l
11. '" 1
'
lft>l"Ji
..
. ; ' . . .
54
...
6. 1
OMA
M
0
IQ
IQ
GI
:" ......................................
;
l . . . . ._
....... , , . , , . , , , , , . . , ....,............
tJ
0
M
Ill
0
M
- HOLD
::fl
HLDA
........
.. .
i DMA
. .. . . . . . .. .
(>
. .
.. . . . .
'
'
.. .
1 11
..
I
I
......................
.......................................................
1 :
'
1 '-------..39
HLDA _
Addre s s Bus
Data Bus
-control Bus ..
'
'
, _
--
DMA
Con t ro l l e r
(;.',
'
'
DREQ
DAC K _
.-
'
'
1 111
P e r i phe r a l
D ev i c e
. . . . . .
56
command
the circuit
"O" which
externally
CS/ ( 1 1 ) : (Chip Select) input active on "O" used to select the circuit as a
peripheral 1/0 device d u ring the inactive cycles
READY (6): i n put used to synchronize the circuit with the memories and the
slow peripheral devices by prolonging the M E M R or M E MW impulses
AEN (9): (Address Enable) c;> utput used for the command of a latch register.
When AEN= 1 , the bits A8 . . . A1 5 of the address provided by 18237A are
written to the address bus.
ADSTB (8): (Address Strobe) output that controls the loading of the
address byte A8 . . . A1 5 in a register
M EMW/ (4) : (Memory Write) TS (three state) output used when writing data
to the memory during a O MA transfer that is either a Write type or a
memory -memory type
MEMR/ (3): (Memory Read) TS output similar with M EMW/, but for reading
from the memory
IOR/ ( 1 ) : (1/0 READ) bidirectional TS signal, active on "O" used by CPU to
read the control reg isters i n the i nactive cycle; in the active cycle it is used
for taking data from a peri pheral device in a OMA writin g transfer
IOW/ (2) : ( 1/0 WRITE} bidirectional TS signal , active on "O"used by CPU to
program the circuit in the inactive cycle; in the active cycle it is used to
transfer d ata to a peri phera l device in a DMA read ing tra nsfer
Req uest/acknowledge signals for microprocessor bus control
DREQi ( 1 9- 1 6): i=0,f 1 ,2 , 3 (OMA Request) inputs on which the peripheral
devices con nectec fo the circuit send asynchronous signals of OMA
transfer request on the afferent channel . The active level of signals and the
channel priorities are programmable. DREQ line must be maintained active
until the corresponding DACK line becomes active .
DACKi (36/37/ 1 4/1 5): (OMA Acknowledge) used to signal the
execution of OMA req uest to the peri pheral devices that req uested the
O MA transfer. The active level is programmable, after using RESET they
are active on "O"
H RQ ( 1 0): ( Hold Request) output used by 18237A to request control over
the buses
H LDA (7): ( Hold Acknowledge) input activated by the microprocessor,
indicatin g that the bus is ready for the OMA transfer. The signal becomes
active ( H ) after at least a clock period after HRQ is activated
Address l i nes
AO . . . A3 (29-26): TS, bidirectional address lines; these are outputs in the
active cycle and contain the less significant 4 bits of the address and they
are i nputs in the i nactive cycle, used by the CPU to address the i nternal
reg isters as ports .
57
A4-A7 (24-2 1 ) : address lines, outputs that work only during D MA transfer,
providing A4-A7 bits of the address provided by DMAC .
Data l i nes
DO-D7 (3 1 -35, 38-40): bidirectional TS lines connected to the data bus of
the system . In the 'program state' , on these l ines the address, state ,
temporary or U C cou nting registers are written or read . I n the active cycle
they represent the address bits A8-A 1 5 , being strobed by the ADSTB signal
to be memorized in a n external latch .
6.2.2 The i nternal block diagram of DMAC 18237A
I n the block diagram (fig.6.2), the following modules can be noticed :
DE CREMENT
TEMP .
I N C / DECR
WORDS
EMP .
COUNTER ( 16 )
T I M I NG
ADS T B
/ MEMR
16
&
CONTROL
/ MEMW
ADORES
EG I S TER ( 1 6 )
F o r e a c h channe l
READ BUFFER
16
R / W BUFFER
BAS E
BASE
ADDR .
CRT .
CRT .
WORDS
ADDR .
COUNT
( 16 )
(16)
(16)
COMMAND
WORDS
CONTROL
COUNT
(16)
AB . . Al S
DO - Dl
DREQ
0-3
8
4
COM ( S )
P R I OR I TY
ENCODER
AND
MAS K ( 4 )
LOG I C
4
8
DBO . . D B 7
PRIORITY
ROTAT I NG
DACK
0-3
R/W
REQUEST ( 4 )
MODE
-'----- _....'---
STATUS
(8)
TEMPORARY
(8)
( 4X6 )
Priority control block: solves the orderi ng problem of the OMA transfer
req uests executing for multiple concurrent channels
4 . OMA transfer channels: the circuit has four programmable independent
channels. On every chan nel , there are five reg isters (register for the
main address, main words counter, current address, current words
counter, mode register).
The 1 8237A circuit has a memory capacity of 344 bits. The registers
significance is:
3.
REGISTER
REGISTER LENGTH
B a s e addre s s
B a s e words coun t e r
Current addre s s
Current words coun t e r
Temporary addre s s
Temporary words coun t e r
S t at u s
Command
Temporary
Mode
Mask
Reque s t
16
16
16
16
16
16
8
8
8
6
4
4
4
4
4
4
1
1
1
1
1
4
1
1
Base address register (1 6 bits): contains the first address the transfer is
made from. This register can be written using the progra m , but it cannot be
read .
Base counter register (1 6 bits) : contains the number of words to be
transferred . It can be written , but it cannot be read .
Current address registers (1 6 bits): contains the value of the transfer
address. This address is automatically increased or decreased after every
transfer. If the channel is programmed with auto i n itialization, the value of
the Base address is loaded in this register.
Current counter register (1 6 bits): determines the n umber of transfers left to
be executed . When it switches from OOOOh to FFFFh, a TC (Terminal
Count) signal i s generated .
Mode register (6 bits): g ives information about the transfer mode and it is
written d u ring the circuit programming
Temporary address register (1 6 bits): contains the temporary address on
16 bits i n the case of memory- memory transfer
Temporary words counter register ( 1 6 bits) : has the same function as the
current cou nter register, but it is used with the temporary address register
59
Temporary data register (8 bits): holds the current byte transferred i n case
each channel . The mask bit is switched to " 1 " when the channel reaches
/EOP, if it was not programmed for auto i nitiaiization .
Request register (4 bits): one for every channel and it signals that a O MA
request arrived on the afferent channel . The priority control block manages
it. A TC or EOP determi nes the erasing of the corresponding req uest.
Channel Port ( * )
OOH
O OH
O lH
O lH
02H
02H
03H
03H
04H
04H
O SH
O SH
0 6H
0 6H
07H
07H
0
0
0
0
2
2
2
2
3
3
3
3
*
**
( w )
R
w
R
w
R
w
R
w
R
w
R
w
R
Slave circuit at P C - AT
Regi s ter
B a s e addre s s channel 0 D MA
Current addre s s channe l 0 DMA
B a s e c oun t e r channe l 0 DMA
Current counter channe l 0 DMA
B a s e addre s s channel 1 D MA
Current addre s s channe l 1 DMA
B a s e count e r channe l 1 DMA
Current coun t e r chann e l 1 DMA
B a s e addre s s channe l 2 DMA
Current addre s s chann e l 2 DMA
B a s e c oun t e r channe l 2 DMA
Current coun t e r chann e l 2 DMA
B a s e addre s s channe l 3 DMA
Current addre s s chann e l 3 DMA
B a s e coun t e r channe l 3 DMA
Current coun t e r chann e l 3 DMA
60
r eg i s t e r
(#)
Command re g i s t e r
S o f tware
r e que s t s
I n d i v i du a l
Mode
ma s k s
r eg i s t e r
reg i s t e r
r eg i s t e r
f l ip - f l op c l e a r
I n t e rna l
Temporary r eg i s t e r
Re s e t
I 8 2 3 7 A -ma s t e r
C l e a r ma s k r eg i s t e r
Wri t e b i t s
*
of
c l e ar
ma s k r eg i s t e r
Port*
Port**
O BH
DOh
0 8 Ho .
DOh
0 9H
D2h
OAR
D4h
O BH.<.
D6h
O CH
D8h
O DH
Dah
ODH
Dah
OEH
DCh
O FH
DEh
R I W Operation
R
w
w
w
w
w
w
w
w
( in al ,
( out
(
0 8h )
OBH,
out
0 9H ,
al)
al )
( out
OAR ,
al )
( ou t
OBH ,
al )
( out
O CH ,
al )
( in al ,
ODH )
( out
ODH ,
al )
( out
OEH ,
al )
( out
O FH ,
al )
**
DACKH
D RQL
EWR
RPY
CTIM
D I SAB
COAHE
0
M-M
REQUEST REGISTER
6
-
I -
SCl
0
0
1
1
sco
0
1
0
1
I - I
SRQB
SCl
Signi ficance
Select s
Selects
Selects
Selects
61
channel
chann e l
channe l
chann e l
0
1
2
3
0
sco
MASK REGISTER
7
S M KB
I SCl
SMKB
SCl
0
0
1
1
0
sco
Signi f i cance
Select s
Select s
Selects
Selects
0
1
0
1
channe l
channe l
chann e l
channe l
O
1
2
3
mask
mas k
mask
ma sk
bit
bit
bit
bit
M O D E REGISTER
SMl
SMO
AUT0 1 =
=
DECR =
=
0
1
0
1
OECR
AUTOI
SOTl I SOTO
SCl
SOTl
Selects
Selects
Selects
Selects
SOTO
0
0
1
1
0
1
0
1
SMl
0
0
1
1
0
sco
Signi ficance
0
1
0
1
0
0
1
1
SCl
channe l
channe l
chann e l
channe l
0
1
2
3
Signi ficance
Te s t ing
Wr i t e i n memory
Read f rom memory
I l l egal
I f SMO = O and SMO = l
SMO
Signi ficance
0
1
0
1
Reque s t mode
Byt e mode
B l ock mode
Cas cade mode
SMKl
SMK2
62
' O
SMKl
I I SMKO
STATUS REGISTER
RQ3
TCi
RQ2
RQl
RQO I TC3
TC2
TCl
TCO
64
D R QO
OAC l<D
Ch
ORQ1
OACK1
HRQ
H LOA
Ch
O R QO
D AC l<D
HRQ
C e nt r a l
Un i t
H LDA
Ch
DRQ1
DACK!
F loppy
Ch
Ch
Ch 2
D R Q2
O AC K2
Ch 3
O R Q2
OACK2
disk
i nt e r f ac e
O R Q3
OACK3
8237A Slave(Oh)
8237A Mester(COh)
prioritary, channel 0 - the most prioritary. For rotating priorities , the channel
whose req uest was executed most recently wil l become the less prioritary
one. This mode prevents the system monopolizing by one channel.
BUS EM
AO -A15
f--
EN
HLDA
'
A 0 -A3 A4 -A7 / C S
I 8 2 3 '1A
HI.DA
C LK
C LK
/IO
/ I O''
/MEHR
/IIEHN
DBO-DB7
HllQ
HOLD
CPU
"
Fi g . 6 . 4
'- / O E
AD S TB
DB O -DB
STE
Jl8 -A15
8282
( Sb i t l at c h )
;.
.
.
DATA BUS
I n terfacing
66
I 8 2 3 ?J!. : i ':o
the
sys tem
./
4-7 can execute 1 6-bit transfers, while channels 0-3 can execute only 8-bit
rransfers , - for PC-XT. Since the controller, by its desi g n , can provide
only 8-bit transfers because of increasing I decreasing the internal address
by only one byte register, after every transfer it is necessary to establish the
mode of execution of the 1 6-bit transfers . The solution for i ncreasing I
decrea _by_-2 the address that the controller gives on the bus is as it
follows: the address l ines that come from OMAC wil l be postponed by 1
related to the l i nes of the address bus, being equivalent to a multiplication
by 2. On the programming level, the 1 6-bit transfer i nvolves certain
changes:
1 . The memory address is reduced by half, being automatically doubled by
the hard realized offset
2 . O MA 1 6-bit tra nsfer can begin only from even memory addresses
3 . The block length wil l b e calculated i n words, not bytes; maxi mum length
becomes 1 28 Kbytes
4. By choosing as an address for the beginning of the transfer the
beginning of a 64 Kbytes page, we make sure that the OMA segment
wi l l not be exceeded
O MAC is able to control only the address lines AO-A 1 5, for that the
maximum block length to be transferred has _64 Kb ytes. It is the PC
designer d uty to control the other address bits A 1 6-A 1 9 for PC-XT (A 1 6A23 for PC-AT) i n order to place the block to be transferred anywhere i n
the 1 Mo memory or the 1 6 Mo memory o f the PC. T h i s can be
accomplished as presented in fig .6.5, by add ing a page register of !!- or 8
bits. For this purpose , the 74LS 1 70 circuit is used for Felix PC
- - XT and
74LS6 1 2 for PC-AT.
Page registers corresponding to different cha nnels can be loaded
employing 1/0 instructions, using the fol lowing port addresses reserved for
this:
PC - XT :
PC-AT :
8 l h f o r channe l 2 DMA
( addre s s b i t s 1 6 - 1 9 )
( addre s s b i t s 1 6 - 1 9 )
8 2 h f o r channe l 3 DMA
8 3 h f o r channe l s O and 1 DMA ( addre s s b i t s 1 6 - 1 9 )
foI
8 9h
( addr e s s b i t s 1 6 -
6 DMA
67
( addre s s b i t s 1 6 - 1 9 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )
( addre s s b i t s 1 6 - 2 3 )
Page2 5 5 ( 64Ko )
D e te rm in e s of f s et
in t h e page
DMA
15
Externa l page
registe r ( 8 )
Pages
( 64Ko )
DMA BUFFER
16
. . . . . . . ..
P age3
Page reg i s t er
dete rmine s
merrory page
OMB
. ...
( 64Ko )
P age2
( 64Ko )
P agel
( 64Ko )
P ageO
( 64Ko )
DMA channel
e/16
0
1
2
3
bits
Defaul t uti l i ty
DRAM re f re s h
Not u s e d
F l oppy D i sk
Hard D i sk
8
8
8
8
PC-AT :
Default
uti l i ty
DMA
Channel
8/16
Bits
Not used
S ound cards
( l ow DMA )
F l oppy D i s k
Not u s e d
16
C a s c ad ing
16
S ound cards
( hi gh DMA )
16
Not u s e d
16
Not used
Sound
cards
Sound
cards
68
cards
( h igh
DMA )
network
cards
( high
DMA ) ,
network
Study the architecture and programming of the 18237 A circuit and its
use in PC.
b.
Write a program sequence that verifies the circuit registers (the ones
that can be verified).
d.
MOV AL,
OUT 08H,AL
OUT 8 7H I
"ii/
OUT 09H,AL
OUT OOH, AL
OUT OAH,AL
OUT OOH, A
MOV AL, 00
OUT OBH, AL
OUT OlH, AL
OUT OFH,AL
OUT OlH,A
OUT OAH, AL
OUT OlH, AL
MOV AL,
PUSH AX
OUT
18
41H, AL
OUT OlH, AL
MOV AL,
MOV AL,
OUT OBH, AL
SSH
;start channel
;of
18253
41H
OUT OBH, AL
MOV AL,
MOV AL,O
OUT OBH, AL
42H
MOV CH, AL
OUT 08H, AL
OUT OBH,AL
PUSH AX
e.
69
timer
BUS
ADDRESS B U S
HRQ
CPU
VIDEO
MEMORY
DRQO
DEMAND
LOGIC
DMAC
HLDA
I 8237A
INPUT
PORT
DATA BUS
Fig . 7 . 1
The block
di agram
71
of the
board
5V
5V
1 0k
DMA
D
CLK
12
11
7474
----5-<
i n it i a l i z a ti on
s w it ch
CLK
5V
1 0k
DACK O
DO
5V
1 0k
------""""-" O E
GND
8286
62
63
64
65
66
67
T
16
15
14
13
12
11
!-'--
D7
( I SA B US )
5V
----
HLDA
AEN
AD S T B
DBO - S B 7
_
AO - A 7
oA8-Al5
--------f
____________,
_________
/ DACK
a l i d Add
Va l i d Addr
/ IOR . /MEMW
Fig . 7 . 3 Timing for the DMA transfer
72
)----
74
; chara c t e r d i s p l ay func t i on
int 2 1 h
mov s i , o f f s e t key
ca l l wa i t
; t he addr .
of
dee ex
j z s t op
mov dx , o f f s e t me s s 2
j mp aga i n
s t op : ca l l de l e t e
etO
: mov ah ,
int
; checks
for p r e s s e d key
16h
j z etO
cmp a l , ' q '
jnz etO
; i f i t was not
'q' ,
'q'
redo t he l o op
ret
MAIN ENDP
PROGRAMM I NG PROC NEAR
mov a l , O fh
out
O dh , a l
mov a l , O O O O O l O Ob
d i s ab l e ,
cyc l e ,
; a c t ive on 1 ,
out
0 8h , al
mov a l , O O O O O l O Ob
! 8 2 3 7 dea c t ivat i on ,
f ixed
priorit ies ,
DRQ
DACK a c t ive on O
; Command Reg i s t e r
out O bh , a l
; mem . WR , b l oc k mode ,
; Mode Reg i s t e r
aut o in i t . addr
mov a l , O fh
; mask f o r channe l s 0 , 1 , 2 , 3
out o fh , a l
; Mask Reg i s t e r
mov a l , Obh
incr .
( f or a l l c hanne l s )
out 8 7 h , a l
mov a l , 2 0h
; t he l ow part of
mov dx , O Oh
the addr e s s
; t he B a s e Addre s s Reg i s t e r f o r C O
out dx , a l
; l ow p a r t o f t he B a s e Addr .
Reg .
for CO
mov a l , 8 3 h
out dx , a l
cal l
; h i gh p a r t of t h e B a s e Addr .
Reg .
for CO
s e l e c t i on
push ax
; s ave a x
int
; wa i t s for a key
1 6h
( b l ock l ength )
pop ax
mov dx , O l h
; the addr e s s of
out
dx , a l
the port a s s o c i a t e d w i t h
mov a l , ah
out
; high byt e of
dx , a l
mov a l , O
out
O fh , a l
mov a l , O
out
0 8h , al
; unma sk a l l channe l s
; a c t ivat e s DMA
ret
PROGRAMM I NG ENDP
75
mov ah , l
int 1 6 h
j z et l
; wa i t s unt i l a k e y i s pre s s e d
mov ah , O
; B IOS s e rvi ce ,
et2 :
pre s s e d k e y reading
int 1 6 h
; the pre s s e d key i s compa red to ENTER
; wa i t s f o r ENTER
cmp a l , [ s i ]
j nz e t 2
ret
WAI T END P
DELETE PROC NEAR
mov bh , l e h
; co l o r a t t r i b .
mov cx , O
; the l e f t - up c o rner
mov dh , 2 5
; l ine 2 5
mov d l , 8 0
; co l umn 8 0
mov a l , O
; c l e a r s c reen
mov ah , 6
; s crol l - up B I OS s e rv i c e
int
for s c reen ye l l ow on b l u e
l Oh
ret
DELETE ENDP
SELECT I ON PROC NEAR
mov dx o f f s e t
me s s 3
mov ah , 9
; DOS d i s p l ay f unc t i on
int 2 l h
mov ex , 1 0
mov s i , 4
e t 3 : mov ah , 1
jz et3
; wa i t i f t he bu f f e r i s empty
mov ah , O l h
mov b l , a l
; move al
and b l , O f Oh
cmp b l , 3 0h
; checks
j ne e t 3
; repeat s i f
i t has b e e n p re s s ed wrong
and a l , O f h
; the u s e f u l
i n f orma t i on is
and bx , ax
; bx f-the pre s s e d d ig i t s
to b l
i f t h e d i g i t has been pre s s e d
re t a ined
cmp s i , l
; the l a s t d i g i t
j e et4
mov ax , bx
; move
mov bx , ax
; ex ; / bx mu l t ip l i e d w i t h 1 0
in
ax
i s not mu l t ip l i e d w i t h 1 0
for
the
mu l t ip l i cat i on
w i th
i s done aga in
de e s i
cmp s i , O
et4 :
j ne e t 3
mov ax , bx
SELECT I ON ENDP
CODE ENDS
END MAIN
76
7.3 Exercise
a.
Analyze the
D MABLOCK.AS M .
b.
above
presented
charts
and
the
program
c.
Change the above program so that the transfer is started through the
program (software request).
d.
Write a program that does a OMA transfer i n byte mode according to
the electrical schematic in figure 7.2, using the video memory as
destination .
e.
Propose a progra m that does a 1 6-bit OMA transfer, using the same
practical assembly, in which a change has been made so that the transfer
will be made on channel 5 .
Remark:
77
8 . 1 Buses
in PC
Processor bus - represents the bus with the higher level, used by the
chip-set to exchange i nfo rmation with the processor
Cache bus - appears i n recent architectures (used i n Pentiu m Pro and
Pentiu m I I ), being dedicated to system cache memory access. It is
sometimes cal led "backside bus". Main boards from the 5-th generation
used by conventional processors have the cache memory connected to
the standard memory bus
Memory bus - is a level 2 bus, which con nects the system memory to
the chip-set and processor. I n some systems, the memory bus and the
processor bus are one and the same
Local 1/0 bus - is a high speed 1/0 bus used to con nect to the memory,
to the processor and to the chip-set system the peri pheral devices
whose performances are critical . Video cards, d isks or speed network
i nterfaces are using this type of buses. The most used 1/0 buses of this
type are : VLBus (Video Local Bus or VESA) and PCI (Peripheral
Component I ntercon nect) bus.
Standard 1/0 bus - is the oldest 1/0 bus used by slow peripheral
devices (mouse, modem, sound cards, slow network cards). This is the
I SA bus (Industry Standard Architecture) or AT bus.
lines, controlling the bus functions, sometimes named control bus and
sometimes not mentioned .
A bus is characterized by:
Bus width : refers usually to the data part. If the bus is large, more
information can circulate on it, having a better performance . The original
ISA bus had 8 bits and ISA-AT, 1 6 bits . The other 1/0 buses (including
VLB and PC I ) have 32 bits. Memory and processor buses, beginning
with Penti u m , have 64 bits. The width of the address bus is separately
specified and it refers to the number of d ifferent locations in which , or
from which , data can be transferred .
Speed : indicates the binary flux on each bus line. Most of the buses are
transmitting 1 bit data /line /cycle, but the new buses like AGP can
transmit 2 bits data /line /cycle, thus doubling the performances. The old
buses l i ke I SA can transfer only 1 bit /line i n two clock cycles, halving
the performances.
Band (debit) of the bus indicates the quantity of the data that can be
transferred theoretically by the bus in a g iven unit of time . Making the
comparison with a highway, if the width is given by the n umber of road
bands and the speed represents how fast the cars are drive n , the band
will be g iven by the multiplication of these two and represents the traffic
value which the channel allows in 1 second . The next table indicates
the theoretical bands of the most used 1/0 buses, but practically these
val ues cannot be achieved from d ifferent reasons. For example, in the
case of ISA bus, the band should be of almost 8 M bytes/s, but in reality,
there are wait states introd uced on the 1/0 cycles, which are red ucing
th is value.
BUS
I SA- 8 ( XT )
I SA - 1 6 ( AT )
E I SA
VLB
PCI
PCI 2 . 1 - 6 4 b i t s
AGP
WIDTH
(BITS )
SPEED
( Mb / S )
BAND
( MB / S )
8
16
32
32
32
64
32
8.3
8.3
8.3
33
33
66
66
7.9
15 . 9
31 . 8
127 . 2
127 . 2
508 . 6
2 54 . 3
80
Cache
Memory
Sys t em
Memory
Video
Adap t e
( DRAM )
PCI S l o t s
I / O PCI BUS
EIDE
Con t ro l l er
I SA/ E I SA S l o t s
I SA/ E I SA
BUS
Fig . 8 . 1 Buses in PC
I n a system that has more buses, the connections g iven by the chip-set
must allow the connection of the devices to the buses and the transfer
between devices con nected to different buses. The device that allows
passi ng from one bus to another is named "bridge" . The best known is the
PCl-ISA Bridge, which is part of the system chip-set at Penti u m and
Penti umPro PC. PCI bus has also a bridge to the processor bus, which can
be fou nd i n Windows 95 at "Device Manager" >"System devices" .
Signals type is seen from the main PC board . A board connected to the bus
cannot get the control of the bus; this means that it cannot generate cycles
fo r reading and writing on its own , so it cannot be a master device . A slave
device can i nitiate a transfer cycle indirectly, by sending a OMA request to
the D MAC ( 1 8237A), but this one wil l manipulate the control signals. Bus
signals are TTL compatible.
SIGNAL
CONNECTOR
PIN
DESCRIPTION
TYPE
s igni f i cant
20
of
bits
Less
the
addre s s bus wh i c h d i r e c t t h e f i rs t
Mbyte o f memory and are va l i d on the
f a l l ing edge o f the s i gna l .
the
s igna l
DMAC
When
is
act ive ,
cont rol s the bus . The I / O addr e s s
decoders are u s i ng thi s s igna l t o
ignore the DMA t rans f e r cyc l e s .
Indi c a t e s that the addre s s s igna l s
are val i d and ready t o be decoded .
ALE i s forced t o " l " dur ing the DMA
cyc l e s .
sys t em
c l ock
MH z
The
with
8 . 33
f requency and 1 / 2
f i l l ing
factor .
syst ems
Some
can
have
d i f f e rent
f requency .
A1 9 -AO
{ addre s s )
A1 2 - A2 1
OUT
AEN
{ addre s s
enab l e )
Al l
OUT
ALE
{ addre s s
l at c h
enab l e )
B2 8
OUT
CLK
{ c l ock )
B2 0
OUT
A2 - A 9
I/O
OUT
D9 , B6 , B1 6
Bl8 ;
Dl l , D1 3 , D
15
IN
reque s t s
DMA
s ent
to
the
DMA
cont rol l e r a s k a channe l f o r da t a
t rans f e r . Channe l s 0 - 3 are for 8 - b i t
5-7
t ran s f e r s
channe l s
for
1 6 -bit
t rans f e r s . DRQ i s igna l mu s t b e kept
act ive unt i l DACKi become s a c t ive , or
e l s e the DMA reque s t i s i gnored .
Al
IN
D7 - D O
{ dat a )
DACK0-3
DACK 5-7
{ DMAack )
DRQ 0 - 3
DRQ 5 - 7
{ DMA
reque s t )
I / O CHCK{ I/O
channe l
che ck )
D8 , B1 5 , Bl
7'
B2 6 ;
D1 0 , D12 , D
14
82
I / OCH RDY
( I /O
channe l
ready )
Al O
IN
D2
IN
Bl4
OUT
Bl3
OUT
I O CS 1 6 -
I / O 16 b i t
hip
elect )
!OR( I/O
read )
! OW ( I/O
wri t e )
I RQ 9 ,
I RQ3 - 7 ,
RQ 1 0 - 1 2 ,
IRQ 1 4 - 1 5
LA2 3 LA1 7
( l a t c hab l e
addre s s )
(No wa i t
state s )
osc
(Oscilla
tor )
REFRESH RESET DRV
( Re s e t
4 , B2 1 - B 2 5 ,
D3 - D 7
IN
wan t s
un i t
un i t
un i t
un i t
to
The s e
s i gna l s
don ' t
pass
through
l a t ches and are va l i d when ALE pa s s e s
t o 1 . Us ing t hem t ogether w i th the
other addre s s l i n e s , one c an addre s s
16
Mbyt e s .
The s e
s i gna l s
c an
be
memori zed in l a t ches on ALE f a l l ing
edge .
The s ignal i s u s e d t oge ther with DRQ
for taking cont rol ove r the sys t em .
C2 - C 8
OUT
Dl7
IN
Dl
IN
C9
OUT
a c t ive
Is
cyc l e s .
in
all
memory
reading
ClO
OUT
act ive
Is
cyc l e s .
in
all
memory
wr i t i ng
BS
IN
B3 0
OUT
Bl9
OUT
B2
OUT
ext e rn a l
I nd i c a t e s
that
the
permi t s memory a c c e s s cyc l e s
b i t s w i t h a wa i t s t a t e .
board
on 1 6
MH z
83
Cl
OUT
SD8 - SD 1 5
( Sy s t em
dat a )
Cl l - Cl 8
I /O
Bl2
OUT
Bll
OUT
TC -
B2 7
OUT
+ SV=
B3 , B2 9 , Dl
6
- 5V=
BS
B9
SMEMR ( s y s t em
mem . read )
SMEMW ( Sys t em
em . wr i t e )
+ 1 2V=
- 1 2V=
GND
B7
Bl , B3 1 , Dl 8
i t ind i c a t e s dat a
When i s a c t ive ,
t rans f e r on SDB - 1 5 and i f the addre s s
i s even , the t rans f e r i s made on 1 6
b i t s ; when the addre s s i s odd - on 8
bits .
Are the mos t s i gni f i c ant 8 b i t s o f
the da t a bus . On ly the dev i c e s that
a l l ow 1 6 - b i t t ran s f e r s u s e them .
I s act ive at the memo ry reading w i t h
f i rs t
p l aced
addre s s
in
the
the
memory Mbyt e .
I t i s act ive at the memory wr i t ing
with the addre s s p l aced i n the f i r s t
memory Mbyt e .
An impu l s e on t h i s p i n ind i c a t e s the
ending of t rans f e r s on one of the DMA
con t ro l l e r channe l s . The chann e l i s
by
t e s t i ng
the
DACK
de t e rmined
s igna l s .
In range 4 . 7 5V - 5 . 2 5 v a t a current
< 1 9 . 8A
In range - 5 . SV - - 4 . 5 v at a current
< 0 . 3A
In range l l . 4 V - 1 2 . 6 V at a current <
7 . 3A
In range - 1 3 . 2V - - 1 0 . 8 V at a current
< 0 . 3A
Table 8 . 2 The
I SA
bus signal s
Addresses AO-A9
I O R or/and I OW
AE N
I n the case of the programmable interfaces, a part of the add ress lines
(AO . . . ) from the bus are connected directly on the correspond ing pins of the
interface, to address the available ports of the circuit and I O R , I OW signals.
U nconnected addresses and the signal AEN wil l be inputs fo r the decoding
circuit whose output wil l command the CS signal of the i nterface .
Decoding circuits can be designed using:
Logical gates
E/PROM memories
AEN= O
ALE
ADDR .
___)--)
l O On s
/ I OW or / I OR
DATA ( / I OR )
DATA ( / I
>
_o
_w
_
\__
\
> 5 5 0n s
-------/
: < l l O n s ...
__
_
_
VAL I D DATA
VAL I D DATA
\._
_
_
_
_
\_
the memory are: address lines AO-A1 0, signal AEN to /CE and I OW to /OE .
The data is loaded to the ports o n the negative edge g iven by the data bits
DO or 0 1 con nected to the G inputs of the register (on level " 1 " the outputs
follow the inputs), when one of the memory locations with address 30Eh or
30Fh was addressed . The locations' content is 01 h (00= 1 ), respectively
02h ( 0 1 = 1 ).
8.5 Exercise
a. Analyze the electrical schematic from figure 8.3, the role of the signals
from the bus and compute the maximum amplitude (V-V) that can be
generated using the circuit.
b. Analyze and execute the program S I N U S . C and determine the
frequency l i mit of the signal that can be generated using this program.
Analyze the dependence of the frequency limit on the resol ution used i n
generating the signal (number of samples/period) .
86
Rectangular
Triangle
Random
Saw-tooth .
8 - bit
Digital
Ana l og
Converter
R6
+1 2V
2 ---.,._,
1 2,....,
11
5
10
6
9
9
,_..,
--__,,....,
12
8
1-7.;----;
1 5,__
7
1-7.
_--:-;
6
16
,_.,.,----:-1
19
5
1-'-'-
-;
4k
C3
- 1 2V
BpF
OAC08
B81 J O U T
87
BS
t-4----.....,
85 I OUT. D"----
B4
83
82 COMP I-'-''--
81
+ 1 2V
+ 1 2V
g g t-+--6-;
'-++-!-+-+-+---:-l
2
02
'-+--+-<-+--'-""' 0 3
'-++-f---i7-l 04
05
'-+----.;-;;,;
12
8 -bit Digital
Analog
A
Conve r t e r
02
9
9
03 >-=-____,_,
8
12
04 l--7i;----;
15
7
05
6
16
----.;,;
i-;;
5
1 9.--
gr g
----,-,u OC
G
4K7
R8
813
21<2
Vee
2816
87
/ / func t i on p o i n t e r
/ / s inus gene rator interrupt prototype
vo i d t ab l e_s i n ( vo i d )
int i ;
f o r ( i = O ; i < s t eps ; i + + )
t ab l e [ i ) = l 2 B * ( l + s in ( 2 * 3 . 1 4 1 5 9 / s t ep s * i ) ) ;
/ / end s inus values t ab l e
vo i d ma in ( vo i d )
f l oat v ;
uns igned int vv ;
char i = ' d ' ;
clrscr ( ) ;
v_int =getve c t ( B ) ;
( I RQ O )
s e tve c t ( B , Gen_s i n ) ; / / put the new i n t e r rup t
wh i l e
mov dx , Ox3 0 e
mov ax , vv
out dx , a l
88
etl :
a s rn {
mov
mov
mov
out
inc
rnov
dee
crnp
j le
mov
dx , Ox3 0 f
bx , t
a l , t ab l e [bx)
dx , a l
bx
dx , s t ep s
dx
bx , dx
etl
bx , O
/ / port f o r s amp l e s
/ / t - t ime
/ / t ake s amp l e f rom t ab l e
/ / out t o port
//t=t+l
/ / l oad numb e r o f s t e p s f o r
/ / t ab l e end
t e s t ing
II
/ / t ime r e s e t
a s rn
mov t , bx
mov dx , O x2 0
rnov a l , Ox2 0
out dx , a l
vo i d prg_t ime
/ / redo t ime i n C
/ / i n t e r rupt d i s charge
EOI ( ou t 2 0H , 2 0 H )
II
(f)
int a , a l , a2 ;
a = ( l l 9 3 1 . 8 / s t ep s / f ) * l 0 0 ;
al=a%2 56 ;
a 2 = a/ 2 5 6 ;
_BL = a l ;
_BH= a 2 ;
asm
mov ax , Ox3 6
mov dx , Ox4 3
/ / l ow byt e
/ / high byt e
high
; / / oc t e t ; O l l - re c t angu l ar s i gna l ;
/ / 0 - b inary ; T imer - po r t 4 3 h
out dx , a l
mov
mov
out
mov
out
dx , Ox4 0
ax , bx
dx , a l
a l , ah
dx , a l
/ / Low
/ / H igh
89
vo id res t ime ( vo i d )
asm
mov ax , Ox3 6
mov dx , Ox4 3
out dx , a l
mov
mov
out
out
dx ,
ax ,
dx ,
dx ,
Ox4 0
OxO O
al
al
/ / Low
/ / H i gh
/ / end r e s t ime
90
91
The correspondence between the signals and the pins (from both
kinds of con nectors) and the bits of the registers, as well as their
significance in the standard mode (SPP) are described in table 9 . 1 .
T_- !J?t,Jal be1_$_i!_cl.dresses of the parallel ports i n the PCs a re:
3bch - address used by the M DA adapters and the pri nter
378h - the pri nter interface address
278h - the printer interface address
DB 2 5
Pin
Centronics
Pin
SPP Pin
Signi ficance
Regis ter
bit
In/Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18-25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
31
36
1 9 - 3 0 , 33 , 17 , 16
- S t robe
Dat a O
Dat a l
Data2
Dat a3
Data4
Dat a5
Dat a 6
Da t a 7
- Ack
Busy
PaperFeed
S e l e c t Ou t
-Aut o f e e d
- Error
- Init
- Se l in
GND
co -
SS
S4
Cl S3
C2
C3 -
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
Out
In
Out
Out
DO
Dl
D2
D3
D4
DS
D6
D7
S6
S7 -
for LPT1 , LPT2 and LPT3 printers respectively. The address of the fourth
device LPT4 is not a standard one. Thus, using the B I O S table described
above, one can reassign the addresses of the standard LPT logical
devices. The signals presented in table 9. 1 are assigned to the bits in the
registers (ports) that make up the hard/soft interface of the parallel port.
Their configuration will be presented shortly.
Data register (Base Address)
D7
D6
D4
DS
D3
D2
Dl
DO
S6
S4
SS
S3
- Error
S2 I Sl I S O
From this register the _peri pheral status signI a re read. For the Standard
Parallel Port, these signals have the following significance :
C4
C2
C3
93
Cl
- Init I - Autofeed
co
- Strobe
Irq 7
----1
IrqEn
'-----11<'--- -Ack
DE--- -Error
,..___
_
SeIOut
--
B A SE
A D D R+ l
PaperTud
,-- Busy
S7 =Busy
S6 = A c k
System
BUS
S5 = P ap e r E n d
S4 =Se l 0 ut
S3 = E r r o r
B A SE
A D D R+2
C O = - St r o be
C l = - A ut o feec
C2 = l n i t
C3 =-Selin
-Strobe
o--- -Auto
-Init
o--- -Selin
IrqEn*
C 4 = l rqEn
CS=Dir*
DIR
B A SE A D D R
1----
D 7 =D at a 7
D 6 = D at a6
D 5 =D a t a 5
Data7
Data6
1----4 Data5
1----4 Data4
--
,___
Data3
D 3 =D a t a 3
1----4 Data2
D 2=Data2
DataO
D 4 = D at a 4
Datal
D l = D at a l
D O = D at a O
D i r selects the d i rection of the data signals: "O " = output, " 1 " = input (only for
bidirectional ports - PS2)
l rqEn validates the apparition of the hardware interrupt on I RQ7, on the rising
edge of the Ack signal (" 1 " = validate l rq7; "O" = invalidate l rq7).
-Se l i n - if set to " 1 " it allows to activate/deactivate the printer by using
DC 1 /DC3 codes
-l n it - through a "O" impulse longer than 50 s, the printer is initialized
-Autofeed - if set to " 1 " , the printer moves to a new line after receiving a CR
-Strobe - through a " 1 " impulse at least 1 s long , the printer is announced that
there is a new valid data on the data l i nes.
94
PC to the printer is
DO-D7 [[X
I
Bl.SY
-S'IROBE
-ACK
i
i
3
I
VA L i
control register is
DAT A
I
I
i
i
Mode3 uses for the i nput 4 bits from the .GQD.trol port and 4 .btts. otthe. state.
port, thus enabling bidirectional 8-bit .kcir.ifrs on any PP. I n this case, the
control outputs must be set to i'1'; ( C O=C 1 =C3=0 an d C2= 1 ) , because, as
they are open-collector outputs, they can be commanded to "O" by an
external device without destructive effects. The reaction register of the
control port, keeping in mind the fact that bits CO, C 1 and C3 have been
reversed , can read these outputs.
95
B7
B6
-Busy Ack
B5
B4
PEnd Online
B3
Error
B2
Bl
BO
Timeout
Beg i n n i n g with the address 0 :478h, on the next three bytes there a re
stored the Time-Out counters for the parallel interfaces that keep track of
the fai led transmission attempts.
Function 01 h
PC.
testi ng the status of the pri nter. The PC reads the status of
the printer.
Inputs: AH = 02; DX = the number of the printer
Outputs: AH = the status of the printer
Remarks: same as for function Oh .
96
The ' N i bble' 4-bit transfer mode, which uses the status lines as a
reverse communication channel
9.6 Application
The suggested application presents how to command of a LCD using
the parallel port of the PC. The connection schematic is presented in
fig . 9 . 3 . To command the LCD data lines the parallel port data register was
used (DO-D7) , the R/W line is connected to the ground because only write
operations are done, RS is con nected to Selectin ( 1 7 ) and Enable From
LCD to Strobe (1 ). The supply source is of 9V, its voltage being stabilized at
+5V using a LM7805 circuit. The LCD contrast is adjusted through a 5Kn
potentiometer con nected to V0 (3).
97
U1
1
9V
De
VIN
P1
-c;'
0
"'
0
-
DO
DI
Dl
-ilHUlD.
D3
D4
0
0
C3
1 00n
"'
,.4EL
1
- 2
- 3
4
- 5
- 6
I
I
no
21
9
72
0-
'
10
l___<;
"'
1
1
T
C2
5k
1 -Strobe
14
15
J
16
4
17
5
18
6
19
7
20
R1
"
47uF
0
z
C1
VOUT
II
8
9
10
- 11
12
13
14
D7
LCD
24
*4< GND
The program lcd 1 6.asm that commands the LCD displays the text
"*Test Message! *".
- -
; ---------
---
- -
- -
---------------
98
----
- - - - -
-------
MAI N
;
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
c l rscr
c l rs c r
'
; c l e a r s c reen procedure
; co l or a t t r ibute
; ( wh i t e l e t t e r s , b l ack background )
cx , O O O O h
dx , 0 1 8 4 fh
l Oh
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wr i t e
p roc near
mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
c a l l de l ay
mov dx , [ PORT l ]
mov ax , B O h
99
etl :
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l a y
mov s i , O
mov dx , [ PORT l ]
mov ax , p r im [ s i ]
out dx , ax
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l ay
add s i , 2
,...., ....... ,......
'- " '.t-'
et2 :
Cl ..;
-- ,
; w i l l be read
; da t a reg i s t e r is s e l e c t e d
; wr i t e , o n e b y one ,
; t he chara c t e r s f rom
; t he f i r s t s t r ing of l eng th B
; s e t STROBE act iva t e d
, c.
- '-'
j ne e t l
mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
c a l l de l ay
mov dx , [ PORT l ]
mov ax , O C O h
o u t dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , l
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , O
out dx , ax
c a l l de l ay
mov s i , O
mov dx , [ PORT l ]
mov ax , s e c [ s i ]
out dx , ax
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
mov dx , [ PORT2 ]
; s e t da t a regi s t e r
; wr i t e t h e next 8 chara c t e r s
; o f t h e s t r ing
1 00
wr i t e
; ----------------- -------------- ------------- --d i sp l
p roc near
; t ext l d i s p l ay procedure
pus ha
mov
ah , 0 2 h
mov
bh , O Oh
mov
dh , 1
mov
dl , 1
int
l Oh
mov
ah , 0 9 h
lea
dx , t ext l
int
2 1h
pop a
RET
displ
endp
-
; - -
- - -
in i t
- -
- - - - - - - - - - - - - - - - - -
proc near
!!1 0 V
et :
s i , fJ
- - - - -
- -
- - -
- - -
- - - - - -
- -
- - - - - - - - - - - -
si , 2
add
c a l l de l ay
mov dx , [ PORT2 ]
mov ax , 1
out dx , ax
c a l l de l ay
cmp s i , 6
j ne e t
RET
endp
; d i s p l ay in i t i a l i z a t i on procedure
mov dx , [ PORT2 ]
mov ax , 2 5 4
out dx , ax
'
c a l l de l a y
mov dx , [ PORT l )
mov ax , va l [ s i )
out dx , ax
ini t
,
- - - De l ay Proc Near
mov dx , O
mov bx , 1
mov a l , 1
xor ah , ah
int
l aH
add bx , dx
- -
- - -
- -
- -
- - - - - -
- - -
- -
- - -
- -
1 01
'
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
code
ENDS
END
MAI N
9. 7 Exercise
a . Analyze and execute the appl ication lcd 1 6.asm. To u nderstand the
progra m , the appendix about the 1 6-character LCD is recommended .
b . Modify the appl ication to display characters introd uced from the PC
keyboard .
c. Develop a n application that rotates a text, introduced from the PC
keyboa rd , on the LCD .
d . Rewrite the applications in C language.
1 02
two ( E P P , ECP) are evolved modes for high speed bid irectional
communications between a PC and an external peri pheral of 50 .. 1 00 times
faster than the standard parallel port. EPP and ECP modes keep the
compatibility with the existing peripherals that are using the old
comunications modes.
EPP and ECP modes are implemented in the newest 1/0 controllers
by most of the peripheral chips producers. These chi ps generate the
protocol signals needed for the data transfer between the PC and the
periphera l . For instance, in EPP mode, a byte can be transferred to the
peripheral using a simple OUT instruction. Also it is to be noticed for this
mode the possibility to address more peripherals by a separate address
transfer cyle. In ECP mode, the hardware is more evolved . In this mode the
presence of a F I FO memory makes O MA transfer efficient, also it allows to
send commands to all the peripherals using a special transfer cycle. The
1 284/94 standard , beside the 5 operating modes, uses a negotiation
method for the data transfer between the peripheral and the PC, defining
the physical interface (cables, connectors) and the electrical interface
(drivers , terminals, i mpedances).
The parallel port based upon the 1 284 standard represents a high
performance i nterface, easy to use for a great variety of peri pherals, from
pri nters to mobile peripherals, scanners, HDDs, etc.
EPP mode is more often used than ECP. The difference between
EPP and ECP is that E P P gene.r_ptJ_nc:j_ C()l"ltroles all transfrn.to and_from
the peripheral, while EC P negoci a tes with the periphera l a reverse_channel
and the handshake c;ontrQI, things harder to achieve with an usual logic, so
a de d i cate cf contro ller or an ECP peripheral chip is necessary.
EPP protocol defi nes A_types of transfer cycles:
1 -2 : Data Read I Write cycles
3-4 : Add resses Read I Write cycles
In EPP mode, the pins and the signals have different names than in the
standard mode (see tab. 1 0 . 1 )
Pin
In/Out
- S t robe
- Wr i t e
Out
2-9
DO -D7
AD 0 - AD 7
10
-Ack
- In t r
In/
Out
In
11
Busy
- Wa i t
In
Function
" Low11 i nd i c a t e s wr i t ing and
" hi gh"
indi c a t e s reading
Addre s s / Da t a b i d i rec t i onal
bus
The p e r iphe r a l gene r a t e s
inte rrup t i on when s e t s the
l ine to " 0 "
" Low" ind i c a t e s the
pos s i b i l i ty of s t a rt ing a
cyc l e ,
12
P ap e r End
13
Select
out
- Auto
Linefeed
- Error
14
15
16
17
1825
- !nit
- Select
in
Ground
User
Def ined
User
Def ined
-Data
S t robe
User
D e f ined
- Re s e t
- Addre s s
S t robe
Ground
In
In
Out
In
Out
Out
'' h i g h "
Lht: elid uf
cyc l e
C a n b e de f ined by every
p e r iphe ral
Can be de f ined by every
p e r iphe r a l
" l ow" i nd i c a t e s that a dat a
t rans f e r i s in progre s s
Can be de f ined by every
p e r iphe r a l
" l ow" r e s e t s t h e p e r iphe ral
" l ow11 ind i c a t e s a n adre s s
t rans f e r in p rogre s s
GND
Paper End , Selectout and Error are not defined in EPP mode, these
lines b eing used in different ways, depending on the peri phera l . These
lines' status can be determined from the standard parallel port registers.
1 04
E P P port registers
EPP port is, compared to SPP, a new set of ports (registers), th ree of
them being inherited from SPP mode. The next table presents these
registers .
Address
Data Port
Wr i t e
( SPP/EPP )
S t atus Port
Bas eAddr+ l
Read
( SPP/EPP )
Con t r o l Port
Write
B a s eAddr + 2
( SPP/EPP )
Bas eAddr+ O
B a s eAddr+ 3
B a s eAddr + 4
Bas eAddr + 5
Bas eAddr + 6
E e. s e_ddr -!- ?
Read/
Write
-
Description
S t andard dat a port
S t andard s t atus port
S t andard command p o r t
The port wr i t ing/ reading genera t e s
an
EPP
cyc l e
to
wr i t e / read
an
a ctd:t:e5s
The port wr i t i ng / reading gene r a t e s
a n EPP cyc l e t o wr i t e / read a dat a
I n s ome EPP imp l ement a t i on s i s u s e d
for 1 6 / 3 2 - b i t t rans f e r s
In s ome EPP imp l emen t a t i ons i s used
for 3 2 - b i t t rans f e r s
In s ome EPP imp l ement a t i on s i s used
for 3 2 - b i t t rans f e r s
It is to be noticed that the first registers are the same as for the
standard mode, keeping the compati bility with the SPP mode.
If data communication to EPP compatible devices is needed , all that is to
be done is to send the data to be transmitted into the E P P data register, at
base address+4, and the EPP port hardware wil l generate all the needed
handshake signals. The same operations are to be done when address
transmission is needed , using the EPP port; the d ifference being in the use
of the E P P address register at base address+3. Both data and address
registers, in E P P mode, are read/write, so to read/write data from/ to the
device , the same registers can be used . The registers from base address +
5 . 7_ can be used for 1 6/32-bit
- data transfers, if the port accepts this. The
parallel port can tran Sfe r on ly- i:r bits at a time, so that any 1 6/32-bit word
sent to the parallel port is i ntercepted by the ISA controller that will
generate 2 or 4 8-bit rapid cycles without the user i ntervention .
.
1.
2.
3.
4.
/Write
/Data
S t robe
/Wait
Data
\
I
x
/Write
/Data
S t robe
\_
/Wait
x==
Da ta
\__
Pin
SPP
ECP
{Ju")/,..
- S t robe
2-9
D O - D7
IN/OUT
: ""
Ho s t C l k
Da t a ( 8 : 1 ]
Out
I n / Out
10
- Ack
P e r iphCl k
In
11
Busy
P e r i phAck
In
- AckRev e r s e
In
1 2 Paper End
13
Select
XF l ag
In
14
- Aut oFeed
Hos tAck
Out
15
- E rror
- Pe r iph
Reque s t
In
16
- In i t
- Reve r s e
Reque s t
Out
Function
I f i t i s '' l ow" ,
there are va l i c
data
on
port .
When
it
is
deact ivat e d ,
a s c ending
the
edge
wi l l be u s e d t o t ran s f e r da t a t c
t h e p e r iphe ral
B i d i re c t i onal dat a bus
Used t ogether w i t h Hos tAck for the
reve r s e data t r an s f e r
Used together w i t h Hos t C l k for the
direct dat a I addre s s t rans f e r
When i t i s " l ow" , the p e r iphe r a l
acknowl edge s - Rever s eReque s t .
Ext ens ib i l i ty f l ag
Gives s t atus i n f o rma t i on f o r d i re c t
dat a / commands
When i t i s " l ow" i nd i c a t e s that a
reve r s e da t a t rans f e r i s p o s s ib l e
When i t i s " l ow" indi c a t e s that the
data tran s f e r i s made in reve r s e
way
1 07
17
18-
25
- S e l e c t in
Ground
1284
Ac t ive
Ground
Out
GND
Ground s ignal
port
1284
..
ECP registers
In the table below the ECP port registers are presented . The fi rst
three of them a re the same as for the standard para l lel p o rt A speci a l
attention must be accorded to the bid i rectional port activation bit (bit 5 from
the control port) . This bit shows the d i rection of data through the ECP port
and affects the bit that shows if the F I FO stack is fu l l or empty, bit from the
ECR register.
.
OFFSET
0
Port Name
D a t a Port
S t a t u s Port
Con t r o l Port
400
401
402
Read/Wr i t e
( ECP mode 0 0 0 0 0 1 )
F I FO Addre s s - ECP
F I FO
F I FO ;
Read/Write
( ECP mode 0 1 1 )
Read/Wr i t e
(Al l Mode s )
Read/Wr i t e
( Al l Mode s )
Data
( Para l l e l
ECP mode 0 1 0 )
Read/Wr i t e
Port
data
Read/Wr i t e
( ECP t e s t mode 1 1 0 )
Read/Wr i t e
Read/Wr i t e
-
Read
Read/Wr i t e
Read/Wr i t e
Bit
Function
7:5
S t andard Mode
001
Byte Mode
010
Fa s t Centron i c s Mode
Oll
ECP Mode
100
E P P Mode
101
Re s e rved
llO
Te s t Mode
lll
ECP Interrupt B i t
DMA Enab l e B i t
ECP S e rv i c e B i t
F I FO Fu l l
F I FO Empty
-1 0
oo
Operating Modes
Standard Mode
SPP
Byte Mode/
PS/2 Mode
__ _
Parallel Port
FIFO Mode ( Fast
Centronics Mode )
1 09
Configuration
Mode
reg i s t e r s
be addressed at base address + 400 and the b its have the sign ificance
presented i n table 1 0.7.
The configuration register A gives extnqg. i nformation about the
ECP port. The most signifi cant bit shows if the interru pts are generated on
leyel pr on edge. It depends on the l?C_ Lnternal bus type. B its 4 and 6 show
the width of the bus used by the ECP controller. Some controllers have only
8-bi t bus, other 1 6 or 32-bit bus. To be able to use at maxim u m the bus
width , the progra m can read the status of these bits to determine the
maxi mum size of the word for communicating with the controller.
The Ta st th ree bits (less sign ificant bits) are used for transrri[s!<:>.r1_L()\lry.
To recover data i n case of error, the program must know exactly how many
bytes were transmitted , determining if there are bytes left i n F I FO . Some
implementations can include bytes into the transmitter registers , that wait to
be transmitted as a part of F I FO (Full Status), other implementations do not
allow th is. bit 2 determines if the i mplementation allows it or not.
Bit
7
6:4
Function
1
0
O Oh
O lh
02h
Ac c ep t s maximum 3 2 - b i t words
03h : 07h
Re s e rved
Re s e rved
1:0
01
10
11
Who l e word
One byt e f rom the word transmi t t ed on the port l e f t
in F I FO
Two byt e s f rom the word t ransm i t t e d o n the port l e f t
i n F I FO
Three byt e s f rom the word t ransmi t t ed on the port
l e f t i n F I FO
Bit
7
6
5:3
2:0
Function
1
I n t e rrup t s s t atus
ind i c a t e s I RQ p i n s t atus
001
IRQ 7
010
I RQ 9
Oll
IRQ 1 0
100
I RQ l l
101
I RQ 1 4
llO
I RQ 1 5
lll
I RQ 5
S e l e c t s or i nd i c a t e s t h e s t atus o f t h e u s e d D MA c hanne l
000
Jumper s e l e c t ed 8 - b i t DMA channe l
001
Channel 1 DMA
010
Channe l 2 DMA
Oll
Channe l 3 DMA
100
Jumper s e l ec t e d 1 6 - b i t D MA channe l
101
Channe l 5 DMA
llO
Chann e l 6 DMA
lll
Chann e l 7 DMA
1 12
BiL6 returns the status of the interrupt line. It can be used to diag nose
confl icts, because it does not reflect the interru pts from the parallel port and
from the other devices that use I RQ .
Bits 5 a n d 3 show the status of the interrupts generated b y the port, and
bits 2 . . 0 show the status of the OMA channels. This field can be
read/written .
E C P mode comm u n i cati o n
The communication with the peripherals in ECP mode is d ifferent from the
communication in SPP mode. The most significant d ifference is that in ECP
mode data can be transmitted in both ways anytime, using add itional
control signals. Below, the ECP d ialog modes (handshake) for both
communication ways (di rect and reverse) are presented .
D i rect data tra nsfer
by
val idating
HostA ck= 1
5. ECP port puts HostC!k on "high"; on the rising edge data is written to
the peripheral
6 . T h e peri pheral signals the data receiving b y deactivating PeriphA ck=O
/ Host
Clk
/ P eriph
Ac k
Ac k
Data
/ Rever s e "'\
Reques t
\. _____..J.
/Ac k
Rev erse
/ P e riph
Clk
/ Ho s t
Ack
/ Pe riph
Ack
Dat a
The RLE protocol incl udes a simple compression algorithm , Run Length
Algorithm. The compression is obtained by counting the identical bytes and
send ing them to destination as follows: fi rst, a byte that represents the RLE
counter is sent, then a byte that represents the repeati ng value is sent. This
algorithm al lows a maxi mum compression rate of 64 : 1 . For example if a
nu mber of 40 "C" characters wi ll be sent, a byte containing the va lue "40"
and a byte conta i n i n g the character "C" wil l allow the peripheral to recover
the i nformation . If i n the data string, we have two bytes of d ifferent values
(characters), a byte containing the value "O" will be the transmitted cou nter,
followed by the va lue of the first byte, then the two bytes for the second
character will be also transmitted .
The i nformation bytes compressed with RLE must be d istingu ished from
the other bytes sent on the data l i nes. I n order to achieve this, a command
to the F I FO port of ECP is sent. The bytes sent to this reg ister can be
address bytes or bytes compressed with RLE . The d ifference is made due
to bit 7 ( M S B ) . If it is 1, the other 7 bits ( 0 . . . 6 ) represent a channel address ;
if it is 0 , the other 7 bits represent the RLE counter. Using MSB for this
purpose, the n u mber of channels is l i mited to 1 2 7 .
1 14
//******************************************************************
//******************************************************************
Main program
int ma in ( vo i d )
//
; /I
II
a o cvv;
for ( a= O ; a< 3 ; a+ + )
port = * p t raddr ;
i f ( port = = O )
II
II
II
else
i n i t i a l i z e port addre s s e s
//
//
/I
/I
i f ( re s u l t = = Ox7 5 )
el se
{ p r i nt f ( " The
II
;}
outportb (port + 4 , va l ) ;
wr i t e EPP da t a reg i s t e r
i f t h e S P P dat a reg i s t e r content i s di f f e rent
//
1 15
II
II
};
*pt raddr + + ;
};
ge t ch ( ) ;
1 0.5 Exercise
Write a n appl ication that determi nes the F I FO stack
port.
1 16
size of
the
ECP
1 1 . O N TH E M E M O RY I N PC SYST E M S
0
OFFSET
15
0
S EGMENT REG I STER
19
PHYS I CAL ADDRESS
The two logical addresses are the content of a segment register and of an
offset from another i nternal register or a result from the addressing modes.
To obtain the p hysical address , 1 6 mu lti ply the segment reg isters content,
the empty positions are padded with "O" , and then the offset is added ,
obtaining a 20-bit address .
The memory space that can be directly addressed by the 8086 processor is
of 1 Mbyte , with addresses between OOOOOH and FFFFFH . The addressing
can be done at byte level and at word level (two successive bytes) without
restrictions for the start addresses of the word operands.
Physically, the memory can be divided i nto two blocks of maxim u m 5 1 2
Kbytes: the even block and the odd block. The even block contains only
even address locations and the odd block, only odd address locations. The
even block is con nected to the inferior half of the data bus, 07-00, and the
odd one to the superior half of the data bus, 0 1 5-08 . The address l ines
A 1 9-A 1 are used to select a memory location simultaneously from both
blocks . The transfer between the selected locations and the data bus is
done only under the control of two more l i nes, AO and /B H E , l i ke in the
table below:
/ BHE
AO
0
0
1
1
0
1
0
1
Tran s f e r
Word
Odd byt e
Even byt e
-
Even
O dd
/ BH E
cs
AO
( HI GH )
cs
( lOW)
D O - D7
D 8 - Dl 5
D O - Dl S
118
8 0 8 6 MIN
A l 6 - Al 9
..
AD O - AD 1 5
....
..
AL E
..
,
/ BHE ..
,
/.QD ..
,
/WR ..
,
M I / O ..
,
DT / R ..
DEN ,..
,
Memory
sys t em
From fig . 1 1 .3 can be seen that beside the multiplexed address and data
lines ADO-AD 1 5 and the high address l ines A 1 6-A1 9 there is the su perior
block val idation signal, /BH E . It must be noticed that in this mode, the
microprocessor generates the memory control signals ALE, /RD , /WR,
M/1 0 , DT/R and D E N . If the microprocessor is con nected i n maxi mum
mode, the specialized circuit 18288- bus controller generates the memory
control signals.
The memory system consists of two blocks: the memory itself and the
address decode r that selects the memory. I n fig . 1 1 .4 , a practical modality
of con necting a memory in an 8086 system is presented .
Addre s s bu s
<RESERUED>
IJPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPAAAAA P UWvV.AA!RR-------RRRR
0K
Su.....ru Uiew
0
0 O:nO
004011 to B4F4h
84F4h to 9Ell0h
9E80h to A000h
A099h to C000h
C088h to Cll00h
ceeeh to F8BBh
F990h to 080Elh
640K
531)(
102)(
6K
128)(
3ZJ(
16811
MK
PJ'O!lrams
Ava i lab l e
Pr011ra111S
Ul deo RAM
Uideo ROM
<noth i ll!I >
SljsteM llOl1
lM
Fol lowi ng the design decision made by I B M , at the first PCs the memory
was d ivided i n 4 parts:
Memory.
1 21
ROM Sca n . Duri n g "cold-boot" , after POST (Power On Self Test) and
after the default handlers instal lation , B I OS verifies the external ROMs
found on the boards i n the slots of the PC. This testing is called ROM
Sca n .
Remark. R O M Scan was not implemented i n t h e fi rst ROM-B I OS and
the fi rst PCs do not have this facil ity.
The external ROM modu les can be usually between C800 : 0 and EOOO : O
addresses . Each 2Kbytes module from this area is verified i f i t h a s a
signature having the form below. If the B I OS fi nd the ROM signature, it
wi l l i nitiate the checksum calcu lation for the mod ule. Each byte is added
mod ulo 1 OOh and the sum should be 0. If the module is found to be
val i d , B I OS executes a FAR CALL at offset 03h and the ROM must
eventually return through a FAR RET. Usually the program from the
ROM mod ule wi l l i nitial ize the dedicated hard and will i nsert certai n
addresses into TIV.
Off set
+O
+l
+2
+3
Length
Content
Remark
1
1
1
?
55h
aah
Length
?
Modu l o l O O h checksum
. ....
.... ........ ..
. ..
...... ...
1 22
i n real mode, the original PC-AT I B M used the free l i n es of the keyboa rd
controller to command the line A20 . The keyboard controller i nvalidates the
line A20 when the processor is ru n n i ng in real mod e , to keep the
compati bil ity with the precedent PCs and validates it when passi ng to
protected mode. Microsoft developed a special d river, H I M E M . SYS , which
allows the line A20 to be manipulated u nder soft contro l , allowing access to
H MA in rea l mode. By practical reasons, H MA is normally used by the DOS
system to keep a part of its code, emptying approxi mately 45Kbytes of
RAM from the conventional memory. This can be done by specifying i n
CON F I G . SYS "DOS= H I G H " .
1 1 .3 Applications
The presented application is con necti ng a 4Kbytes EPROM memory
and a 1 6Kbytes S RAM memory i n a PC system , i n the e mpty places of the
extension slots . The start address of the EPROM memory i s considered to
be CCOOOh and for the S RAM memory - DOOOOh (see fig . 1 1 .5)
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
.c..E
OE
VPP
27 1 6
rig . l l . 6
E P ROM
.-----.
7408
E P ROM
memories
Al9
Al8
Al7
Al6
Al4
AlS
Al3
Al2
All
AlO
A9
AS
A7
A6
AS
A4
A3
A2
Al
AO
AO
Table 11 . 2
EPROM
The address l i nes A 1 9-A 1 2 are used i n both memory banks, and l ines
A1 1 -A1 will be used for addressing. AO is used in selecti ng the low (even)
ban k if AO="O" or the high (odd) one if A0=" 1 " and /BH E="O" . Figure 1 1 . 7
presents the d ecoder made accord i ng to the table 1 1 . 2 .
DO
01
02
03
04
05
06
07
CS1
OE
6 2 64
Fig . 11 . 8
SRAM
Al9
Al8
Al7
Al 6
Al4
AlS
Al3
Al2
All
AlO
A9
AS
A7
A6
AS
A4
A3
A2
Al
AO
AO
Table 11 . 3
SRAM
1 25
The l ines A1 9-A1 4 will be used to generate the signal CS2 and A1 3-A1 wil l
be used t o address the memory. AO is used t o select the low (eve n )
memory ba n k , because it is con nected t o /CS 1 from a memory circuit and
/BH E is con nected to /CS 1 from the other memory, to select the high (od d )
memory ba n k .
I
A
B
c
YO
Y1
Y2
Y3
Y4
fil._Y5
Y6
G2 BY7
2
3
6
4
5
2
74 LS04
74 LS 1 38
Fig . 11 . 9
The
addr e s s
decoder
for
the
SRAM memo r i e s
1 1 .4 Exercise
a.
b.
c.
d.
Using C H ECKIT detect the memories con nected to the system o n the
I SA bus and analyze the EPROMs contents.
e.
Write an appl ication for detecti ng the ROM blocks from the memory
map.
f.
1 26
8
7
6
s
4
3
2
1
23
22
19
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
8
7
6
s
4
3
2
1
23
22
19
00
01
02
03
04
OS
06
07
18
20
21
.Q.E.
OE
VPP
MR
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
00
01
02
03
04
OS
06
07
9
10
11
13
14
1S
16
17
.Q.E.
OE
VPP
27 1 6
2716
12
13
Fi g . 1 1 . 1 0
E le c t r i c a l
1 27
10
9
B
7
6
5
4
3
25
24
21
23
2
10
9
B
7
6
5
4
3
25
24
21
23
2
DO
D1
D2
D3
D4
D5
D6
D7
AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A1 1
A12
CS 1
DO
D1
D2
D3
D4
D5
D6
D7
CS1
CS2
'M.
.GS2
'M.
OE
OE
6264
Fig . 1 1 . 1 1
AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A1 1
A12
E l ectrical
6264
s chema t i c
128
for
the
SRAM memo r i e s b l o c k
1 2 . TH E CAC H E M E M O RY
1 2.1
An
S y s tem I n te r face
Fig . 1 2 . 1
Ba s i c mode l
129
of
the
cache
I n this system , each time the processor reads or writes the cache i ntercepts
the transfer to the bus, al lowing the reduction of the system response time .
Notions about cache
Before d iscussing the basic model and the architecture of the cache
memory, some common terms wil l be defi ned .
C ache h it designates a transaction whereby the cache memory contains
the i nformation req uested by the processor.
Cache m iss designates a transaction whereby the cache memory does not
conta i n the i nformation requested by the processor.
Cache consistency. Because the cache is a copy of a small memory area ,
it is i mportant that it reflects always the content of the main memory. To
maintai n the cache consistency, the terms below are used to descri be
certai n operations. The su pervision of the address l i nes done by the cache
for a transfer represents a snooping operatio n . It allows the cache to see if
itself contains the d ata that are the object of the transfer. When the cache
takes over the i nformation from the data lines, the actual ization operation is
cal led "snarf" . The "snoop" -"s narf" processes allow the cache to keep
its consistency.
To descri be the data i nconsistency, the next terms are used : d i rty data
which means that data are mod ified i n the cache but not i n the main
memory and stale data when the data are mod ified i n the main memory
but not i n the cache.
cycle. The cache memory will do a "snarf' operation , so that the next time
the processor will find the data i n the cache. The "look aside" cache is
easier, which makes it cheaper. This architectu re provides a better
response time i n case of "cache miss" because the D RAM memory and the
cache memory see the bus cycle at the same ti me.
,- - - - - - - - - - - - - - - - - - - - -
CPU
I
I
I
I
SRAM
(Cache )
I
I
Cache
Controller
Tag RAM
- - - - - - - - - - - - - - - - - - - - - _I
System Interface
Fig . 12 . 2 "Look aside" cache archi tecture
" Look t h ro u g h " read arch itectu re
C PU-
SRAM
( Cache )
Cache
Controller
Tag
RAM
System Interface
Fig . 12 . 3 "Look through" cache architecture
The main characteristic of this architectu re is that the cache memory
is placed between the processor and the main memory. I n this case, the
cache memory sees the processor bus cycle before allowi ng the passing to
the system bus. When the processor starts a memory access, the cache
1 31
The write tech niq ues determine the way the cache memory solves a
writing cycle . The two used methods a re "write back" and "write
t h rou g h " . In "write back" method , the cache memory works l i ke a buffer.
When the processor i n itiates a writi ng cycle , the cache memory receives
the data and fi nal izes the cycle, and then when the system bus is available,
the cache memory writes the data into the main memory. This method
provides maxi m u m performance, allowi ng the processor to conti nue
workin g , while the main memory is updated later. The control of the writi ng
i nto the main memory i ncreases the cache memory complexity and costs .
I n the second method , "write throu g h " , the processor writes i nto the main
memory through the cache memory . The cache updated its content, but the
writi ng cycle conti n ues u ntil data is stored i nto the main memory. This
method is less com plex, so it is cheaper. Its performance is lower beca use
the processor must wait u ntil the main memory stores the data .
The main memory is d ivided i nto equal areas called cache pages .
The size of a page depends on the size of the cache memory and of its
organ ization .
Cache l i ne
A cache page is d ivided i nto smaller parts cal led cache lines. The
size of a cache line is determined by the processor and by the cache
memory arch itectu re .
I n fig u re 1 2 .4, w e see how the m a i n memory ca n be d ivided i nto
cache pages and l i nes.
D RAM
Memory
Cache Page
Cache Memory
Line m
-
Cache Page
Cache Page
Cache P age
Line
L i ne
Line
The organizing scheme allows each line from the main memory to be
stored at any location from the cache memory (fig . 1 2 . 5 ) . The fully
associative cache d oes not use cache pages , only cache lines. The main
memory and the cache memory are d ivided i nto equal size lines. For
1 33
example fig . 1 2 . 5 shows how line 1 from the main memory is stored i n line 0
from cache, but this is not the only possibility, l i n e 1 can be stored
anywhere in the cache memory, that is why it is ca lled "fu l ly-associative" . A
"ful ly-associative" scheme assures the best performance beca use any
memory location can be stored at any location of the cache memory. A
disadvantage is the complexity of th is system . The complexity appea rs
because we have to determine if the req uested data is i n the cache
memory in order to accomplish the time req u i rements . The cu rrent address
must be compared to all the addresses in the RAM , need ing a large
nu mber of com parisons, increasing the complexity and the i mplementation
costs for a large cache. That is the reason why th is type of cache is
commonly used only for caches smaller than 4Kbytes.
D RAM
Memory
Line m
Cache Memory
Line
L i ne
L i ne
....
\'
1\
Line m
-
'Ill
L i ne
Line
L i ne
1
O
DRAM Memory
I
Line n I II
I
I
/."" I
- I
I
Line 0
Cache memory
ine 0
Page 0
P if;g'e m
, -
Line nI ,'
Line n
Line n
Line 0
1 35
Memory
DRAM
/I
'
Line n I
- I
I
L i ne
._
I
I
I
---------- ---------
L i ne n
Cache
Memory
I
I -
ine
Page
'
Page m
L i ne
I
I
I
I
I
I
I
I
I
I
I
I
Way
Way
L i ne n
L ine n
..._
.,,
L i ne
L i ne
: - - - - - - - - - - - - - - - - - -
addressed before level L2. F ig . 1 2 . 8 shows how the L 1 and L2 cache work
in a Penti u m processor.
CPU
Ll Cache
Memory
L2 Cache
Memory
DRAM
System Interface
Fig . 12 . 8
Description
Re s e rved
De s c r iptors ind i c a t e a tab l e con t a ining
the
to
pa rame t e r s
ident i fy
the
charac t e r i s t i c s o f the cache memory
Table 12 . 6 . Descriptors
Descriptor
value
o oh
O lh
02h
03h
04h
06h
OSh
OAh
O Ch
4 0h
Cache description
Nu l l
I n s t ru c t i ons TLB , 4 K page s , 4 - way a s s o c i a t ive , 3 2
i npu t s
I n s t ru c t ions TLB , 4M page s , f u l l y a s s o c i a t ive , 3 2
i nput s
D a t a TLB , 4 K page s , 4 - way a s s co c i a t ive , 6 4 input s
D a t a TLB , 4M page s , 4 - way a s s c oc i a t ive , s inpu t s
I ns t ru c t i ons cache , S K , 4 - way a s s co c i a t ive , 3 2 - byt e
l ine s
I n s t ru c t i ons cache , 1 6 K , 4 - way a s s coc i at ive , 3 2 - byte
l in e s
D a t a cache , S K , 2 - way a s s o c i a t ive , 3 2 - byte l in e s
D a t a cache , 1 6 K , 4 - way a s s co c i a t ive , 3 2 - byte l in e s
Does not have l evel L2 cache ( P 6 f ami ly ) or L 3 ( P4 )
1 38
/
/
/
1 2 .7 Exercise
a.
b.
1 39
Appendix 1
EFLAGS register can be modified using several instructions and it is used
for branching programs (arithmetic flags) and to control the processor.
3
1
... 2 2 2 1 1
... 2 1 0 9 8
1
7
1 1 1
6 5 4
1
2
1
1
N
T
I OPL
I
N
A v R
0
I I
T
D
c M F
p F
IOPL
v v
1
3
1
9 8 7 6
0
4 3 2 1 0
D I T s z
p
A
c
0
0
1
F F F F F F
F
F
F
D I T s z
p
A
c
0
0
1
F F F F F F
F
F
F
Bi t
Label
Description
0
2
4
6
7
8
9
10
11
12 - 13
14
16
17
18
19
20
21
CF
PF
AF
ZF
SF
TF
IF
DF
OF
IOPL
NT
RF
Ca rry f l ag
P a r i t y f l ag
Aux i l iary carry f l ag
Z e r o f l ag
S ign f l ag
Trap f l ag
I n t e rrupt enab l e f l ag
D i re c t i on f l ag
Ove r f l ow f l ag
I / O Privi l ege l eve l
Ne s t e d t a s k f l ag
Re sume f l ag
Vi rtual 8 0 8 6 mode f l ag
Al ignment check f l ag 4 8 6 + )
Vi rtual inte rrup t f l ag
Virtual inte rrup t pending f l ag
I D f l ag
VM
AC
VIF
VIP
ID
141
Type Fam .
Model
0100
0100
0100
0100
0100
0000/1
0010
0011
0011
0011
xxxx
00
00
00
0100
0100
0100
0100
0101
0111
xxxx
00
00
01
00
00
0100
0100
1000
1000
xxxx
0101
0101
0001
0010
xxxx
01
0101
0001
xxxx
01
0101
0010
xxxx
01
0101
0011
xxxx
00
0101
0100
xxxx
01
0101
0100
xxxx
00
00
00
0110
0110
0110
0001
0011
0101
xxxx
00
00
0110
0110
0110
0111
xxxx
xxxx
01
0110
0011
xxxx
00
0110
1000
xxxx
00
0110
1010
xxxx
00
0110
1011
xxxx
00
1111
O O Ox
xxxx
Table
Al . l
Notes :
Description
Version
00
00
00
00
00
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
,,,
(l)
\i)
\lI
\ii
,,,
\11
,,,
,,,
\>J
""
(2)
I' I
(l)
(2)
I' I
(l)
(l)
"'
\l I
(2)
('!
(l)
"'
"'
\;)
l'J
Int e l
Intel
Int e l
I nt e l
Int e l
486
486
487
DX2
DX2
Int e l 4 8 6
Int e l 4 8 6
Int e l DX2
support
Int e l DX4
Int e l DX4
DX proce s s or
SX proc e s s o r
p roc e s sor
proc e s sor
Ove rdr ive proc e s sor
S L proce s s or
SX2 proce s s or
proc e s sor with Wr i t e Back
proce s s or
Ove rdrive proce s s or
I nt e l Xeon
1 42
Fig .
Al . 1
1 43
Appendix 2
The CMOS memory content
Address
Signi ficance
O O h - O dh Locat i on s u s e d
reg i s t e r s
POST ( Power
Oeh
On S e l f T e s t )
s t at u s b i t s
Ofh
Shut down
s t atus byt e
( the shut down
caus e )
1 - ba t t e ry supp ly mi s s i ng
1 - inva l i d checksum
1 - wrong reg i s t ered conf igura t i on
1 - wrong RAM s i z e
D3
D2
Dl
DO
DO
D1
D2
D3
D4
DS
D6
D7
l Oh
l lh
12h
13h
F l oppy d i s k
driver type
( Re s e rved )
HDD type
D7 D4
D3 DO
D7 D4
D3 DO
F i r s t HDD
Se cond HDD
( Re s erve d )
D7 D6
DS D4
1 5 - 1 6h
1 7 - 18h
F l oppy d i s k driver
00-1
10-3 , 11-4
01-2
D i sp l ay driver
0 0 - not ins t a l l ed
0 1 - 4 0 c lm - CGA , EGA , VGA
1 0 - 8 0 c lm - CGA , EGA , VGA
1 1 - Monochrome TTL
D3
0
D2
0
D1
! - Coproce s s o r i ns t a l l e d
DO
1 - F l oppy d i s k driver i ns t a l l ed
B a s e memory s i z e
1 0 0 h = 2 5 6 k , 2 0 0 h= 5 1 2 k , 2 8 0h = 6 4 0 k
Ext ended memory addr e s s ( over lM ) - 0 - 3 c 0 0 h in M
I
1 44
'
The memory locations with addresses between 1 Oh and 20h are protected by
a checksum mechanism. At reset, if the checksum does not equal the data
stored at addresses 2eh - 2fh , the CMOS memory setup routine from B I OS is
cal led .
Addr .
( AWARD )
B7 Motherboard c h i p s e t ( S i s 8 5 C 5 0 1 / 8 5 C 5 0 2 )
B O Aut omat i c conf i gurat i on not used ( l unu s e d )
( AM I )
4 1h
B 7 - B 6 awa i t ing t ime f o r I OR/ I OW cyc l e
B 5 - B4 awa i t ing t ime f o r D MA cyc l e f o r 1 6 b i t channe l s
B 3 - B 2 awa i t ing t ime f o r D MA cyc l e for 8 bit channe l s
B l EMR
undocument e d
BO
4 2 h - 4 4 h - ( AWARD ) Mothe rboard chip s e t s e t t i ngs
( AM I )
44h
B4 NM ! Announc e supp l y int e r rupt
B 3 NMI Local bu s exp i red
4 0h
1 45
4 6h
4 7h
5 0h
5 lh
52h
53h
( AWARD )
B 7 - B 6 AT Bus de l ay at b i t 3 8
B 5 - B4 AT Bus de l ay at b i t 1 6
B 3 - B2 AT Bus de l ay at b i t 8
B l - B O AT I / O bus de l ay
( AM I )
( Error : l = unu s e d )
B 7 B I OS Sys t em Cacheab l e
( Error : l = unu s e d )
B 6 V i de o B I OS Cacheab l e
B 6 - B O not used
- ( AM I )
B 7 - B 6 AT Bus de l ay at b i t 3 8
B 5 - B4 AT Bus de l ay at b i t 1 6
B 3 - B 2 AT Bus de l ay at b i t 8
B l - B O AT I / O bus de l ay
- ( AWARD ) Motherboard chip s e t s e t t i ngs
- ( AWARD ) P C I s l ot l , l a t ency 0 - 2 5 5 ( e rror : 0 )
( AM I )
B7 B ank 0 / 1 pre l oad RAS
B 6 B ank 0 / 1 acce s s w i t h Wa i t S t a t e s
B 3 - 2 Bank 0 / 1 Wa i t S t a t e s
( AWARD ) P C I s l ot l s e t t ings
B7 P I RQ O # t r i ggered inte rrup t s
0 = o n edge
l = on l eve l
B 6 - B 2 not in use
B 0 - 1 S l o t 1 IRQ s e t t ings
O O = A- P I RQO ( Erro r )
O l = B - P I RQ l
l O = C - P I RQ2
l l = D - P I RQ3
- ( AWARD ) P C I s l ot 2 , l a t ency 0 - 2 5 5 ( e rror : 0 )
( AWARD ) P C I s l o t 2 s e t t ings
( AM I )
B7
Bank 2 / 3 p re l oad RAS
B6
Bank 2 / 3 acce s s w i t h Wa i t S t a t e s
B 3 - B2
Bank 2 / 3 Wa i t s t a t e s
5 4 h ( AWARD ) P C I s l ot 3 ' l a t ency 0 - 2 5 5 ( e rror : O )
5 5 h - ( AWARD ) P C I s l ot 3 s e t t ings
5 6h - ( AWARD ) P C I s l o t 4 , l a t ency 0 - 2 5 5 ( e rror : O )
5 7 h - ( AWARD ) P C I s l o t 4 s e t t ings
5 8 h - ( AWARD ) r e s e rved for PCI bus s l ot 5
B3 on board CMD IDE Mode 3
5 9h - ( AWARD ) P C I s l o t 5 s e t t ings
5Ah - ( AWARD ) I RQ s e t t ings f o r PCI bus
B4 - B 7 P I RQ 3 # Interrupted l ine ( O =noth ing , Bh= I RQ l l , e t c )
B O - B 3 P I RQ O # Inte rrup t e d l ine
5Bh- ( AWARD ) I RQ s e t t ings for PCI bus
B4 - B 7 P I RQ3 # Inte rrup t ed l ine ( O =nothing , Bh= I RQ l l , e t c )
B O - B 3 P I RQ 2 # Inte rrrupted l ine
5 Ch - 5 Fh - ( AWARD ) not used
60h - ( AWARD ) Power management
B7
not used
1 46
1 47
1 48
Appendix 3
Appendix
PC
1/0
Port address
Reserved for
0 0 0 - 0 l Fh
0 2 0 - 0 2 lh
P I C - mas t e r ( 8 2 5 9A )
0 4 0 - 0 S Fh ( 4 0 - 4 3 h )
T ime r 8 2 5 4
0 6 0 - 0 6 Fh ( 6 0 - 6 3 h )
Keyboard Con t ro l l e r 8 0 4 2
0 7 0 - 0 7 Fh
0 8 0 - 0 9 Fh ( 8 0 - 8 3 h )
Page Reg i s t e r 7 4 LS 6 1 2
( ! 8 2 5 3 - 5 PC - XT )
( I 8 2 5 5A - P C - XT )
OAO - O B Fh
P I C - s l ave
O C O - ODFh
DMA Con t ro l l e r - ma s t e r ( 8 2 3 7 - A5 )
( 8 2 5 9A)
O FOh
OFlh
Re s e t FPU
O F 8 - 0 FFh
FPU
1 7 0 - 177h
IDE s e condary ( HD )
1F0 - 1F7h
I D E pr imary ( HD )
2 0 0 - 2 0 7h
2 7 8 - 2 7 Fh
LPT2
2 B 0 - 2 DFh
EGA Card
2Elh
G P I B Adaptor
2E2 - 2E3h
Data acqu i s i t i on ( 0 )
2 E 8 - 2 E fh
COM4
2 F 8 - 2 FFh
COM2
(O)
3 0 0 - 3 1 Fh
3 3 0 - 3 3 lh
Audi o board
3 6 0 - 3 63h
Network c a rd ( addre s s l o w )
3 6 4 - 3 67h
Re s e rved
3 6 8 - 3 6 Bh
3 6 C - 3 6 Fh
Re s e rved
3 7 8 - 3 7 Fh
LPTl
3 8 0 - 3 8 Fh
SDLC
3A0 - 3AFh
Bi synchronous 1
3 BC - 3 B Fh
MDA+LPT
3 C 0 - 3 CFh
EGA card
3 D 0 - 3 DFh
CGA card
3 E 8 - 3 E Fh
COM3
3 F 0 - 3 F7h
FD Cont ro l l er
3 F 8 - 3 FFh
COM l
1 49
Appendix 3
!lRQJ
DACK!
l.IRQJ
IUWIU!SHS'l'S(;U:
1llQ7
UIQ6
IRQ5
IR()4
lllQJ
l)ACX2
TIC
A.I.I!
+SV
osc
GND
ConnIOf Pin Al
SoturSid
81
82
BJ
64
w;
llO
It'
1!11
1>
11!0
811
1112
BIJ
BH
615
616
Dl7
81
Rl9
BX>
BZ1
Bl1
MF.Ml<>JOCSlt>lllQIO
U!Qll
OIQ12
l!lQJS
IRQM
DllCKO
DRQO
nllCK'i-
D.llQS
l)ACKh-
nR
01\CX"/
c--m
Ol
m
1)4
05
f')6
[l'7
l.l8
"'
DIO
Ill!
Dl2
OU
014
DRQ7
nt5
<5V
MA!>TER
QI()
Dl6
011
l>I
823
1124
B'l5
1126
IJl7
D2ll
il2'l
bl
1131
150
emu;.
LAZI
LAZZ
LUI
U\20
1.Al<I
LAIS
tA17
Ml!MRMl!M\'{ll8
09
DIO
DI!
011
013
llH
D15
Compon...t 5\d
CJ
C2
Cl
C4
C5
a
(.7
Cll
C9
CIO
Cit
en
Cl-'I
Cl.f
CI5
C!6
C\7
C\8
1/0CHCKV1
Ll6
t:l!!
D4
w
Dl
Ill
[l(l
l/OOIRJJY
Al\N
A
AU
Al?
Al6
Al5
AH
t\13
Al2
All
AlO
,..,
Al
Al
A1
A4
AS
M
A1
AS
119
AlO
All
Al2
AH
Al4
AIS
Al.I>
A.l'l
All
Al9
A2C
All
"22
Al!
A23
"'
""
A5
A4
A3
.\2
Al
AO
A24
A26
Ail
A'.lll
A29
/\JlJ
All
Appendix 4
The application board use a 1 6-character LCD , on single line,
PVC 1 60 1 0 1 P(N}. The display has more parts: the d isplay itself, a
microcontroller, a DDRAM (Display Data RAM } memory and a CGRAM
(Character Generator RAM} . The d isplay connector has 1 4 pins:
Pin
Signal
I/O
Function
1
2
3
4
5
6
GND
Von
Vo
RS
R/W
EN
7+14
DB O+DB 7
I
I
I
I
I
I
I
Ground
Log i c a l supp l y
LCD cont ra s t
Reg i s t e r s e l e c t i on
LCD read/wr i t e
Ac t ivat i on s igna l
Data bus
Pins 7-1 0 : D80-DB3 - 1/0 pins for data read/write from/to the d isplay
(will not be used for 4-bit transfers};
Pins 1 1 - 1 4: D 84-D87 - 1/0 pins for communication with the d isplay
(these are the pins used i n the case of 4-bit transfers};
Pin 5 : R/W - selection signal for read/write from/to the d isplay;
Pin 4 : RS - selection signal for the internal register; using the i nternal
register the d isplay can be programmed
0 = instructions register;
1 =data register;
Pin 2 : VDD - supply voltage for the display internal log ic;
Pin 3 : Vo - varying voltage applied to the display for contrast control;
P i n 1 : G N D - g round;
Pin 6 : E N (enable} - the activation of this pin selects the d isplay
1 51
Cl ear
display
CODE
DB DB DB DB DB DB DB DB
RS R/'i'l
7 6 5 4 3
2
1
0
0
Description
C l e a r s a l l d i s p l ay memory
and returns the cursor to
t h e home pos i t ion
Execut i on
t ime
l . 64s
Re turn
home
Entry
mode set
l . 64s
I /D
not to s h i f t the d i s p l ay .
The s e operat i ons are
perf ormed dur i ng data wr i t e
4 0 s
and read .
D i splay
ON/OFF
control
Cursor or
display
0
shi ft
1 S / C R/L
Func tion
set
1 DL
Set CGRAM
0
address
MSB ACG
LSB
the d i s p l ay w i t hout
chanq ing DDRAM content s .
S e t s i n t e r f a c e d a t a l engt h
( DL ) , numb e r of d i sp l ay
l i nes ( N ) and chara c t e r
f ont
4 0s
4 0s
4 0s
(F)
40s
s e t t i ng .
Set DDRAM
0
addr e s s
MSB ADD
S e t s t h e DDRAM addre s s .
DDRAM data is s ent and
LSB
rece ived a f t e r t h i s
4 0s
s e t t i ng .
Reads Busy F l ag
Read busy
f l ag &
0
address
Wri t e
data in
1
CG or
DDRAM
Read data
from CG
1
o r DDRAM
BF
M S B AC
W r i t e da ta
Re ad data
( BF ) ;
Wr i t e s i n t o DDRAM o r CGRAM
152
4 0 s
4 0s
4 0 s
Flags:
Accompan i e s d i s p l ay s h i f t when
data is wr i t t en . For norma l
operat i ons , s e t to
S=l
I /D = l
I n c rement DL= l :
8 bits
I/D=O
4 bits
S/C=l
D i s p l ay S h i f t N = l :
S / C= O
Cur s o r move N = 0 :
R/L= l
S r ight s h i f t F = l
R/L= l
Le f t s h i f t F = O :
BF=l
BF=O
(1)
l ine
l i ne
:5 1 0
5
dot s
DD RAM
C G RAM
ACG
( CGRAM )
CGRAM addre s s
ADD
AC
l = ON O = O F F
B l inking )
x 7 do t s
( Cursor -
l = ON O = O F F ( Cursor )
I n t e rn a l execut i on
Di s p l ay D a t a RAM
l = ON O =O F F ( D i s p l a y )
*
Not r e l evant
JO
11
12
13
14
15
16
I 00 I 01 I 0 2 I 0 3 1 0 4 1 I 0 6 1 0 7 1 4 0 1 4 1 1 4 2 1 4 3 1 44 1 4 5 1 4 6 1 47 1
os
The DDRAM address is sent on 7 bits . Based on the memory map, one can
establish the addresses to be sent to the data bus d i rectly on 8 bits :
Character addresses:
From the physical address, O?h to 40h there are free memory
locations (to be used for other purposes) . To display the 1 6 characters , the
first 8 are displayed from address 80h and the next 8 from address CO.
1 53
Appendix
CPUID
instruction
The non l ntel processors follow the general lines of the CPU I D
returned information significance. For some families, some values have
other significance .
Many of the non l ntel processors accept extended levels of the
CPU I D instruction . Levels 80000005 and 80000006 return cache memory
descriptors for AMO and Cyrix families.
Regis ter
EAX
EBX
ECX
ECX
T ab l e AS . 1
1 54
80000005
Regis ter
Cache description
4 M / 2 M L2 TLB
EAX
31-28
2 7 - 16
1 5 - 12
11-0
4k Ll
EBX
ECX
Tab l e A S . 2 .
Bits
#1
Signi ficance
Bits
Data
Data
Code
Code
T1B # 1
T1B , a s s o c i a t ive
T1B input s
T1B , a s s o c i a t ive
T1B , input s
#2
Signi f icance
3 1 -28
27-16
1 5 - 12
11-0
Un i f i e d 12
3 1 - 15
23 - 16
15-8
7-0
L2
12
12
12
Bits
#2
#2
#2
Signi ficance
cache s i z e i n Koc t e t s
#2
a s s o c i a t ive cache
cache l ine s number
cache l ine s i z e i n o c t e t s
for
l eve l
80000005-
#1 TLB L2 u nified cache is indicated for value OOOOb in the most significant
positions
#2
OOOOb - L2 d isabled
000 1 b - d i rect mapping
00 1 0b - 2 ways
0 1 OOb - 4 ways
0 1 1 0b - 8 ways
1 000b - 1 6 ways
1 1 1 1 b - ful l
1 55
[;..: '.
'
256 bits
REFERENCES
RE F E R E N C ES
www.pcguide. com
1 0 . [***] " Intel Processor Identification and the CPU I D Instruction" AP-485 J u ly 2001
1 1 . [***] "AM O Processor Recognition" Application Note January 2002
1 2. Buchanan, W. PC interfacing, Communications and Windows Programing
Addison Wesley 1 999
1 3. [***] www.intel. com
1 4 . Lung u ,
1 57
TEORA, 2000