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Data Sheet
14-Pin, 8-Bit Flash Microcontroller
DS41326E
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-355-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41326E-page 2
PIC16F526
14-Pin, 8-Bit Flash Microcontroller
High-Performance RISC CPU:
Standby current:
- 100 nA @ 2.0V, typical
Operating current:
- 11 A @ 32 kHz, 2.0V, typical
- 175 A @ 4 MHz, 2.0V, typical
Watchdog Timer current:
- 1 A @ 2.0V, typical
- 7 A @ 5.0V, typical
High Endurance Program and Flash Data Memory
cells:
- 100,000 write Program Memory endurance
- 1,000,000 write Flash Data Memory endurance
- Program and Flash Data retention: >40 years
Fully Static Design
Wide Operating Voltage Range: 2.0V to 5.5V:
- Wide temperature range
- Industrial: -40C to +85C
- Extended: -40C to +125C
Device
PIC16F526
Program
Memory
Peripheral Features:
12 I/O Pins:
- 11 I/O pins with individual direction control
- 1 input-only pin
- High current sink/source for direct LED drive
- Wake-up on change
- Weak pull-ups
8-bit Real-time Clock/Counter (TMR0) with 8-bit
Programmable Prescaler
Two Analog Comparators:
- Comparator inputs and output accessible
externally
- One comparator with 0.6V fixed on-chip
absolute voltage reference (VREF)
- One comparator with programmable on-chip
voltage reference (VREF)
Analog-to-Digital (A/D) Converter:
- 8-bit resolution
- 3-channel external programmable inputs
- 1-channel internal input to internal absolute
0.6 voltage reference
Data Memory
Flash (words)
SRAM (bytes)
Flash
(bytes)
1024
67
64
I/O
Comparators
Timers 8-bit
8-bit A/D
Channels
12
DS41326E-page 3
PIC16F526
VDD
RB5/OSC1/CLKIN
2
3
RB4/OSC2/CLKOUT
RC5/T0CKI
4
5
RC4/C2OUT
RC3
RB3/MCLR/VPP
VSS
12
RB1/C1IN-/AN1/ICSPCLK
11
RB2/C1OUT/AN2
10
RC0/C2IN+
RC1/C2IN-
RC2/CVREF
RB0/C1IN+/AN0/ICSPDAT
RC5/T0CKI
NC
GND
RB1/C1IN-/AN1/ICSPCLK
10
RB2/C1OUT/AN2
RC1/C2IN-
RB3/MCLR/VPP
RB0/C1IN+/AN0/ICSPDAT
11
RC2/CVREF
RB4/OSC2/CLKOUT
PIC16F526
16 15 14 13
12
RC3
RC4/C2OUT
RB5/OSC1/CLKIN
DS41326E-page 4
14
13
VDD
FIGURE 1-2:
PIC16F526
NC
FIGURE 1-1:
RC0/C2IN+
PIC16F526
Table of Contents
1.0 General Description..................................................................................................................................................................... 7
2.0 PIC16F526 Device Varieties ...................................................................................................................................................... 9
3.0 Architectural Overview .............................................................................................................................................................. 11
4.0 Memory Organization ................................................................................................................................................................ 15
5.0 Flash Data Memory Control ...................................................................................................................................................... 23
6.0 I/O Port ...................................................................................................................................................................................... 27
7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 37
8.0 Special Features of the CPU..................................................................................................................................................... 43
9.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 59
10.0 Comparator(s) ........................................................................................................................................................................... 63
11.0 Comparator Voltage Reference Module.................................................................................................................................... 69
12.0 Instruction Set Summary ........................................................................................................................................................... 71
13.0 Development Support................................................................................................................................................................ 79
14.0 Electrical Characteristics ........................................................................................................................................................... 83
15.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 97
16.0 Packaging Information............................................................................................................................................................. 107
The Microchip Web Site .................................................................................................................................................................... 115
Customer Change Notification Service ............................................................................................................................................. 115
Customer Support ............................................................................................................................................................................. 115
Reader Response ............................................................................................................................................................................. 116
Index .................................................................................................................................................................................................. 117
Product Identification System................ ........................................................................................................................................... 119
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
DS41326E-page 5
PIC16F526
NOTES:
DS41326E-page 6
PIC16F526
1.0
GENERAL DESCRIPTION
1.1
Applications
TABLE 1-1:
Clock
Memory
Peripherals
Timer Module(s)
Wake-up from Sleep on Pin Change
Features
I/O Pins
Input Pins
20
1024
67
64
TMR0
Yes
11
1
Internal Pull-ups
Yes
Yes
Number of Instructions
Packages
33
14-pin PDIP, SOIC, TSSOP, QFN
The PIC16F526 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and
precision internal oscillator.
The PIC16F526 device uses serial programming with data pin RB0 and clock pin RB1.
DS41326E-page 7
PIC16F526
NOTES:
DS41326E-page 8
PIC16F526
2.0
2.1
2.2
DS41326E-page 9
PIC16F526
NOTES:
DS41326E-page 10
PIC16F526
3.0
ARCHITECTURAL OVERVIEW
TABLE 3-1:
Device
PIC16F526
PIC16F526 MEMORY
Program
Memory
Data Memory
Flash
(words)
SRAM
(bytes)
Flash
(bytes)
1024
67
64
DS41326E-page 11
PIC16F526
FIGURE 3-1:
11
Flash Program
Memory
1K x 12
Flash Data
Memory
64x8
Program
Bus
Data Bus
Program Counter
PORTB
RB0/ICSPDAT
RB1/ICSPCLK
RB2
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RAM
67
bytes
File
Registers
STACK1
STACK2
12
PORTC
Addr MUX
Instruction Reg
Direct Addr
5-7
RC0
RC1
RC2
RC3
RC4
RC5/T0CKI
Indirect
Addr
FSR Reg
STATUS Reg
Device Reset
Timer
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decode and
Control
Power-on
Reset
Timing
Generation
Watchdog
Timer
Internal RC
Clock
Comparator 1
MUX
C1IN+
C1INC1OUT
VREF
ALU
8
W Reg
Comparator 2
C2IN+
C2INC2OUT
CVREF
CVREF
CVREF
Timer0
MCLR
VDD, VSS
8-bit ADC
AN0
AN1
AN2
VREF
DS41326E-page 12
PIC16F526
TABLE 3-2:
Name
RB0//C1IN+/AN0/
ICSPDAT
RB1/C1IN-/AN1/
ICSPCLK
RB2/C1OUT/AN2
RB3/MCLR/VPP
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
RC0/C2IN+
RC1/C2INRC2/CVREF
RC3
RC4/C2OUT
RC5/T0CKI
Function
Input
Type
RB0
TTL
C1IN+
AN
Output
Type
Description
Comparator 1 input.
AN0
AN
ICSPDAT
ST
RB1
TTL
C1IN-
AN
Comparator 1 input.
AN1
AN
ICSPCLK
ST
RB2
TTL
C1OUT
AN2
AN
RB3
TTL
MCLR
ST
VPP
HV
RB4
TTL
OSC2
XTAL
CLKOUT
RB5
TTL
OSC1
XTAL
CLKIN
ST
RC0
TTL
C2IN+
AN
RC1
TTL
C2IN-
AN
RC2
TTL
CVREF
RC3
TTL
Comparator 2 input.
Comparator 2 input.
RC4
TTL
C2OUT
RC5
TTL
T0CKI
ST
VDD
VDD
VSS
VSS
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, = Not used, TTL = TTL input,
ST = Schmitt Trigger input, HV = High Voltage
DS41326E-page 13
PIC16F526
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
PC
PC + 1
EXAMPLE 3-1:
PC + 2
1. MOVLW 03H
2. MOVWF PORTB
3. CALL SUB_1
4. BSF PORTB, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is flushed from the pipeline, while the new instruction is being fetched and then executed.
DS41326E-page 14
PIC16F526
4.1
User Memory
Space
FIGURE 4-1:
Data Memory
Space
MEMORY ORGANIZATION
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
000h
1FFh
200h
3FEh
3FFh
400h
Configuration Memory
Space
4.0
43Fh
440h
443h
444h
447h
448h
Reserved
49Fh
4A0h
Unimplemented
7FEh
Configuration Word
7FFh
DS41326E-page 15
PIC16F526
4.2
4.2.1
4.2.2
FSR<6:5>
00
01
20h
File Address
10
40h
11
60h
00h
INDF(1)
INDF(1)
INDF(1)
INDF(1)
01h
TMR0
EECON
TMR0
EECON
02h
PCL
PCL
PCL
PCL
03h
STATUS
STATUS
STATUS
STATUS
04h
FSR
FSR
FSR
FSR
05h
OSCCAL
EEDATA
OSCCAL
EEDATA
06h
PORTB
EEADR
PORTB
EEADR
07h
PORTC
PORTC
PORTC
PORTC
08h
CM1CON0
CM1CON0
CM1CON0
CM1CON0
09h
ADCON0
ADCON0
ADCON0
ADCON0
0Ah
0Bh
ADRES
CM2CON0
ADRES
CM2CON0
ADRES
CM2CON0
ADRES
CM2CON0
0Ch
VRCON
VRCON
VRCON
VRCON
0Dh
General
Purpose
Registers
0Fh
10h
2Fh
30h
General
Purpose
Registers
1Fh
50h
General
Purpose
Registers
3Fh
Bank 0
Note 1:
FIGURE 4-2:
70h
General
Purpose
Registers
5Fh
Bank 1
General
Purpose
Registers
7Fh
Bank 2
Bank 3
Not a physical register. See Section 4.8 Indirect Data Addressing: INDF and FSR Registers.
DS41326E-page 16
PIC16F526
TABLE 4-1:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page #
N/A
TRIS
--11 1111
27
N/A
OPTION
1111 1111
19
00h
INDF
xxxx xxxx
22
01h/41h
TMR0
xxxx xxxx
37
02h(1)
PCL
1111 1111
21
03h
STATUS
0001 1xxx
18
04h
FSR
05h/45h
OSCCAL
06h/46h
07h
08h
CM1CON0
09h
ADCON0
0Ah
ADRES
0Bh
CM2CON0
C2OUT
C2OUTEN
C2POL
RBWUF
Value on
Power-on
Reset
CWUF
PA0
TO
PD
DC
CAL3
CAL2
CAL1
CAL0
100x xxxx
22
1111 111-
20
27
CAL6
CAL5
PORTB
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
PORTC
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
28
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
q111 1111
63
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
1111 1100
61
C2ON
xxxx xxxx
62
C2NREF
C2PREF1
C2WU
q111 1111
64
0Ch
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
001- 1111
69
21h/61h
EECON
FREE
WRERR
WREN
WR
RD
---0 x000
23
25h/65h
EEDATA
26h/66h
EEADR
Legend:
x = unknown, u = unchanged, = unimplemented, read as '0' (if applicable), q = value depends on condition.
Shaded cells = unimplemented or unused
The upper byte of the Program Counter is not directly accessible. See Section 4.6 Program Counter for an explanation of how to
access these bits.
Note 1:
xxxx xxxx
23
--xx xxxx
23
DS41326E-page 17
PIC16F526
4.3
STATUS Register
REGISTER 4-1:
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RBWUF
CWUF
PA0
TO
PD
DC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
DS41326E-page 18
PIC16F526
4.4
OPTION Register
Note:
REGISTER 4-2:
W-1
W-1
W-1
W-1
W-1
W-1
W-1
W-1
RBWU
RBPU
T0CS(1)
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
RBWU: Enable Wake-up On Pin Change bit (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
x = Bit is unknown
If the T0CS bit is set to 1, it will override the TRIS function on the T0CKI pin.
DS41326E-page 19
PIC16F526
4.5
OSCCAL Register
REGISTER 4-3:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U-0
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-1
0000001
0000000 = Center frequency
1111111
bit 0
Unimplemented: Read as 0
DS41326E-page 20
x = Bit is unknown
PIC16F526
4.6
Program Counter
4.6.1
EFFECTS OF RESET
FIGURE 4-3:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTO Instruction
10 9 8 7
PC
0
PCL
PA0
4.7
Stack
Instruction Word
7
Status
CALL or Modify PCL Instruction
10 9 8 7
PC
0
PCL
Instruction Word
Reset to 0
PA0
0
Status
DS41326E-page 21
PIC16F526
4.8
EXAMPLE 4-1:
MOVLW
MOVWF
CLRF
NEXT
INCF
BTFSC
GOTO
CONTINUE
:
:
;initialize pointer
;to RAM
;clear INDF
;register
;inc pointer
;all done?
;NO, clear next
FSR,F
FSR,4
NEXT
;YES, continue
FIGURE 4-4:
(FSR)
6
DIRECT/INDIRECT ADDRESSING
Direct Addressing
(opcode)
4
bank select
Indirect Addressing
(FSR)
0
location select
00
01
10
11
bank
select
location select
00h
Data
Memory(1)
0Ch
0Dh
Addresses map back to
addresses in Bank 0.
0Fh
10h
2Fh
4Fh
6Fh
1Fh
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
DS41326E-page 22
PIC16F526
5.0
5.1
EXAMPLE 1:
BANKSEL EEADR
MOVF DATA_EE_ADDR, W
MOVWF EEADR
;Data Memory
BANKSEL EECON1
;Address to read
BSF EECON, RD
;EE Read
MOVF EEDATA, W
;W = EEDATA
5.2
3.
4.
5.2.1
EXAMPLE 2:
BANKSEL
EEADR
MOVLW
EE_ADR_ERASE
MOVWF
EEADR
BSF
EECON,FREE
; SELECT ERASE
BSF
EECON,WREN
; ENABLE WRITES
BSF
EECON,WR
; INITITATE ERASE
; ERASE
Note 1: The FREE bit may be set by any command normally used by the core. However, the WREN and WR bits can only be
set using a series of BSF commands, as
documented in Example 1. No other
sequence of commands will work, no
exceptions.
2: Bits <5:3> of the EEADR register indicate
which row is to be erased.
DS41326E-page 23
PIC16F526
5.2.2
EXAMPLE 3:
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
EEADR
EE_ADR_WRITE
EEADR
EE_DATA_TO_WRITE
EEDATA
EECON,WREN
EECON,WR
;
;
;
;
;
;
5.3
Write Verify
EXAMPLE 4:
LOAD ADDRESS
MOVF
EEDATA, W
BSF
EECON, RD
LOAD DATA
INTO EEDATA REGISTER
ENABLE WRITES
INITITATE ERASE
XORWF
EEDATA, W
BTFSS
STATUS, Z
GOTO
WRITE_ERR
REGISTER 5-1:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEDATA7
EEDATA6
EEDATA5
EEDATA4
EEDATA3
EEDATA2
EEDATA1
EEDATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 5-2:
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEADR5
EEADR4
EEADR3
EEADR2
EEADR1
EEADR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0.
bit 5-0
DS41326E-page 24
x = Bit is unknown
PIC16F526
REGISTER 5-3:
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
Unimplemented: Read as 0.
bit 4
bit 3
bit 2
bit 1
bit 0
5.4
Code Protection
DS41326E-page 25
PIC16F526
NOTES:
DS41326E-page 26
PIC16F526
6.0
I/O PORT
6.2
6.1
6.3
TRIS Register
PORTB
TABLE 6-1:
PORTC
Device
PIC16F526
Yes
Yes
Yes
REGISTER 6-1:
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
x = Bit is unknown
DS41326E-page 27
PIC16F526
REGISTER 6-2:
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS41326E-page 28
x = Bit is unknown
PIC16F526
6.4
I/O Interfacing
FIGURE 6-1:
RBPU
Data
Bus
Q
Data
Latch
WR
Port
I/O Pin(1)
Q
CK
W
Reg
Q
TRIS
Latch
TRIS f
CK
Reset
(2)
(2)
RD Port
Q
CK
Pin Change
ADC
COMP
Note 1:
2:
DS41326E-page 29
PIC16F526
FIGURE 6-2:
Data
Bus
WR
Port
FIGURE 6-3:
I/O Pin(1)
Data
Latch
GPPU
RBPU
MCLRE
CK
C1OUTEN
W
Reg
TRIS f
Reset
Q
TRIS
Latch
Input Pin
Q
CK
Reset
ADC Pin Enable
Data Bus
RD Port
Q
CK
RD Port
Pin Change
ADC
Note 1:
DS41326E-page 30
Note 1:
PIC16F526
FIGURE 6-4:
CK
I/O
pin(1)
Q
Data
Latch
I/O
pin(1)
CK
Q
TRIS
Latch
TRIS f
CK
FOSC/4
W
Reg
W
Reg
Data
Latch
WR
Port
Data
Bus
WR
Port
RBPU
Data
Bus
FIGURE 6-5:
Reset
(Note 2)
Q
TRIS
Latch
TRIS f
CK
RD Port
Reset
OSC2
INTOSC/RC/EC
(Note 3)
CLKOUT Enable
(Note 2)
Note 1:
Oscillator
Circuit
RD Port
OSC1
Oscillator
Circuit
CK
Pin Change
Note 1:
2:
3:
DS41326E-page 31
PIC16F526
FIGURE 6-6:
Data
Bus
WR
Port
W
Reg
TRIS f
BLOCK DIAGRAM OF
RC0/RC1
FIGURE 6-7:
CVREF
Data
Latch
I/O
pin(1)
CK
Data
Bus
WR
Port
1 I/O PIN(1)
Data
Latch
Q
CK
TRIS
Latch
W
Reg
CK
Reset
TRIS f
Q
TRIS
Latch
Q
CK
RD Port
COMP2
Note 1:
DS41326E-page 32
RD Port
Note 1:
PIC16F526
FIGURE 6-8:
Data
Bus
WR
Port
W
Reg
TRIS f
FIGURE 6-9:
I/O Pin(1)
D
Q
Data
Latch
Q
CK
Data
Bus
WR
Port
I/O Pin(1)
Data
Latch
Q
CK
C2OUTEN
D
Q
TRIS
Latch
W
Reg
CK
TRIS f
Q
TRIS
Latch
Q
CK
Reset
Reset
RD Port
RD Port
Note 1:
Note 1:
DS41326E-page 33
PIC16F526
FIGURE 6-10:
Data
Bus
WR
Port
W
Reg
TRIS f
I/O Pin(1)
D
Q
Data
Latch
Q
CK
Q
TRIS
Latch
Q
CK
T0CS
Reset
RD Port
T0CKI
Note 1:
DS41326E-page 34
PIC16F526
TABLE 6-2:
Addr
Name
Bit 7
Bit 6
RBWU
RBPU
N/A
TRIS
N/A
OPTION
03h
STATUS
06h
PORTB
07h
PORTC
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
--11 1111
--11 1111
1111 1111
1111 1111
TOCS
TOSE
PSA
PS2
PS1
PS0
PA0
TO
PD
DC
RB5
RB4
RB3
RB2
RB1
RB0
--xx xxxx
--uu uuuu
RC5
RC4
RC3
RC2
RC1
RC0
--xx xxxx
--uu uuuu
RBWUF CWUF
Legend: Shaded cells are not used by PORT registers, read as 0. = unimplemented, read as 0, x = unknown,
u = unchanged,
q = depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
TABLE 6-3:
Priority
RB0
RB1
RB2
RB3
RC0
RC1
RC2
RC4
RC5
1
2
3
AN0
C1IN+
TRISB
AN1
C1INTRISB
AN2
C1OUT
TRISB
RB3/MCLR
C2IN+
TRISC
C2INTRISC
CVREF
TRISC
C2OUT
TRISC
T0CKI
TRISC
DS41326E-page 35
PIC16F526
6.5
6.5.1
EXAMPLE 6-1:
6.5.2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
SUCCESSIVE OPERATIONS ON
I/O PORTS
FIGURE 6-11:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g. DSTEMP)
PC
MOVWF PORTB
PC + 1
MOVF PORTB, W
Q1 Q2 Q3 Q4
PC + 2
PC + 3
NOP
NOP
RB<5:0>
Instruction
Executed
DS41326E-page 36
MOVWF PORTB
(Write to PORTB)
Port pin
sampled here
MOVF PORTB,W
(Read PORTB)
PIC16F526
7.0
FIGURE 7-1:
Comparator
Output
FOSC/4
PSOUT
1
1
1
T0CKI
pin
Programmable
Prescaler(2)
T0SE(1)
T0CS(1)
8
Sync with
Internal
Clocks
TMR0 Reg
PSOUT
(2 cycle delay) Sync
PSA(1)
3
PS2(1), PS1(1), PS0(1)
C1T0CS(3)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer.
3: The C1T0CS bit is in the CM1CON0 register.
DS41326E-page 37
PIC16F526
FIGURE 7-2:
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
T0 + 1
T0 + 2
Instruction
Executed
PC + 4
PC + 5
PC + 6
NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
NT0 + 2
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
Read TMR0
reads NT0
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC 1
Instruction
Fetch
PC
PC + 1
MOVWF TMR0
T0
Timer0
PC + 2
T0 + 1
Name
PC + 4
PC + 5
NT0
Read TMR0
reads NT0
Write TMR0
executed
TABLE 7-1:
PC + 3
PC + 6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Executed
Addr
PC + 3
NT0
Write TMR0
executed
FIGURE 7-3:
PC
(Program
Counter)
PC + 2
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
NT0 + 1
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
Read TMR0
reads NT0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
All Other
Resets
xxxx xxxx
uuuu uuuu
1111 1111
uuuu uuuu
01h
TMR0
08h
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
0Bh
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
1111 1111
uuuu uuuu
N/A
OPTION
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
N/A
TRIS(1)
--11 1111
--11 1111
Legend:
Note 1:
Value on
Power-On
Reset
DS41326E-page 38
PIC16F526
7.1
7.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
FIGURE 7-4:
7.1.2
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
(3)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
Note 1:
T0
T0 + 1
T0 + 2
Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = 4 TOSC max.
2:
3:
DS41326E-page 39
PIC16F526
7.2
Prescaler
7.2.1
SWITCHING PRESCALER
ASSIGNMENT
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0 WDT)
CLRWDT
;Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
MOVLW b'00xx1111'
CLRWDT
;PS<2:0> are 000 or 001
MOVLW b'00xx1xxx' ;Set Postscaler to
OPTION
;desired WDT rate
EXAMPLE 7-2:
CLRWDT
MOVLW
CHANGING PRESCALER
(WDT TIMER0)
OPTION
DS41326E-page 40
PIC16F526
FIGURE 7-5:
TCY (= FOSC/4)
Data Bus
0
Comparator
Output
0
1
M
U
X
1
0
1
T0CKI
Pin
M
U
X
T0SE(1)
T0CS(1)
Sync
2
Cycles
TMR0 Reg
PSA(1)
C1TOCS
0
Watchdog
Timer
8-bit Prescaler
M
U
X
8
PS<2:0>(1)
8-to-1 MUX
(1)
PSA
WDT Enable bit
0
MUX
PSA(1)
WDT
Time-out
Note 1:
DS41326E-page 41
PIC16F526
NOTES:
DS41326E-page 42
PIC16F526
8.0
8.1
Configuration Bits
DS41326E-page 43
PIC16F526
REGISTER 8-1:
CPDF
MCLRE
CP
WDTE
FOSC2
FOSC1
bit 7
FOSC0
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1: Refer to the PIC16F526 Memory Programming Specification, DS41317 to determine how to access the
Configuration Word.
2: DRT length (18 ms or 1 ms) is a function of Clock mode selection. It is the responsibility of the application
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Section 14.1 DC Characteristics: PIC16F526 (Industrial) and
Section 14.2 DC Characteristics: PIC16F526 (Extended) for VDD rise time and stability requirements
for this mode of operation.
DS41326E-page 44
PIC16F526
8.2
Oscillator Configurations
8.2.1
FIGURE 8-1:
OSCILLATOR TYPES
LP:
XT:
HS:
INTRC:
EXTRC:
EC:
8.2.2
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
Low-Power Crystal
Crystal/Resonator
High-Speed Crystal/Resonator
Internal 4/8 MHz Oscillator
External Resistor/Capacitor
External High-Speed Clock Input
C1(1)
Note 1: This device has been designed to perform to the parameters of its data sheet.
It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance characteristics than its earlier version. These
differences may cause this device to
perform differently in your application
than the earlier version of this device.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capacitor
values and/or the Oscillator mode may
be required.
RS(2)
C2(1)
Note 1:
2:
3:
PIC16F526
Sleep
XTAL
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
OSC1
RF(3)
To internal
logic
OSC2
FIGURE 8-2:
RB5/OSC1/CLKIN
PIC16F526
OSC2/CLKOUT/RB4
Note 1:
OSC2/CLKOUT/RB4(1)
TABLE 8-1:
Osc
Type
Resonator
Freq.
XT
4.0 MHz
30 pF
30 pF
HS
16 MHz
10-47 pF
10-47 pF
Note 1:
Cap. Range
C1
Cap. Range
C2
DS41326E-page 45
PIC16F526
TABLE 8-2:
Osc
Type
Resonator
Freq.
Cap. Range
C1
Cap. Range
C2
LP
32 kHz(1)
15 pF
15 pF
XT
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
20 MHz
15-47 pF
15-47 pF
HS
Note 1:
2:
8.2.3
FIGURE 8-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
CLKIN
74AS04
PIC16F526
10k
XTAL
FIGURE 8-4:
330
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
To Other
Devices
330
74AS04
74AS04
74AS04
CLKIN
0.1 mF
PIC16F526
XTAL
8.2.4
EXTERNAL RC OSCILLATOR
10k
20 pF
DS41326E-page 46
20 pF
PIC16F526
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
FIGURE 8-5:
EXTERNAL RC
OSCILLATOR MODE
VDD
REXT
OSC1
Internal
clock
CEXT
PIC16F526
VSS
FOSC/4
OSC2/CLKOUT
8.2.5
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
DS41326E-page 47
PIC16F526
8.3
Reset
TABLE 8-3:
Register
W
Power-on Reset
qqqq qqq0(1)
qqqq qqq0(1)
INDF
00h
xxxx xxxx
uuuu uuuu
TMR0
01h
xxxx xxxx
uuuu uuuu
PCL
02h
1111 1111
1111 1111
STATUS
03h
0001 1xxx
FSR
04h
100x xxxx
1uuu uuuu
OSCCAL
05h
1111 111-
uuuu uuu-
PORTB
06h
--xx xxxx
--uu uuuu
PORTC
07h
--xx xxxx
--uu uuuu
CMICON0
08h
q111 1111
quuu uuuu
ADCON0
09h
1111 1100
1111 1100
ADRES
0Ah
xxxx xxxx
uuuu uuuu
CM2CON0
0Bh
q111 1111
quuu uuuu
VRCON
0Ch
001-1111
uuu-uuuu
OPTION
1111 1111
1111 1111
TRISB
--11 1111
--11 1111
qq0q quuu(2)
TRISC
--11 1111
--11 1111
EECON
21h/61h
---0 x000
---0 q000
EEDATA
25h/65h
xxxx xxxx
uuuu uuuu
EEADR
26h/66h
--xx xxxx
--uu uuuu
DS41326E-page 48
PIC16F526
TABLE 8-4:
Power-on Reset
0001 1xxx
000u uuuu
0001 0uuu
0000 0uuu
0000 uuuu
1001 0uuu
0101 0uuu
DS41326E-page 49
PIC16F526
8.3.1
MCLR ENABLE
FIGURE 8-6:
MCLR SELECT
RBWU
RB3/MCLR/VPP
MCLRE
8.4
Internal MCLR
The PIC16F526 device incorporates an on-chip Poweron Reset (POR) circuitry, which provides an internal
chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program
the RB3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD, or program the pin as RB3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 14-5 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Section 14.0 Electrical Characteristics for details.
When the device starts normal operation (exit the
Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating parameters
are met.
DS41326E-page 50
PIC16F526
FIGURE 8-7:
VDD
Power-up
Detect
RB3/MCLR/VPP
MCLR Reset
S
MCLRE
WDT Time-out
Pin Change
Sleep
WDT Reset
Start-up Timer
(10 ms, 1.125 ms
or 18 ms)
CHIP Reset
Comparator Change
Wake-up on
Comparator Change
FIGURE 8-8:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 8-9:
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS41326E-page 51
PIC16F526
FIGURE 8-10:
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
DS41326E-page 52
PIC16F526
8.5
8.6
TABLE 8-5:
Oscillator
Configuration
Subsequent
Resets
18 ms
18 ms
EC
1.125 ms
10 s
INTOSC, EXTRC
1.125 ms
10 s
HS, XT, LP
8.6.1
WDT PERIOD
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
DS41326E-page 53
PIC16F526
FIGURE 8-11:
Watchdog
Time
M
U
X
Postscaler
8-to-1 MUX
PS<2:0>(1)
PSA
WDT Enable
Configuration
Bit
1
MUX
PSA(1)
WDT Time-out
Note 1:
TABLE 8-6:
Address
N/A
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
RBWU
RBPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
DS41326E-page 54
PIC16F526
8.7
TABLE 8-7:
FIGURE 8-12:
VDD
VDD
33k
PIC12F510
PIC16F506
Q1
10k
TO/PD/RBWUF/CWUF
STATUS AFTER RESET
CWUF RBWUF TO PD
MCLR(2)
40k(1)
Reset Caused By
Power-up
Note 1:
2:
FIGURE 8-13:
VDD
R1
Q1
R2
Note 1:
PIC12F510
PIC16F506
MCLR(2)
40k(1)
Reset on Brown-out
BROWN-OUT
PROTECTION CIRCUIT 2
VDD
Legend: u = unchanged
8.8
BROWN-OUT
PROTECTION CIRCUIT 1
VDD
2:
R1
R1 + R2
= 0.7V
FIGURE 8-14:
BROWN-OUT
PROTECTION CIRCUIT 3
VDD
MCP809
VSS
Bypass
Capacitor
VDD
VDD
RST
MCLR
PIC12F510
PIC16F506
Note:
DS41326E-page 55
PIC16F526
8.9
8.9.1
SLEEP
8.9.2
2.
3.
Note:
4.
DS41326E-page 56
PIC16F526
8.10
Program Verification/Code
Protection
FIGURE 8-15:
8.11
ID Locations
8.12
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC16F526
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB1
Data
RB0
VDD
To Normal
Connections
DS41326E-page 57
PIC16F526
NOTES:
DS41326E-page 58
PIC16F526
9.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER
Note:
9.1
Clock Divisors
9.1.1
The ADC clock is derived from the instruction clock. The ADCS divisors are then
applied to create the ADC clock
VOLTAGE REFERENCE
9.1.2
9.1.3
TABLE 9-1:
Event
MCLR
ADCS<1:0>
11
Conversion completed
CS<1:0>
Conversion terminated
CS<1:0>
Power-on
11
11
9.1.4
DS41326E-page 59
PIC16F526
9.1.5
SLEEP
TABLE 9-2:
Source
ADCS
<1:0>
Divisor
20
MHz
16
MHz
11
.5 s
1 s
INTOSC
500
kHz
350
kHz
200
kHz
100
kHz
32 kHz
FOSC
10
.2 s
.25 s
.5 s
1 s
4 s
8 s
11 s
20 s
40 s
125 s
FOSC
01
.4 s
.5 s
1 s
2 s
8 s
16 s
23 s
40 s
80 s
250 s
FOSC
00
16
.8 s
1 s
2 s
4 s
16 s
32 s
46 s
80 s
160 s
500 s
TABLE 9-3:
Entering
Sleep
ANS0
Unchanged Unchanged
Wake or
Reset
DS41326E-page 60
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
PIC16F526
9.1.6
REGISTER 9-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
ANS1
ANS0
ADCS1
ADCS0
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5-4
bit 3-2
bit 1
bit 0
Note 1:
When the ANS bits are set, the channels selected will automatically be forced into Analog mode, regardless of the pin
function previously defined. The only exception to this is the comparator, where the analog input to the comparator and
the ADC will be active at the same time. It is the users responsibility to ensure that the ADC loading on the comparator
input does not affect their application.
2:
3:
4:
5:
DS41326E-page 61
PIC16F526
REGISTER 9-2:
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
EXAMPLE 9-1:
PERFORMING AN
ANALOG-TO-DIGITAL
CONVERSION
EXAMPLE 9-2:
loop0
MOVLW 0xF1
;configure A/D
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
BTFSC ADCON0, 1;wait for DONE
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop1
loop2
CHANNEL SELECTION
CHANGE DURING
CONVERSION
MOVLW 0xF1
MOVWF ADCON0
BSF ADCON0, 1
BSF ADCON0, 2
;configure A/D
loop0
;start conversion
;setup for read of
;channel 1
BTFSC ADCON0, 1;wait for DONE
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
loop1
BSF ADCON0, 2
DS41326E-page 62
x = Bit is unknown
loop2
PIC16F526
10.0
COMPARATOR(S)
REGISTER 10-1:
and
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
x = Bit is unknown
2: When comparator is turned on, these control bits assert themselves. Otherwise, the other registers have
precedence.
DS41326E-page 63
PIC16F526
REGISTER 10-2:
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
x = Bit is unknown
DS41326E-page 64
PIC16F526
FIGURE 10-1:
C1PREF
C1IN+
C1IN-
C1OUT (Register)
VREF
(0.6V)
C1OUTEN
0
C1NREF
C1ON
C1POL
T0CKI
T0CKI Pin
C1T0CS
RC4/C2OUT
C2PREF1
C2IN+
1
0
READ
CM1CON0
C2OUTEN
+
C2OUT (Register)
C2PREF2
C2INC2ON
C2POL
1
0
CVREF
C2NREF
C1WU
S
CWUF
READ
CM2CON0
C2WU
DS41326E-page 65
PIC16F526
10.1
Comparator Operation
FIGURE 10-2:
SINGLE COMPARATOR
VIN+
VIN-
Result
Note:
10.5
10.6
VIN-
VIN+
Result
10.7
10.2
Comparator Reference
10.3
10.4
Effects of Reset
10.8
Comparator Output
DS41326E-page 66
PIC16F526
FIGURE 10-3:
RS < 10 K
AIN
CPIN
5 pF
VA
VT = 0.6V
RIC
ILEAKAGE
500 nA
VSS
Legend:
TABLE 10-1:
CPIN
VT
ILEAKAGE
RIC
RS
VA
=
=
=
=
=
=
Input Capacitance
Threshold Voltage
Leakage Current at the Pin
Interconnect Resistance
Source Impedance
Analog Voltage
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Value on All
Other Resets
STATUS
RBWUF
CWUF
PA0
TO
PD
DC
0001 1xxx
qq0q quuu
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
q111 1111
quuu uuuu
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
q111 1111
quuu uuuu
--11 1111
--11 1111
Name
TRIS
Legend:
DS41326E-page 67
PIC16F526
NOTES:
DS41326E-page 68
PIC16F526
11.0
COMPARATOR VOLTAGE
REFERENCE MODULE
11.2
11.1
EQUATION 11-1:
REGISTER 11-1:
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
VROE
VRR
VR3
VR2
VR1
VR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3-0
x = Bit is unknown
Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the
CVREF pin.
DS41326E-page 69
PIC16F526
FIGURE 11-1:
8R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator 2
Input
VR<3:0>
RC2/CVREF
VREN
VR<3:0> = 0000
VRR
VROE
TABLE 11-1:
Name
VRCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Value on all
other Resets
uuu- uuuu
VREN
VROE
VRR
VR3
VR2
VR1
VR0
001- 1111
CM1CON0
C1OUT
C1OUTEN
C1POL
C1T0CS
C1ON
C1NREF
C1PREF
C1WU
q111 1111
quuu uuuu
CM2CON0
C2OUT
C2OUTEN
C2POL
C2PREF2
C2ON
C2NREF
C2PREF1
C2WU
q111 1111
quuu uuuu
Legend:
DS41326E-page 70
PIC16F526
12.0
TABLE 12-1:
Description
Register file address (0x00 to 0x7F)
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register f)
Default is d = 1
label
Label name
TOS
Top-of-Stack
PC
WDT
TO
Power-down bit
Options
Contents
italics
FIGURE 12-1:
6
OPCODE
5
d
0
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11
OPCODE
8 7
5 4
b (BIT #)
0
f (FILE #)
OPCODE
0
k (literal)
OPCODE
0
k (literal)
Time-out bit
PD
< >
0xhhh
Program Counter
dest
OPCODE FIELD
DESCRIPTIONS
Field
f
Assigned to
Register bit field
In the set of
User defined term (font is courier)
DS41326E-page 71
PIC16F526
TABLE 12-2:
Mnemonic,
Operands
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Cycles
12-Bit Opcode
MSb
LSb
Status
Notes
Affected
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
DS41326E-page 72
PIC16F526
ADDWF
Add W and f
BCF
f,d
Bit Clear f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 f 31
d 01
Operands:
0 f 31
0b7
Operation:
Operation:
0 (f<b>)
Status Affected:
None
Description:
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 31
0b7
Status Affected: Z
Operation:
1 (f<b>)
Description:
Status Affected:
None
Description:
ANDWF
AND W with f
BTFSC
Syntax:
[ label ] ANDWF
ANDLW
Syntax:
[ label ] ANDLW
Operands:
0 k 255
Operation:
f,d
f,b
f,b
Syntax:
Operands:
0 f 31
d [0,1]
Operands:
Operation:
Operation:
skip if (f<b>) = 0
Status Affected: Z
Status Affected:
None
Description:
Description:
DS41326E-page 73
PIC16F526
BTFSS
CLRW
Syntax:
Syntax:
[ label ] CLRW
0 f 31
0b<7
Operands:
None
Operation:
00h (W);
1Z
Operands:
Clear W
Operation:
skip if (f<b>) = 1
Status Affected:
None
Status Affected:
Description:
Description:
CALL
Subroutine Call
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 255
Operands:
None
Operation:
(PC) + 1 Top-of-Stack;
k PC<7:0>;
(STATUS<6:5>) PC<10:9>;
0 PC<8>
Operation:
00h WDT;
0 WDT prescaler (if assigned);
1 TO;
1 PD
Status Affected:
None
Status Affected:
TO, PD
Description:
Description:
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
Syntax:
[ label ] COMF
Operands:
0 f 31
Operands:
Operation:
00h (f);
1Z
0 f 31
d [0,1]
Operation:
(f) (dest)
Status Affected:
Status Affected:
Description:
Description:
DS41326E-page 74
f,d
PIC16F526
DECF
Decrement f
INCF
Syntax:
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
(f) 1 (dest)
Operation:
(f) + 1 (dest)
Status Affected:
Status Affected:
Description:
Decrement register f. If d is 0,
the result is stored in the W
register. If d is 1, the result is
stored back in register f.
Description:
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
(f) 1 d;
Operation:
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 511
Operands:
0 k 255
Operation:
k PC<8:0>;
STATUS<6:5> PC<10:9>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
skip if result = 0
GOTO k
Increment f
INCF f,d
INCFSZ f,d
IORLW k
DS41326E-page 75
PIC16F526
IORWF
Inclusive OR W with f
MOVWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
Operation:
(W) (f)
Operation:
Status Affected:
None
Status Affected:
Description:
Description:
MOVF
Move f
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 31
d [0,1]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
IORWF
f,d
MOVF f,d
Move W to f
MOVWF
NOP
Operation:
(f) (dest)
Status Affected:
Description:
MOVLW
Move Literal to W
OPTION
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
(W) OPTION
Status Affected:
None
Status Affected:
None
Description:
Description:
DS41326E-page 76
MOVLW k
OPTION
PIC16F526
RETLW
SLEEP
Syntax:
[ label ]
Syntax:
[label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W);
TOS PC
Operation:
00h WDT;
0 WDT prescaler;
1 TO;
0 PD
RETLW k
SLEEP
Status Affected:
None
Description:
Status Affected:
Description:
RLF
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[label ]
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
Operation:
Status Affected:
Status Affected:
C, DC, Z
Description:
Description:
RLF
f,d
SUBWF f,d
register f
RRF
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
Operation:
Status Affected:
(f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Description:
Status Affected:
None
Description:
RRF f,d
register f
DS41326E-page 77
PIC16F526
TRIS
XORWF
Syntax:
[ label ] TRIS
Syntax:
[ label ] XORWF
Operands:
f=6
Operands:
Operation:
0 f 31
d [0,1]
Exclusive OR W with f
f,d
Status Affected:
None
Operation:
Description:
TRIS register f (f = 6 or 7) is
loaded with the contents of the W
register
Status Affected:
Description:
XORLW
Syntax:
[label ]
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Description:
DS41326E-page 78
XORLW k
PIC16F526
13.0
DEVELOPMENT SUPPORT
13.1
DS41326E-page 79
PIC16F526
13.2
13.3
13.4
MPASM Assembler
13.5
13.6
DS41326E-page 80
PIC16F526
13.7
13.8
13.9
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
DS41326E-page 81
PIC16F526
13.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
13.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
DS41326E-page 82
PIC16F526
14.0
ELECTRICAL CHARACTERISTICS
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
DS41326E-page 83
PIC16F526
PIC16F526 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 14-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
INTOSC OR
EC MODE
ONLY
2.5
2.0
0
20
10
25
Frequency (MHz)
FIGURE 14-2:
Oscillator Mode
LP
XT
XTRC
INTOSC
EC
HS
0
200 kHz
4 MHz
8 MHz
20 MHz
Frequency
DS41326E-page 84
PIC16F526
14.1
DC Characteristics
Param
No.
Sym.
Characteristic
Min.
Typ.(1) Max.
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
D002
VDR
1.5*
D003
VPOR
Vss
D004
SVDD
0.05*
V/ms
D005
IDDP
250*
D010
IDD
Supply Current(3, 4, 6)
175
400
250
700
A
A
250
0.75
400
1.2
A
mA
1.4
2.2
mA
11
38
22
55
A
A
D020
IPD
Power-down Current(5)
0.1
0.35
1.2
2.2
A
A
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current(5)
1.0
7.0
3.0
16.0
A
A
VDD = 2.0V
VDD = 5.0V
D023
ICMP
Comparator Current(5)
15
60
26
76
A
A
D022
30
75
75
135
A
A
D023
IFVR
100
120
175
205
D024
IAD*
120
150
2.0V
200
250
5.0V
DS41326E-page 85
PIC16F526
14.2
DC Characteristics
Param
No.
Sym.
Characteristic
Min.
Typ.(1) Max.
Units
Conditions
D001
VDD
Supply Voltage
2.0
5.5
D002
VDR
1.5*
D003
VPOR
Vss
D004
SVDD
0.05*
V/ms
D005
IDDP
250*
D010
IDD
Supply Current(3,4,6)
175
400
250
700
A
A
250
0.75
400
1.2
A
mA
1.4
2.2
mA
11
38
26
110
A
A
D020
IPD
Power-down Current(5)
0.1
0.35
9.0
15.0
A
A
VDD = 2.0V
VDD = 5.0V
D022
IWDT
WDT Current(5)
1.0
7.0
18
22
A
A
VDD = 2.0V
VDD = 5.0V
D023
ICMP
Comparator Current(5)
15
60
26
76
A
A
D022
30
75
75
135
A
A
D023
IFVR
100
130
175
220
D024
IAD*
120
150
2.0V
200
250
5.0V
DS41326E-page 86
PIC16F526
TABLE 14-1:
DC CHARACTERISTICS
Param
Sym.
No.
VIL
Characteristic
Min.
Typ.
Max.
Units
Conditions
D030
D030A
Vss
0.8
Vss
0.15 VDD
Otherwise
D031
Vss
0.15 VDD
D032
MCLR, T0CKI
Vss
0.15 VDD
D033
Vss
0.15 VDD
D033
Vss
0.3 VDD
D033
Vss
0.3
VIH
D040
D040A
2.0
VDD
0.25VDD
+ 0.8V
VDD
Otherwise
For entire VDD range
D041
0.85VDD
VDD
D042
MCLR, T0CKI
0.85VDD
VDD
D042A
0.85VDD
VDD
D042A
0.7VDD
VDD
D043
1.6
VDD
50
250
400
D070
IPUR
IIL
D060
I/O ports
D061
RB3/MCLR(3)
0.7
D063
OSC1
0.6
0.6
VDD 0.7
VDD 0.7
VOL
D080
D080A
VOH
D090
D090A
15
pF
D101
CIO
50
pF
D120
ED
Byte endurance
100K
1M
E/W
40C TA +85C
D120A
ED
Byte endurance
10K
100K
E/W
+85C TA +125C
D121
VMIN
5.5
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F526 be driven with external clock in RC mode.
2: Negative current is defined as coming out of the pin.
3: This spec. applies to RB3/MCLR configured as RB3 with pull-up disabled.
4: This spec. applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed
will be the same whether or not the pin is configured as RB3 with pull-up enabled or as MCLR.
5: The leakage current on the nMCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage may be measured at different input voltages.
DS41326E-page 87
PIC16F526
TABLE 14-2:
COMPARATOR SPECIFICATIONS.
Comparator Specifications
Characteristics
Sym.
Min.
Typ.
Max.
Units
0.70
VIVRF
0.50
0.60
VOS
5.0
10
mV
VCM
VDD 1.5
CMRR*
Response Time
(1)*
CMRR
55
db
TRT
150
400
ns
TMC2COV
10
Comments
TABLE 14-3:
Sym.
CVRES
*
Note 1:
2:
Typ.
Max.
Units
Resolution
Characteristics
VDD/24*
VDD/32
LSb
LSb
Comments
Absolute Accuracy(2)
1/2*
1/2*
LSb
LSb
2K*
Settling Time(1)
10*
DS41326E-page 88
PIC16F526
TABLE 14-4:
Sym.
Characteristic
Min.
Typ.
Max.
Units
bit
Conditions
NR
Resolution
Integral Error
1.5
1.5
-0.7
+2.2
A03
EINL
A04
A06
A07
EGN
Gain Error
A10
Monotonicity
A25
VAIN
Analog Input
Voltage
VSS
A30
ZAIN
Recommended
Impedance of
Analog Voltage
Source
(1)
VDD
10
guaranteed
TABLE 14-5:
VDD (Volts)
RB0/RB1/RB4
2.0
5.5
RB3
2.0
5.5
Min.
Typ.
Max.
Units
-40
25
85
125
-40
25
85
125
73K
73K
82K
86K
15K
15K
19K
23K
105K
113K
123K
132k
21K
22K
26k
29K
186K
187K
190K
190K
33K
34K
35K
35K
-40
25
85
125
-40
25
85
125
63K
77K
82K
86K
16K
16K
24K
26K
81K
93K
96k
100K
20k
21K
25k
27K
96K
116K
116K
119K
22K
23K
28K
29K
DS41326E-page 89
PIC16F526
14.3
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T Time
to
mc
MCLR
ck
CLKOUT
osc
Oscillator
cy
Cycle time
os
OSC1
drt
t0
T0CKI
io
I/O port
wdt
Watchdog Timer
Fall
Period
High
Rise
Invalid (high-impedance)
Valid
Low
High-impedance
FIGURE 14-3:
LOAD CONDITIONS
Legend:
pin
CL
VSS
DS41326E-page 90
PIC16F526
FIGURE 14-4:
Q1
Q3
Q2
Q4
Q1
OSC1
1
TABLE 14-6:
AC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ.(1)
Max.
1A
FOSC
DC
DC
20
DC
200
kHz
Oscillator Frequency
TOSC
External CLKIN
(2)
Period(2)
Oscillator Period(2)
Units
Conditions
LP Oscillator mode
0.1
20
200
kHz
250
ns
XT Oscillator mode
50
ns
LP Oscillator mode
LP Oscillator mode
250
ns
250
10,000
ns
XT Oscillator mode
50
250
ns
TCY
200
4/FOSC
ns
TosL,
TosH
50*
ns
XT Oscillator
2*
LP Oscillator
10*
ns
HS/EC Oscillator
TosR,
TosF
25*
ns
XT Oscillator
50*
ns
LP Oscillator
15*
ns
HS/EC Oscillator
*
Note 1:
2:
DS41326E-page 91
PIC16F526
TABLE 14-7:
AC CHARACTERISTICS
Param
No.
Freq.
Min.
Tolerance
F10
Sym.
FOSC
Characteristic
Internal Calibrated
INTOSC Frequency(1)
Typ.
Max.
Units
Conditions
1%
7.92
8.00
8.08
2%
7.84
8.00
8.16
5%
7.60
8.00
8.40
DS41326E-page 92
PIC16F526
FIGURE 14-5:
I/O TIMING
Q1
Q4
Q2
Q3
OSC1
I/O Pin
(input)
17
I/O Pin
(output)
19
18
New Value
Old Value
20, 21
Note:
All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 14-8:
TIMING REQUIREMENTS
Sym.
TOSH2IOV
Characteristic
OSC1 (Q1 cycle) to Port Out Valid(2), (3)
18
TOSH2IOI
19
TIOV2OSH
20
21
TIOR
TIOF
Time(3)
Time(3)
time)(2)
Min.
Typ.(1)
Max.
Units
100*
ns
50
ns
20
ns
10
50**
ns
10
58**
ns
DS41326E-page 93
PIC16F526
FIGURE 14-6:
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
31
34
34
I/O pin(1)
Note 1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT Reset only in XT, LP and HS modes.
TABLE 14-9:
AC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ.(1)
Max.
Units
30
TMCL
2000*
ns
VDD = 5.0V
31
TWDT
9*
9*
18*
18*
30*
40*
ms
ms
32
TDRT
18*
18*
30*
40*
ms
ms
0.5*
0.5*
1.125*
1.125*
2*
2.5*
ms
ms
2000*
ns
Standard
Short
34
*
Note 1:
TIOZ
Conditions
DS41326E-page 94
PIC16F526
FIGURE 14-7:
T0CKI
40
41
42
AC CHARACTERISTICS
Param
Sym.
No.
40
41
42
*
Note 1:
Tt0H
Tt0L
Tt0P
Characteristic
T0CKI High Pulse
Width
No Prescaler
No Prescaler
T0CKI Period
With Prescaler
With Prescaler
Min.
ns
10*
ns
ns
10*
ns
20 or TCY + 40* N
ns
Conditions
Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
DS41326E-page 95
PIC16F526
TABLE 14-11: FLASH DATA MEMORY WRITE/ERASE TIME
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
Operating Voltage VDD range is described in
Section 14.1 DC Characteristics: PIC16F526 (Industrial)
AC CHARACTERISTICS
Param
No.
Sym.
43
TDW
44
TDE
*
Note 1:
Min.
Typ.(1)
Max.
Units
3.5
ms
3.5
ms
Characteristic
Conditions
DS41326E-page 96
PIC16F526
15.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at 25C. Maximum or minimum represents (mean + 3) or (mean 3) respectively, where s is a standard deviation, over each temperature range.
FIGURE 15-1:
3.00
2.50
IDD (mA)
2.00
1.50
Typical 5V
1.00
0.50
Max. 2V
Typical 2V
0.00
5
10
15
20
25
Fosc (MHz)
DS41326E-page 97
PIC16F526
FIGURE 15-2:
800
700
600
IDD (A)
500
5V
400
300
200
2V
100
0
0
FOSC (MHz)
FIGURE 15-3:
800
5V
700
600
IDD (A)
500
400
300
2V
200
100
0
0
FOSC (MHz)
DS41326E-page 98
PIC16F526
FIGURE 15-4:
120
100
IDD (A)
80
60
32 kHz Typical
40
20
0
1
VDD (V)
DS41326E-page 99
PIC16F526
FIGURE 15-5:
0.45
0.40
0.35
IPD (A)
0.30
0.25
0.20
0.15
0.10
0.05
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-6:
18.0
16.0
14.0
Max. 125C
IPD (A)
12.0
10.0
8.0
6.0
4.0
Max. 85C
2.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41326E-page 100
PIC16F526
FIGURE 15-7:
9
8
IPD (A)
6
5
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-8:
25.0
20.0
IPD (A)
Max. 125C
15.0
10.0
Max. 85C
5.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41326E-page 101
PIC16F526
FIGURE 15-9:
80
Maximum
Typical
IPD (A)
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-10:
50
Typical: Statistical Mean @25C
Maximum: Mean (Worst-Case Temp) + 3
(-40C to 125C)
Max. 125C
45
40
Max. 85C
35
Time (ms)
30
Typical. 25C
25
20
Min. -40C
15
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41326E-page 102
PIC16F526
FIGURE 15-11:
0.8
0.7
Max. 125C
0.6
Max. 85C
VOL (V)
0.5
0.4
Typical 25C
0.3
0.2
Min. -40C
0.1
0.0
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 15-12:
0.45
Typical: Statistical Mean @25C
Typical:
Statistical
Mean @25C
Maximum:
Mean
(Worst-Case
Temp) + 3
Maximum: Meas(-40C
+ 3 to 125C)
(-40C to 125C)
0.40
Max. 125C
0.35
Max. 85C
VOL (V)
0.30
0.25
Typ. 25C
0.20
0.15
Min. -40C
0.10
0.05
0.00
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
DS41326E-page 103
PIC16F526
FIGURE 15-13:
3.5
3.0
Max. -40C
Typ. 25C
2.5
Min. 125C
VOH (V)
2.0
1.5
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
FIGURE 15-14:
(VDD = 5.0V)
VOH vs. IOH OVER TEMPERATURE
(
,
)
5.5
5.0
Max. -40C
Typ. 25C
VOH (V)
4.5
Min. 125C
4.0
3.5
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
DS41326E-page 104
PIC16F526
FIGURE 15-15:
1.7
1.5
VIN (V)
1.3
Typ. 25C
1.1
Min. 125C
0.9
0.7
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 15-16:
4.0
VIH Max. 125C
3.5
VIN (V)
3.0
2.5
2.0
VIL Max. -40C
1.5
1.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41326E-page 105
PIC16F526
FIGURE 15-17:
45
40
35
Max. 125C
DRT (ms)
30
25
Max. 85C
20
Typical. 25C
15
Min. -40C
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
Note:
DS41326E-page 106
PIC16F526
16.0
PACKAGING INFORMATION
16.1
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
PIC16F526
-I/PG e3 0215
0410017
Example
PIC16F526-E
/SLG0125
0431017
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example
16F526-I
0431
017
XXXXXXXX
YYWW
NNN
Example
16-Lead QFN
MG1
0431
017
XXX
YYWW
NNN
TABLE 16-1:
Part Number
Marking
PIC16F526-I/MG
MG1
PIC16F526-E/MG
MG2
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PIC device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS41326E-page 107
PIC16F526
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PIC16F526
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DS41326E-page 110
PIC16F526
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DS41326E-page 111
PIC16F526
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41326E-page 112
PIC16F526
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41326E-page 113
PIC16F526
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41326E-page 114
PIC16F526
APPENDIX A:
REVISION HISTORY
DS41326E-page 115
PIC16F526
NOTES:
DS41326E-page 116
PIC16F526
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
DS41326E-page 117
PIC16F526
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To:
RE:
Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16F526
N
Literature Number: DS41326E
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS41326E-page 118
PIC16F526
INDEX
A
A/D
Specifications.............................................................. 89
ALU ..................................................................................... 11
Assembler
MPASM Assembler..................................................... 80
B
Block Diagram
Comparator for the PIC16F526................................... 65
On-Chip Reset Circuit ................................................. 51
Timer0......................................................................... 37
TMR0/WDT Prescaler................................................. 41
Watchdog Timer.......................................................... 54
Brown-Out Protection Circuit .............................................. 55
C
C Compilers
MPLAB C18 ................................................................ 80
Carry ................................................................................... 11
Clock Divisors ..................................................................... 59
Clocking Scheme ................................................................ 14
Code Protection ............................................................ 43, 57
CONFIG1 Register.............................................................. 44
Configuration Bits................................................................ 43
Customer Change Notification Service ............................. 115
Customer Notification Service........................................... 115
Customer Support ............................................................. 115
D
Data Memory (SRAM and FSRs)
Register File Map.................................................. 16, 17
DC and AC Characteristics ................................................. 97
Graphs and Tables ..................................................... 97
Development Support ......................................................... 79
Digit Carry ........................................................................... 11
E
Errata .................................................................................... 5
F
Flash Data Memory Control ................................................ 23
FSR ..................................................................................... 22
Fuses. See Configuration Bits
I
I/O Interfacing ..................................................................... 29
I/O Ports .............................................................................. 27
I/O Programming Considerations........................................ 36
ID Locations .................................................................. 43, 57
INDF.................................................................................... 22
Indirect Data Addressing..................................................... 22
Instruction Cycle ................................................................. 14
Instruction Flow/Pipelining .................................................. 14
Instruction Set Summary..................................................... 72
Internet Address................................................................ 115
L
Loading of PC ..................................................................... 21
M
Memory Organization.......................................................... 15
Memory Map ............................................................... 15
PIC16F526.................................................................. 15
O
Option Register................................................................... 19
OSC selection..................................................................... 43
OSCCAL Register............................................................... 20
Oscillator Configurations..................................................... 45
Oscillator Types
HS............................................................................... 45
LP ............................................................................... 45
RC .............................................................................. 45
XT ............................................................................... 45
P
PIC16F526 Device Varieties................................................. 9
POR
Device Reset Timer (DRT) ................................... 43, 53
PD............................................................................... 55
Power-on Reset (POR)............................................... 43
TO............................................................................... 55
PORTB ............................................................................... 27
PORTC ............................................................................... 27
Power-down Mode.............................................................. 56
Prescaler ............................................................................ 40
Program Counter ................................................................ 21
Q
Q cycles .............................................................................. 14
R
RC Oscillator....................................................................... 46
Reader Response............................................................. 116
Read-Modify-Write.............................................................. 36
Registers
CONFIG1 (Configuration Word Register 1)................ 44
Special Function ......................................................... 16
Reset .................................................................................. 43
S
Sleep ............................................................................ 43, 56
Software Simulator (MPLAB SIM) ...................................... 81
Special ................................................................................ 17
Special Features of the CPU .............................................. 43
Special Function Registers ........................................... 16, 17
Stack................................................................................... 21
STATUS register................................................................. 55
Status Register ............................................................. 11, 18
T
Timer0
Timer0 ........................................................................ 37
Timer0 (TMR0) Module .............................................. 37
TMR0 with External Clock .......................................... 39
Timing Diagrams and Specifications .................................. 91
Timing Parameter Symbology and Load Conditions .......... 90
TRIS Register ..................................................................... 27
DS41326E-page 119
PIC16F526
W
Wake-up from Sleep ........................................................... 56
Watchdog Timer (WDT) ................................................ 43, 53
Period.......................................................................... 53
Programming Considerations ..................................... 53
WWW Address.................................................................. 115
WWW, On-Line Support........................................................ 5
Z
Zero bit ................................................................................ 11
DS41326E-page 120
PIC16F526
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
PIC16F526
PIC16F526T(1)
Temperature
Range:
I
E
=
=
Package:
P
SL
ST
MG
Pattern:
Special Requirements
c)
d)
Plastic (PDIP)(2)
14L Small Outline, 3.90 mm (SOIC)(2)
Thin Shrink Small Outline (TSSOP)(2)
16-Lead 3x3 (QFN)(2)
Note 1:
2:
DS41326E-page 121
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS41326E-page 122