Errata for IEEE Standard 421.

5-2005

IEEE Recommended Practice for

Excitation System Models for
Power System Stability Studies
June 28, 2008
The following errata were compiled over the past two years by the Performance and
Modeling Working Group of the Excitation Systems Subcommittee of the Energy
Development and Power Generating Committee.
1. DC1A, DC2A, DC3A diagrams show a lower limit symbol on exciter (TE) block, but
there is no value or parameter name associated with it. The limits were removed to be
consistent with the previous versions of the standard.
2. Fig. E.6 (non-windup on lag-lead block) The multiplier for z should be (T2/T1 1)
instead of (T1/T2 1). Also, the limits A and B have been reversed to be consistent
with the logic given below the figure.
3. The AC7B block diagram should have "sTE" in the denominator instead of "1 + sTE" to be
consistent with the other AC models.
4. In Annex H, the two AC7B sample data sets are missing parameters which have been
added.
5. The model ST5B block diagram was modified in one of the last revisions before approval
of the Standard. The model as approved is attached.
6. The type PSS2B description has been updated to add the omitted explanation of the
bypassed washout block with time constant TW4. The washout block is also added to
Annex E to note that use of 0 in a washout block indicates that it should be bypassed
(block output equal to its input). The sample data have been updated with this note.
7. The ST7B model block diagram and descriptive text have been corrected
8. The definition of the limit signal w has been added to Annex E, Figure E.8.
9. the final version of this errata document is to be posted to
http://standards.ieee.org/reading/ieee/updates/errata/index.html

Errata List:
1. Limits on DC exciter removed:

Fig. 5.1 Type DC1A - DC Commutator Exciter

Fig. 5.2 Type DC2A - DC Commutator Exciter with Bus-Fed Regulator

Fig. 5.3 Type DC3A - DC Commutator Exciter with Non-Continuously Acting Regulators

2. Fig. E.6 (non-windup on lag-lead block) drawing corrections:

T2>T1,T1>0,T2>0
Ify>A,thenx=A
Ify<B,thenx=B
IfA>y>B,thenx=y
Fig. E6 Lag-Lead with Non-windup Limiter

3. AC7B drawing change to main exciter TE block:

Fig. 6.7 Type AC7B Alternator-Rectifier Excitation System

4. Added missing sample data for AC7B model.

H.11 Sample Data for a Type AC7B Excitation System

DataSet1.AlternatorRectifierExcitationSystem
TR
0.0
VAmax 1.0
KPR 4.24
VAmin 0.95
KIR 4.24
KP
4.96
KDR 0.0
KL
10.
TDR 0.0
KF1 0.212
VRmax 5.79
KF2 0.0
VRmin 5.79
KF3 0.0
KPA 65.36
TF
1.0
KIA 59.69
KC
0.18

KD
0.02
KE
1.0
TE
1.1
VFEmax 6.9
VEmin 0.5
VE0.75max 3.02
SE0.75max 0.075
VEmax 6.30
SEmax 0.44

DataSet2.DCExciter
TR
0.0
KPR 170.0
KIR 130.0
KDR 60.0
TDR 0.03
VRmax 10.0
VRmin 0.0
KPA 1.0
KIA 0.0

KD
0.0
KE
1.0
TE
1.0
VFEmax 99.
VEmin 99
VE0.75max 3.38
SE0.75max 1.36
VEmax 4.5
SEmax 1.5

VAmax
VAmin
KP
KL
KF1
KF2
KF3
TF
KC

10.0
0.0
1.0
0.0
0.0
0.0
0.0
1.0
0.0

5. ST5B corrected drawing

+

X>0

X>0
VRMAX
KR

VOEL
VUEL
VC

VREF

HV
Gate

LV
Gate

VS

1+sTC1 1+sTC2
1+sTB1 1+sTB2
VRMIN
KR

VRMAX
KR

1+sTUC1 1+sTUC2
1+sTUB1 1+sTUB2
VRMIN
KR

VRMAX
KR
VRMIN

VRMAX* VT

1
1+sT1

EFD

VRMAX
KR

VRMIN*VT
KC

IFD

1+sTOC1 1+sTOC2
1+sTOB1 1+sTOB2
VRMIN
KR

Fig. 7.5 Type ST5B Static Potential Source Excitation System

6. Corrected omissions to PSS2B text and sample data:

8.2 Type PSS2B Power System Stabilizer Model
Forthefirsttypeofdualinputstabilizer,KS3wouldnormallybe1 , TW4 would be bypassed (its output
set equal to its input), and KS2 would be equal to T7/2H where H is the inertia constant of the
synchronousmachine.

E.5 Washout Block

Ablockdiagramrepresentationforawashout(highpassfilter)isprovidedinFig.E9.AsappliedinthePSS2B
stabilizer,somewashoutsmaynotbeused.Inthiscase,theblockshouldbebypassed(itsoutputsetequaltoits
input).Bypassingtheblockisdenotedbysettingitstimeconstant,TW,equaltozero.

IfTW=0,THENy=u
Fig. E9 Washout Block

H.10 Sample Data for a Type AC6A Excitation System

TypePSS2AStabilizerParametersWithSpeedandElectricalPowerInputs
KS1=20
M=2
KS2=1.13=T7/2H
N=4
KS3=1
VSTMAX=0.20
T1=T3=0.16
VSTMIN=0.066
T2=T4=0.02
T6=0
H=synchronousmachineinertiaconstant
T7=10.0
TW1=TW2=TW3=10
T8=0.3
T9=0.15
TW4=0[block bypassed; block output equal to input]

H.13 Sample Data for a Type ST1A Excitation System

Stabilizer
TypePSS2AwithSpeedDeviationandElectricalPowerasInputs
VSI1=speedinputinpu
M=2
VSI2=electricalpowerinputinpu
N=4
KS1=20
VSTMAX=0.20
KS2=1.13=T7/2H
VSTMIN=0.066
KS3=1
T6=0
T1=T3=0.16
T7=10
T2=T4=0.02
T8=0.3
H=synchronousmachineinertiaconstant
T9=0.15
TW1=TW2=TW3=10
Tw4=0[block bypassed; block output equal to input]

H.16 Sample Data for a Type ST4B Potential or Compound-Source Controlled

Rectifier Excitation System
Stabilizer
KS1=20.0
KS2=0.99
KS3=1.0
T1=0.15
T2=0.025
T3=0.15
T4=0.02

TypePSS2B
T7=10.0
T8=0.5
T9=0.1
T10=0.0
T11=0.033
N=1
M=5

VSI1=Speedpu
VSI2=ElectricalPowerpu
VSTMAX=0.1
VSTMIN=0.1
TW1=TW2=TW3=10.0
TW4=0.0

[block bypassed; block

T6=0.0

output equal to input]

7. Corrections to Type ST7B block diagram and description:

7.7 Type ST7B Excitation System Model
TheAVRincludestheappropriateinputsonitsreferenceforanOverExcitationLimiter(OEL1)andUnder
ExcitationLimiter(UEL).Theselimitations,whentheyworkatvoltagereferencelevel,keepthePSS(VS
signal from type PSS1A, PSS2A or PSS2B) in operation. However, the UEL Limitation can also be
transferredtotheHVgateactingontheoutputsignal.InadditiontheoutputsignalpassesthroughaLV
gateforaCeilingOverExcitationLimiter(OEL2).
Allcontrolloopsinthediagram,includinglimitationfunctions,arebuilttoobtainanonwindupbehavior
ofanyintegrator(seeAnnexE).SampledataforthemodelareprovidedinAnnexH.
VC

VOEL1

+
VREF

VS

VMAX

(ALTERNATE)

1+sTG
1+sTF

LV
GATE

HV
GATE

VREF_FB

VMIN
VUEL
(ALTERNATE)

(ALTERNATE)

VOEL2
1+sTC
1+sTB

LV
GATE

HV
GATE

KPA

VUEL

LV
GATE

+
VRMIN.VT

VRMAX.VT
HV
GATE

VR

VRMIN.VT

VRMAX.VT

+
KL

KIA
1+sTIA

KH

Fig. 7.7 Type ST7B Static Potential Source Excitation System

E.4 Proportional Integral block

RevisionoftextforFig.E8:
TheST7BmodelimplementsaNonWindupProportionalIntegralfunctionasrepresentedonFigE8.Ifa
nonlinearityisacting(thatmeanseitherasaturationisreachedoraLVorHVcomparatorimposesanother

signalwcalculatedbyanotherfunction,forexampleanoverorunderexcitationlimiterastheoutput
signal),thenthelowpassfilteroutputfollowsthePIoutputsignal,insuringanonwindupbehaviorofthe
PIfunctionintegrator.TheinputsignalofthelowpassfilteroftimeconstantTiisthePIoutputsignal,
afterapplicationofallnonlinearitytreatments.
A
u

KP +

KI
s

KP

LV or HV
GATE

KP
with TI =
KI

B
1
1+sTI

Fig. E8 Non-Windup Proportional Integral Block

ThePIcontrollerisrealizedaccordingtothefollowingprinciple:
U

KP

non-linearities

1
1+sTI

Uistheerrorsignalattheinputofthefunction.Sisitsoutput.
Thenonlinearitiescanbeasaturationoftheoutputsignal,oraHighoraLowValueGatewithanyother
signal.
Ifnononlinearitiesareacting,thetransferfunctioncanbecalculatedasfollow:

S Kp U S

1
1 s TI

1
S Kp U
1 s TI

S Kp

1 s TI
U
s TI

Thetransferfunctionofthisdiagramis:

1 s TI
S
Kp
U
s TI
ThenthisdiagramrepresentsaPIcontroller.Thechosenrepresentationensuresanonwindupbehaviorof
theintegrator.